CN1246219A - 可编程晶体振荡器 - Google Patents
可编程晶体振荡器 Download PDFInfo
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- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
- H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
- H03B5/36—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
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- H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
- H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
- H03B5/36—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
- H03B5/366—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device and comprising means for varying the frequency by a variable voltage or current
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- H03B2201/00—Aspects of oscillators relating to varying the frequency of the oscillations
- H03B2201/02—Varying the frequency of the oscillations by electronic means
- H03B2201/025—Varying the frequency of the oscillations by electronic means the means being an electronic switch for switching in or out oscillator elements
- H03B2201/0266—Varying the frequency of the oscillations by electronic means the means being an electronic switch for switching in or out oscillator elements the means comprising a transistor
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- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
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- H03J2200/10—Tuning of a resonator by means of digitally controlled capacitor bank
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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Abstract
本发明提供一种可编程晶体振荡器,它具有存储器,用于存储频率定义参数。典型地,这些中的一个参数用于对耦合到晶体的可调节容性负载电路进行编程,由此调节晶体的源频率。另外的参数用于对锁相环电路的输出频率进行编程,所述锁相环路被耦合以接收被调节的源频率。还可以用其它的参数来对锁相环电路的输出频率进行分频,以提供指定的输出频率。可将振荡器制造成一般的可编程晶体振荡器而不需考虑输出频率,然后高速编程,以高的精度产生顾客所指定的输出频率。
Description
背景技术
本发明涉及一种可编程晶体的振荡器。具体说,本发明尤其针对具有耦合于晶体的可调节容性负载电路的可编程晶体振荡器。
晶体振荡器广泛使用于产生计时信号给电子硬件,诸如计算机、仪表和电信设备。晶体振荡器典型地包含石英晶体和振荡器电路,它电气激励晶体,以便在由晶体的物理特性决定的谐振频率下产生振荡信号。振荡器电路或分立的输出电路(缓冲器)将振荡信号的波形控制成电子硬件可接受的计时脉冲串。
计时频率由电子硬件厂商指定,由此它在宽的频率范围内变化。但是,晶体的谐振频率由其物理特性,即尺寸、形状、晶体结构等决定。修整晶体的谐振频率可以通过选择镀敷在晶体表面的金属来实现。因此,晶体振荡器的制造是个费时费钱的复杂过程。这样,晶体振荡器的供应者便采购大量的晶体振荡器,使它们制造成具有各种各样的标准输出频率。但是,如果顾客需要自定的频率,则厂家通常必需“从零开始”,通过将晶锭切成特定尺寸的晶体片,然后使晶体片经受许多处理步骤(研磨、腐蚀和镀敷),所有这些都被设计成用以实现顾客自定的输出频率。顾客自定的晶体振荡器是高价的,并需要长的制造投产准备阶段(数月)。
由于事实上所有晶体都能够振动,故制造效率非常高的。但是,如果晶体的谐振频率无法修整得满足一个顾客的频率指定,则通常将晶体编入产品清单,希望能用于满足另一个顾客的频率指定。在顾客自定的晶体振荡器的情况下,厂商生产过量的自定晶体,以确保能满足顾客对(输出频率以及质量这两者)需要的晶体的足够批量乃非罕见。于是将过剩的晶体振荡器列入产品清单。保持大量的晶体产品清单表示重大的制造损失。
发明概述
相容于本发明的系统和方法通过提供计射电路来解决传统方法中的一些缺点,该计费电路包括:用以产生源频率晶体的,耦合到晶体的振荡器电路以及耦合到晶体的可编程负载电路。将倍频器电路耦合到振荡器电路,以接收经过调节的源频率。另外,还包含编程电路,以提供第一编程数据给可编程负载电路来调节晶体的源频率,以及第二编程数据给倍频器电路。倍频器电路又提供输出频率,该输出频率等于经过调节的源频率和由第二编程数据指定的倍增因子的乘积。
本发明的优点将在以下描述中部分地提出,并从描述中显而易见,或可通过本发明的实践加以知道。另外,将借助于所附权利要求具体指出的诸元件和组合,来实现和获取本发明的优点。
应该理解,上述一般的描述和下面详细的描述只是示范性和解释性的,正如权利要求那样并非对本发明的限制。
这里所结合并构成本说明书一部分的附图描述了本发明的实施例,并且与描述部分一起用于解释本发明的原理。
附图概述
图1是描述根据本发明实施例一可编程晶体振荡器封装的示范性封装配置的平面图;
图2是根据本发明实施例一可编程晶体振荡器的方块图;
图3是包含在图2可编程晶体振荡器中的可编程容性负载电路的详细电路示意图;及
图4是包含在图2可编程晶体振荡器中的锁相环路电路示意图。
最佳实施例
现在将对本发明目前的较佳实施例进行详细描述,它的一个例子在附图中有描述。只要可能,在所有的附图中将使用相同的标号指示相同或类似的部件。
按本发明,可编程晶体振荡器设置有存储器,用于存储输出频率定义参数。典型地,将这些参数中的一个用于对耦合到晶体的可调容性负载电路进行编程,由此调节晶体的源(谐振)频率。将另外的参数用于对被耦合以接收经过调节的源频率的锁相环电路的输出频率进行编程。结果,通过将适当的参数作为编程数据存储在存储器中,并根据这些参数进行编程,几乎所有能够振荡的晶体都可以用于根据本发明的晶体振荡器中,随后可以对它们编程,以产生宽范围的特定的输出频率。另外,可以迅速而低成本地进行这样的频率编程。
在图1中根据本发明描述了可编程晶体振荡器的实施例。该振荡器20可以生产成各种各样的工业标准尺寸,并且根据振荡器拟在其具体应用中的安装方式而有两种基本封装配置,即引脚穿孔和表面安装(SMD)。这里描述的实施例具有六个输入/输出(I/O)终端,它们由标记时钟脉冲终端21、专用程序输入终端22、接地(VSS)终端23、电源(VDD)终端24、标记输出终端25和时钟信号输出(Fout)/编程时钟脉冲输入(CLKin)终端26构成。如下面将详细描述的,将编程数据在由提供给终端26的时钟脉冲(CLKin)控制的时刻通过终端22送入。
当通过编程数据对可编程晶体振荡器20编程时,它在终端26上产生时钟信号输出(Fout),它的编程频率符合顾客指定的目标频率(在例如380KHz到175MHz的宽范围中的任何地方),并且具有±100ppm(parts per million)或更好的精度。以百分比表示,100ppm等于目标频率的±0.01%。根据本发明的一个特点,晶体振荡器20包括可编程只读存储器(PROM)50,(图2),在其中可把以顾客数据形式编程的数据在由厂商对振荡器进行编程的时刻提供给终端26的时钟脉冲(CLKin)所影响的定时控制下,经由程序终端22送入。此后,顾客数据可以通过将时钟脉冲提供给终端21而在终端25上读出顾客数据。如果将此标记数据特性省掉,则图1所示的晶体振荡器封装配置可减少到4个终端。
由图2的方块图更为详细地描述的可编程晶体振荡器20包括电气连接在集成电路芯片上的压脚31和32之间的晶体坯30,用于由振荡器电路34加以激励,并由此产生源振荡信号。这个振荡器电路包含对电阻器、电容器和反相器诸元件的配置,这些元件在晶体振荡器领域中均为熟知的,因此在这里不需描述。在振荡器电路34的输出端作为参考频率信号Fref出现的源振荡信号的频率大半由晶体片的物理特性决定。
根据本发明的特点,可编程晶体振荡器20适应宽广范围的源频率,例如5.6396MHz到27.3010MHz。即即,源频率可以在这个范围以内从晶体到晶体发生变化,而并不危及晶体振荡器20待要进行编程的能力,以输出任何由顾客指定的在例如380Khz-175MHz的范围以内的目标频率的时钟信号,并具有至少100ppm的工业标准精度。实际上,不同的晶体源频率不需要在编程之前预先知道。
仍然参照图2,振荡器电路34输出提供给倍频器36(图4中描述更为详细)的参考频率Fref。倍频器以频率FPLL输出时钟信号到分频器38,它将频率FPLL除以从编程网络42接收到的可编程参数N,以产生符合顾客指定的编程频率的时钟信号Fout。Fout和Fref信号作为分开的输入提供给多路复用器40。在编程网络42中的程序控制逻辑的控制下,利用路径43,多路复用器40通过输出缓冲器44输出时钟信号Fout或Fref输出到终端26上。
根据本发明的另一个特性,如果必要,晶体振荡器还包含一对可编程的负载电路46和48,以调节晶体30上的容性负载,转而又将晶体的源频率拉至有助于晶体振荡器20的最佳编程的频率范围以内,以不仅得到由顾客指定的输出频率精度,而且也得到有助于倍频器36稳定操作的低锁相环路频率。
图3详细描述了负载电路46和48。负载电路46和48可以分别包含例如多个电容器771到77n和871到87n。电容器771到77n分别连接在地和第一开关元件或晶体管781到78n的源极之间,而电容器871到87n则分别连接到地和第二开关元件或晶体管881到88n的源极之间。如从图3中还可看到的那样,每一个晶体管781到78n的栅极由来自编程网络42的输出端761到76n中相应的一个输出端加以连接,这在图2中集中地表示为76。这些晶体管的漏极共同连接到源频率输入路径79,该路径79连接晶体压脚31至振荡器电路34。按照类似的方式,将栅极分别连接到来自编程网络42的输出端861到86n,(在图2中表示为86),而晶体管881到88n的漏极则共同连接到源频率输入路径89,后者连接将晶体压脚32到振荡器电路34。此外,设置固定的电容器75和85(每一个都具有例如35pf的电容)作为正常晶体坯30的额定电容负载。
响应于存储器网络42中所存储的参数,将选出的输出路径761到76n和861到86n驱动到高电平上,以激励或开通晶体管781到78n和881到88n中相应的一个。结果,使与被激励的晶体管相关联的那些电容器771到77n和871到87n耦合到源频率输入路径79和89中的一个。由此,可根据存储在存储器网络42中的参数设置晶体坯30的容性负载,且因此可将晶体源频率“拉”到所需的范围以内,使总的输出频率调节由信频器电路36加以完成。如果不需要晶体频率的“拉动”,则不激励晶体管781到78n和881到88n。
每一个电容器771到77n和871到87n都可以具有例如5pf的电容。另外,电容器771到77n和871到87n对称地分别连接到源频率输入路径79和89,从而对于每一个连接到源频率输入路径79的电容器771到77n,使电容器871到87n中相应的一个连接到源频率输入路径89。因此,电容器771到77n和871到87n的许多对(来自每一组电容器771到77n和871到87n中的一个)分别连接到输入路径79和89,而与每一对电容器相关联的电容电容增量变化可以是2.5pf。正如前面提到的那样,该电容负载调节对于按需使晶体的源频率拉上或拉下,以调节参考时钟信号频率Fref适合于晶体振荡器20的最佳频率编程数值乃是有效的。
正如图4所见,倍频器36包括分频器52,它将参考频率Fref除以存储在编程网络42中的可编程参数Q,并将最终时钟信号频率提供给锁相环路(PLL)的相位探测器54。锁相环路包括电荷泵56、环路滤波器60和压控振荡器58,压控振荡器58产生送到图2中分频器38的时钟信号频率FPLL。这个时钟信号频率FPLL还通过分频器64被反馈送回相位探测器54的第二个输入端。分频器64将FPLL频率除以也存储在编程网络42内的可编程参数P。
在操作中,参数Q和P(将在下面详细说明)分别从程序网络42提供给程序分频器电路52和64。由此参考频率Fref在分频器电路52中被除以编程参数Q。如上所述,Fref响应于晶体30的源频率,并且因此而典型地处于5.64MHz到27.3MHz的范围内。如果Q是在132到639范围以内的整数,则商Fref/Q(即分频器52的输出)可以落在32KHz到50KHz的范围内,而不必考虑晶体的源频率。商Fref/Q是图4所示锁相环电路的环路频率。
将环路频率连同分频器64的输出提供给相位探测器54,它典型地输出频率大致上等于分频器52和64的输出频率之间的差的控制信号。然后将控制信号提供给电荷泵56,它输出与控制信号的频率成比例的DC信号。在电荷泵56的输出端设置环路滤波器60,以限定锁相环路的响应。
然后DC信号提供给压控振荡器(VCO)58,它输出频率由DC信号的电势控制的时钟信号FPLL。再后将时钟信号FPLL通过P分频器64反馈送回相位探测器54的输入端中的一个。相应地,按照这样的锁相环路安排,FPLL等于乘以可编程P的环路频率的积,P是在2048到4097的范围内的一个整数,从而使FPLL在87.5MHz到175MHz范围以内。时钟信号FPLL还被提供给分频器电路38(见图2),它在该分频器电路38处被除以下面从编程网络42取得的整数参数:1、2、4、8、16、32、64、128或256中的任何一个编程参数,然后通过多路复用器40和输出缓冲器44作为频率Fout输出。
相位探测器54、电荷泵56、环路滤波器60和VCO58均旨在代表应用于相位锁定两个输入信号电路的宽广类别,这在现有技术中是熟知的,故将不进一步描述。
通常,输出频率FPLL和Fref满足下面的等式:
FPLL=Fref(P/Q)
因此,FPLL是环路频率的倍数。相应地,对于相对低的环路频率,FPLL最后可以小的环路频率增量进行精细调节。如果环路频率太低,则锁相环路可能变得不稳定而导致抖动。因此,已经决定最佳环路频率范围是32KHz到50KHz,较好的范围是42.395KHz到43.059KHz。还可以使用在此范围以上的环路频率(但小于200KHz),其输出频率分辨率比通过传统的晶体振荡器PLL得到的更好。
但是,用于数字电路定时应用的传统的晶体振荡器锁相环路在明显更高的环路频率,也即,大于200KHz下工作。在这些频率下,这样一种传统的晶体振荡器无法获得与本发明可得到的同样高的频率分辨率。典型地,例如多晶硅电容器和其它低噪声元件结合在本发明所使用的锁相环路中,从而使它可在42.395KHz到43.059KHz较佳范围内的环路频率下工作,而且有相对小的抖动。
正如在申请人相关的专利申请(题为“包括顾客指定频率编程晶体振荡器用策略定位中心在内的全球销售后勤网络”,序号为08/795,980,于此同时提出,且其内容在这里通过引用加以结合)中更为详细地描述的那样,仅仅P、Q和N诸参数可能不足以得到足够接近于指定目标频率(例如在100parts permillion(100ppm以内))的输出频率。在这种情况下,如上所述,拉动晶体源频率,以使得到的输出频率落入可接受的精度范围以内。
由此,可把根据本发明可的编程晶体振荡器用来产生基于晶体源频率的宽广范围的输出频率。输出频率通过用可编程电容负载调节源频率,并以相对低的环路频率操作锁相环电路而得。因此,对于任何具有源频率例如在5.6396HMz到27.3010MHz宽广范围内的晶体,通过单单将合适的P、Q和N以及晶体拉动参数存储在编程网络42中所包含的PROM中,均可获得在指定目标频率的100ppm或更小,以内的晶体振荡器输出频率。如在引用的待批申请中所指出的那样,可把晶体振荡器20制造成一般的可编程晶体振荡器而不用考虑顾客所指定的输出频率,并简单地大约经几秒钟的编程来产生根据顾客指定的输出频率。因此,不需要制造多个标准频率的晶体,由此使制造过程简化,加快并降低成本。这样便可大大减少从顾客购货定单到产品交割的投产准备阶段。
虽然文中已用标准微机处理型晶体坯(它在5.6396MHz到27.3010MHz的范围内振荡)描述了本发明,但如上所述,将会了解到,本发明可以使用工业标准的钟表晶体(大量生产,以32.768KHz振荡)来实现。在这种情况下,可以得到所想要的低锁相环路频率,而无需图4倍频器36中的分频器52。于是晶体坯30将实际上以直接驱动的关系与锁相环电路相耦合。依仗于大量生产,钟表晶体的成本明显低于微机处理型晶体,故在生产根据本发明的可编程晶体振荡器时,可以实现进一步的节约。
对于熟悉现有技术的人,很明显,可对本发明的可编程晶体振荡器以及这种可编程晶体振荡器的结构作出各种修改和变化,而不背离本发明的范围或主旨。
从这里所揭示的本发明的说明书和实践考虑,对于熟悉本领域的人将会明显本发明的其它实施例。所希望的是,说明书和例子只是示例性的,而本发明的真正的范围和主旨则由下面的权利要求加以指出。
Claims (26)
1.一种计时电路,其特征在于包含:
用于产生源频率的晶体;
耦合到所述晶体的可编程负载电路;
耦合用于接收所述源频率的振荡器电路;
耦合到所述振荡器电路用于接收所述源频率的倍频器电路;及
编程电路,配置来提供第一编程数据给所述可编程负载电路,以调节所述源频率,并提供第二编程数据提供给所述倍频器电路,从而使所述倍频器电路提供输出频率,它大致上等于所述调节源频率与由所述第二编程数据所指定倍增因。
2.如权利要求1所述的计时电路,其特征在于所述可编程负载电路是可编程的容性负载电路。
3.如权利要求2所述的计时电路,其特征在于所述源频率通过耦合到所述晶体的源频率路径而加以提供,所述可编程容性负载电路包含:
多个电容器,把被选的所述多个电容器之一耦合到所述源频率的路路。
4.如权利要求3所述的计时电路,其特征在于所述可编程容性负载电路还包含:
多个开关元件,每一个都具有共同连接到所述源频率路径的第一终端,以及耦合到所述多个电容器中相应之一的第二端。
5.如权利要求4所述的计时电路,其特征在于所述编程电路根据存储在那里的所述第一编程数据产生多个输出信号,所述多个输出信号提供给所述可编程容性负载电路,以激励所述多个开关元件中选出的一个开关元件,从而使所述电容器的相应之一连接到所述源频率的路径。
6.如权利要求4所述的计时电路,其特征在于所述多个开关元件的每一个都包含一个MOS晶体管。
7.如权利要求1所述的计时电路,其特征在于所述倍频器包含锁相环电路。
8.如权利要求1所述的计时电路,其特征在于所述第二编程数据包含第一参数P和第二参数Q,所述输出频率(Fout)和所述调节源频率(Fadj)满足:
Fout=Fadj(P/Q)
9.如权利要求7所述的计时电路,其特征在于所述倍频器环电路包含:
第一分频器,用于将所述经调节的源频率除以所述第二编程数据的第一参数,以产生第一频率;
包含在所述锁相环电路中的第二分频器,用于将所述输出频率除以所述第二编程数据的第二参数,以产生第二频率;及
包含在所述锁相环电路中并被耦合以接收所述第一和第二频率的探测器,所述探测器响应于所述第一和第二频率而输出控制信号,用以控制所述输出频率的产生。
10.如权利要求9所述的计时电路,其特征在于还包含:
第三分频器电路,耦合到所述锁相环电路和所述编程电路,用于将所述输出频率除以存储在所述编程电路中的所述第二编程数据的第三参数。
11.如权利要求7所述的计时电路,其特征在于提供所述被调节的源频率给分频器电路,以产生小于200Khz的所述锁相环电路的环路频率。
12.如权利要求11所述的计时电路,其特征在于所述环路频率在32KHz到50Khz的范围以内。
13.如权利要求11所述的计时电路,其特征在于所述环路频率在42.395KHz到43.058KHz的范围以内。
14.如权利要求9所述的计时电路,其特征在于所述探测器根据所述一和第二频率之间的相位差,输出所述控制信号,所述锁相环电路还包含:
电荷泵电路,接收所述控制信号以及相应地输出DC信号;
环路滤波器;及
通过所述环路滤波器耦合到所述电荷泵的压控振荡器,所述压控振荡器在所述DC信号的控制下产生所述输出频率。
15.如权利要求1所述的计时电路,其特征在于还包含专用的外部编程序端,用于送入所述第一和第二编程数据,以存储在包含在所述编程电路中的可编程只读存储器中。
16.一种可编程计时电路,其特征在于包含:晶体;
振荡器电路,它被耦合以激励所述晶体到产生源频率;
耦合到所述晶体,并配置得可对所需负载电容进行编程的容性负载电路,以便选择性地调节所述源频率;及
耦合到所述振荡器电路的锁相环电路,所述锁相环电路产生输出频率,作为所述被调节的源频率和倍增因子的乘积。
17.如权利要求16所述的可编程计时电路,其特征在于还包含:
存储器,耦合到所述锁相环电路和所述可编程容性负载电路,用于存储编程数据,所述编程数据包含第一参数,用于将所述容性负载电路编程到所需负载电容,以及第二参数,用于将所述锁相环电路编程到所述倍增因子。
18.如权利要求17所述的可编程计时电路,其特征在于所述存储器包含PROM。
19.如权利要求17所述的可编程计时电路,其特征在于所述晶体通过输入路径耦合到所述振荡器电路,所述可编程容性负载电路包含:
多个电容器;及
多个开关元件,每一个所述开关元件具有耦合到所述多个电容器中相应的一个电容器的第一终端,以及耦合到所述输入路径的第二终端,所述存储器提供所述第一参数作为多个信号,以激励所述多个开关元件中选出的一个开关元件,由此将所述多个电容器中所述相应的一个电容器耦合到所述输入路径。
20.如权利要求19所述的可编程计时电路,其特征在于所述多个开关元件中每一个都包含MOS晶体管。
21.如权利要求17所述的可编程计时电路,其特征在于还包含专用编程终端,它提供用于存储在所述存储器中所述编程数据的外部入口。
22.一种可编程晶体振荡器,其特征在于包含:
具有关联源频率的晶体;
振荡器电路;
输合所述晶体到所述振荡器电路的的输入路径;
耦合到所述输入路径的可编程容性负载,用于根据负载参数调节所述源频率;
锁相环电路,被耦合以接收所述经调节的源频率,并相应地产生环路频率,所述锁相环电路将所述环路频率乘以频率参数,以产生想要的输出频率;及
编程电路,耦合到所述可编程容性负载电路以及所述锁相环电路,所述编程电路存储所述负载以及频率参数,以分别编程所述容性负载电路和所述锁相环电路。
23.如权利要求22所述的可编程晶体振荡器,其特征在于所述晶体是工业标准的钟表晶体,它具有本质上为32.768Khz的关联源频率。
24.如权利要求1所述的计时电路,其特征在于还包含:
第一PROM,用于存储标识数据;
编程终端,用于用所述标识数据编程所述第一PROM;及
第一输出终端,用于将所述识别数据从所述第一PROM读出。
25.如权利要求24所述的计时电路,其特征在于还包含:
第二PROM,由通过所述程序终端进入的所述第一和第二编程数据编程;及
第二输出终端,用于输出所述输出频率,并接收时钟脉冲以时钟触发所述识别数据至所述第一PROM中,和时钟触发所述第一和第二编程数据至所述第二PROM中。
26.如权利要求25所述的计时电路,其特征在于还包含第二输入终端,用于接收时钟信号,以从所述第一PROM将所述识别数据读出到所述第一输出终端上。
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US08/795,978 US5952890A (en) | 1997-02-05 | 1997-02-05 | Crystal oscillator programmable with frequency-defining parameters |
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US6664860B2 (en) | 2003-12-16 |
HK1026079A1 (en) | 2000-12-01 |
MY118540A (en) | 2004-12-31 |
EP0958652A1 (en) | 1999-11-24 |
ZA98866B (en) | 1998-08-05 |
AR011624A1 (es) | 2000-08-30 |
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BR9807549A (pt) | 2000-02-15 |
DE69826244T2 (de) | 2005-11-17 |
KR20000070691A (ko) | 2000-11-25 |
US20030122630A1 (en) | 2003-07-03 |
JP2001510657A (ja) | 2001-07-31 |
US20010017573A1 (en) | 2001-08-30 |
US5952890A (en) | 1999-09-14 |
US6188290B1 (en) | 2001-02-13 |
CN1191672C (zh) | 2005-03-02 |
WO1998034338A1 (en) | 1998-08-06 |
DE69826244D1 (de) | 2004-10-21 |
CA2278583A1 (en) | 1998-08-06 |
TW404095B (en) | 2000-09-01 |
AU6050698A (en) | 1998-08-25 |
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