CN1274474A - 集成电路封装用的芯片级球形格栅阵列 - Google Patents

集成电路封装用的芯片级球形格栅阵列 Download PDF

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Publication number
CN1274474A
CN1274474A CN98810000A CN98810000A CN1274474A CN 1274474 A CN1274474 A CN 1274474A CN 98810000 A CN98810000 A CN 98810000A CN 98810000 A CN98810000 A CN 98810000A CN 1274474 A CN1274474 A CN 1274474A
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layer
polymer
circuit
integrated circuit
electronic packaging
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CN98810000A
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R·D·许尔勒
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3M Co
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Minnesota Mining and Manufacturing Co
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Abstract

一种集成电路封装用的芯片级球形格栅阵列,它具有设置在半导体模片与基板之间的非聚合物层或支承结构。非聚合物支承结构的作用是通过降低热应力效应和/或通过降低或消除在集成电路封装中形成空隙而提高电路的可靠性。非聚合物支承结构可以是诸如铜箔的具有足够硬度以允许以条带形式处理芯片级封装的材料。

Description

集成电路封装用的芯片级球形格栅阵列
本申请是1996年12月2日提交的申请No.08/759,253的部分续展申请。
                           发明背景
1.技术领域
本发明总的涉及集成电路的封装，更具体地涉及球形格栅阵列。具体地，本发明涉及采用具有非聚合物支承结构的柔性带的芯片级球形格栅设计。
2.背景技术描述
电子元件尺寸减小和复杂性增大的要求已经推动电子工业生产更小和更复杂的集成电路(IC)。这些相同的趋势已经迫使IC封装具有更小的管脚印刷更多的引线数目和更好的电学和热学性能。与此同时，还要求这些IC封装满足可以接受的可靠性标准。
随着器件尺寸的减小和电路复杂性的相应提高，要求集成电路封装具有更小的管脚印刷(footprint)、更多的引线数目和更高的电学和热性能。同时，还要求IC封装满足可接受的可靠性标准。
球形格栅阵列(BGA)封装是为满足具有更高引线数目和更小管脚印刷的集成电路封装的需要而研制的。BGA封装通常是正方形封装，其终端通常具有从封装的底部突起的焊接球形阵列的形式。这些终端被设计为安装到位于印刷电路板(PCB)或其它合适基板上的多个焊接垫片上。
最近，利用带式自动焊接(TAB)工艺方法和通常由薄聚酰亚胺基板上的铜轨迹组成的柔性电路(有时称为TAB带)已经制备出BGA封装。可以将导电引线叠合在TAB带的一侧和两侧。这种BGA设计常常称为带式BGA(TBGA)。在TBGA设计中，带上的电路具有通过诸如引线焊接和热压焊接或倒装芯片的任何传统方法连接到半导体模片(die)上的引线。如果在带的两侧都存在这一电路，那么，导电通孔可以通过该带从一层电路延伸到另一层。
对于诸如便携式电子元件(蜂窝式电话、磁盘驱动器、寻呼机等)的有些应用，即使BGA封装有时也太大。因此，有时将焊柱(solder bump)直接淀积在IC自身的表面上，用于附着到PCB上(通常称为直接芯片装接或倒装芯片)。然而，这种方法存在许多问题。首先，焊球的淀积需要许多成本高的工艺步骤。此外，通常必须在模片下方淀积一层聚合物底层填料，以使倒装芯片附着到PCB上的可靠性到达可以接受的程度。要求聚合物底层填料是为了降低由于模片的热膨胀较低而PCB的膨胀通常相对很高而引起的热应力(“热失配应力”)。淀积底层填料聚合物是一个代价高的工艺过程，它会使元件丧失返修的能力。因此，如果发现任何缺陷，昂贵的PCB就必须被抛弃。
为了解决与倒装芯片工艺有关的问题，于是研制出另一类BGA封装。可以将这类BGA封装称为芯片级球形格栅阵列或者芯片级封装(CSP)。之所以称为芯片级封装是因为整个封装尺寸与IC自身尺寸相当或者大不了多少。在芯片级封装中，焊球终端通常淀积在半导体模片的下方，以减小封装尺寸。CSP的一个例子是由TESSERA研制的所谓“MICRO BGA”的产品。这一产品由在模片与电路之间有一层软的适应弹性体层(或者弹性体衬垫)的柔性电路组成。这个弹性元件由诸如硅酮之类的聚合物材料构成，厚度通常约为125-175微米(5-7密耳)。弹性体的一个用途是通过使模片与PCB之间的热失配应力减至最小而获得合适的可靠性，不需要昂贵的底层填料的材料。
尽管当前的芯片级封装设计改善了电路板的空间利用和易于表面安装组件，但是，这些产品也存在许多缺点。首先，通常难以找到满足低吸湿、低排气和能够承受工业中常用的清洗溶剂等工业要求的合适的弹性体材料。例如，已知硅酮被一些常用的清洗溶剂断损，聚合物材料总是会吸湿和放潮气。如果吸湿太高，那么，在回流温度下这一湿气的快速排放将会引起在元件界面上形成空隙，甚至使封装破裂。例如，湿气可以从带中的聚合物材料中释放出来并陷入到模片附着粘合剂中。当这一陷入的湿气在电路板组件加热操作期间膨胀时则会形成空隙，通常会引起裂纹和封装失效。形成的这种空隙在回流固定到PCB期间可能会特别剧烈。
芯片级封装设计的另一个重要挑战是把弹性体固定到柔性带上的工艺方法。常用的一种方法是检取弹性体衬垫和将其放置在各个位置上，而另一种方法是丝网印刷流体聚合物，接着进行固化。在这两种情况中，都难以满足CSP应用所需的苛刻容限要求。再一种问题是封装的平整度。在典型的CSP设计中，封装平整度(共面性)应小于25微米(1密耳)，以保证在回流时所有的焊球与PCB接触，这是很关键的。这一平整度或共面性的水平用常用的软聚合物和弹性体材料是难以实现的。最后，如果模片未与封装的其它部件适当隔离，那么，由于被组装的模片与诸如电路板的基板之间产生的热应力可能会导致焊球接点的过早失效。
由于目前出现了大量的处理这种结构的设备，通常需要处理条带形式的IC封装。例如，方形平面包装的引线框通常已经在四至八个单元的条带中处理。塑料BGA封装和某些TBGA封装也已做成条形以使于在组装中处理。这种条带被装入料箱中，料箱用于为模片附着、引线焊接、上模(overmolding)/密封、焊球附着和其它处理步骤馈送组装设备。尽管有些组装器可能需要以一卷卷形式进行这些处理，但是，多数可能还是以传统的条带形式。然而，采用弹性衬垫的传统CSP设计对于不用一些附加的刚性源的传统条带形式处理缺乏足够的硬度。例如，TESSERA“MICRO BGA”设计采用金属框粘合到部件的条带的外缘上，以允许条带形式处理。采用这种框是不方便的，并增加产品的最终成本，因为它会增加带处理设计中元件的复杂性和数目以及需要增加步骤，在处理期间附着和去除框。因此，尽管条带形式处理一直被集成电路封装所采用，但是，目前条带形式的芯片级封装设计却并不存在。
在其它CSP设计中，弹性体衬垫被直接叠合到电路和半导体模片上，没有采用粘合剂层，因此消除了在粘合剂层中形成空隙。然而，这种设计仍然存在热应力的问题和对于条带形成的处理不具有足够高的坚固性。
在另一些CSP设计中，如TEXAS INSTRUMENTS公司的“MICRO STAR BGA”，IC直接粘合到柔性电路的表面上，不用聚合物或者弹性体衬垫。这种结构不能解除模片与PCB的耦合，因此，需要采用昂贵的底层填料材料使焊接点达到所需的可靠性。此外，已经发现，来自这种设计所采用的聚合物材料的湿气在对模片附着粘合剂固化期间会排出，从而导致粘合剂的空隙。
因此，需要一种低成本和抗溶剂的芯片级封装，它具有足够高的共面性和不存在与湿气和热应力有关的问题。还需要一种易于以条带形式生产的芯片级封装。
发明概要
本发明所揭示的方法和装置涉及集成电路封装的芯片级球形格栅阵列。这些产品可以用于提供低成本的芯片级封装，它们具有高的可靠性和能够简化工艺。
在所公开的实施例中，在半导体模片及其附属电路之间使用一种非聚合物层或支承结构。当用作支承结构时，非聚合物层可以用于提供基本坚固和平面的表面，以及使模片与诸如印刷电路板(PCB)的基板相分开或去耦合。在典型的实施例中，在芯片级封装组件的非聚合物支承结构与相邻元件之间还可以使用粘合剂材料，以使模片与基板附着在一起，并进一步解除耦合。通过解除模片与基板的耦合，非聚合物支承结构可降低热应力。由于支承结构是非聚合物材料，因此基本上消除了支承结构与模片之间空隙的形成。非聚合物支承结构还具有足够的硬度，允许以条形形式进行集成电路处理。当被用作厚度比支承结构层更薄和硬度比支承结构层更小的层时，除了其它事情之外，非聚合物材料的作用是基本上消除空隙的形成。
在一个方面中，本发明是一种集成电路的封装，包括具有电学互连阵列的中间电路和具有第一和第二侧的至少一层非聚合物层。非聚合物层的第一侧与集成电路结构耦合，非聚合物层的第二侧与中间电路结构耦合。
在另一个方面中，本发明是一种形成集成电路封装的方法，包括步骤：提供一个包括电学互连阵列的中间电路、和提供至少一层非聚合物层，它具有适合于与集成电路结构耦合的第一侧。该方法还包括步骤：使非聚合物层的第二侧与中间电路结构耦合。
在另一个方面中，本发明是一种电子封装，包括具有一层图案化导电层和至少一层图案化介电的柔性带。该封装还包括至少一个具有第一和第二侧的非聚合物支承结构。支承结构的第一侧与柔性带的导电层的第二侧结构耦合。
在另一个方面中，本发明是一种电子封装，包括具有第一和第二侧面和一个外侧边界的有图案的导电层。对导电层进行图案化以形成环绕外侧边界的圆周而设置的周边导电部件的导电区域，作为半导体器件的电连接。该封装还包括具有第一和第二侧面和圆周小于有图案导电层的圆周的外侧边界的有图案介电层。对介电层进行图案化以形成穿过介电层延伸的多个开孔，开孔中的每一个开孔被设置为接收一个焊球。导电层的第一侧面被连接到介电层的第二侧面，以致于使介电层中的多个开孔与导电层的至少部分导电区域对准，以及使导电层的周边导电部件延伸到介质构件的外侧边界以外。还提供一个具有第一和第二侧面的基本坚固的非聚合物支承结构，其弹性模量大于6.89×106kPA。支承结构的第一侧面被结构耦合到导电层的第二侧面上。半导体器件的第一侧面结构耦合到非聚合物支承结构的第二侧面上。半导体器件包括多个电接触部位，接触部位中至少有一个被电耦合到导电层的周边导电部件上。在介电层的第一侧面上设置多个焊球，每一个焊球被定位在介电层中多个开孔的一个开孔中并被电连接到导电层的导电区上。
附图简述
图1是现有技术的一种传统芯片级封装设计的截面表示。
图2是现有技术的另一种传统芯片级封装设计的截面表示。
图3是根据所揭示方法和装置的一个实施例的芯片级封装设计的截面表示。
图3A是根据所揭示方法和装置的一个实施例的另一芯片级封装设计的截面表示。
图3B是根据所揭示方法和装置的一个实施例的另一芯片级封装设计的截面表示。
图3C是根据所揭示方法和装置的一个实施例的另一芯片级封装设计的截面表示。
图3D是根据所揭示方法和装置的一个实施例的另一芯片级封装设计的截面表示。
图4是说明根据所揭示方法和装置的一个实施例将粘合层叠合到薄的非聚合物材料上的截面表示。
图5是根据所揭示方法和装置的一个实施例的已经与粘合剂层叠和经过穿孔的非聚合物材料片的俯视图。
图6是根据所揭示方法和装置的一个实施例的图5所示非聚合物材料片与柔性电路叠合的俯视图。
图6A是根据所揭示方法和装置的一个实施例的图5所示非聚合物材料片具有附着引线焊接模片的俯视图。
图7是根据所揭示方法和装置的一个实施例的定位在焊接用的定位器中的芯片级封装条带的截面表示。
图8是根据所揭示方法和装置的一个实施例的在上模期间定位于定位器中的芯片级封装条带带的截面表示。
图9是根据所揭示方法和装置的一个实施例的模片在密封用定位器之上的芯片级封装条带的截面表示。
图10是根据所揭示方法和装置的一个实施例的已完成的芯片级封装的截面表示。
具体实施例的描述
图1示出在半导体模片12与双层柔性电路带18之间放置一弹性体衬垫10的传统芯片级封装的集成电路封装设计。弹性体衬垫10通常用作带的一部分，在每一侧上设置有粘合层16和粘合层24。通常采用双层电路带，当然，也可以使用三层或多层的电路带。在一种方法中，用粘合层16将双层柔性电路带18附着到弹性体衬垫10上，包括有图案的介质(通常为聚酰亚胺)层20和有图案的导电层21。另一方法，粘合层16和/或24可以没有，例如通过丝网印刷将弹性衬垫施加到带18上。双层柔性带18可以例如通过将导电金属层21直接蒸镀或溅射在电介质层20上而形成。导电层21可以用选择性蒸镀和刻蚀法形成图案。例如通过将导电金属直接溅射在电介质层20上形成导电层21。电介质层20形成有接受焊球(或焊柱)14的开孔(或通孔)22的图案，从而使焊球14与有图案导电层21实现电接触。
如图1所示，粘合层16可以在层21的有图案化导电材料与弹性体衬垫10之间变形(或被压缩)，与此同时，在没有导电材料图案的那些区域中，则在弹性体衬垫10与电介质层20之间有填料加以间隔。例如，粘合层16的厚度在变形前为50微米(2密耳)，有图案的导电层21与弹性体衬垫10之间的的厚度被压缩到12.5微米(0.5密耳)与37.5微米(1.5密耳)之间。用粘合层24将半导体模片12附着到弹性体衬垫10上。在图1所示的芯片级封装设计中，在电路引线42与模片衬垫44之间提供内引线焊接。用存放在密封剂封壳48内的密封剂46将半导体模片12的边缘，包括内引线焊接区在内密封起来。
在图1所示的传统芯片级封装设计中，弹性体衬垫10通常是弹性模量相对较低的弹性体，用于使集成电路与做在PCB或其它基板上的焊接点相隔离或“去耦合”，以降低焊接点上的应力和增大在热循环周期中电路的可靠性。然而，在诸如图1所示的传统芯片级封装设计中，合适弹性体的选择常常是困难的。这是因为难以找到满足集成电路封装苛刻要求的弹性体材料。此外，将弹性体衬垫附着到其它电路元件上的过程通常充满挑战，例如要实现准确定位或涉及丝网印刷或固化常有的麻烦。采用的典型弹性体材料包括基于硅酮的材料和低模量的环氧树脂。
图2示出利用三层柔性电路带和“冲压”通孔的另一传统芯片级封装集成电路设计。在图2中，利用粘合层217将较厚的电介质层220焊接到有图案的导电电路层216上，形成一个三层带。较厚的聚合物覆盖层211直接淀积在三层带218上并用粘合层224附着到半导体模片212上。覆盖层211通常是具有较薄截面厚度(约25微米)的，但模量高于图1弹性体衬垫10的聚合物材料。通常，覆盖层211是基于环氧树脂的材料。在这一传统应用中，三层带/柔性电路组合通常被配置为一个“条带”，是相当坚固的，以致于在传送步骤中无需弯曲焊接引线240便可将条带卸下或放置到使模片过度塑模的固定器中。
仍参考图2，在模片附着粘合剂224固化时(通常在约150℃温度下进行)，由于从聚合物，如电介质层220(通常为聚酰亚胺)和覆盖层211中释放的湿气，在粘合层224中会形成空隙。在将焊球214回流固定到诸如PCB板236的基板上期间通常会进一步产生空隙。同时，在焊球214中可能形成热裂纹。热裂纹通常是由模片212与附着基板236之间产生的热应力引起的。这种热裂纹可能是焊球接点238过早失效的起因。
具有非聚合物支承结构的芯片级封装组件
在所揭示方法和装置的实施例中，在半导体器件或集成电路(例如半导体模片)与附属电路之间采用一种非聚合物支承结构(或衬垫)提供基本坚固和平面的表面，和使模片与诸如PCB的基板隔离或去耦合。在典型的实施例中，为了提供模片与基板的附着和进一步解除耦合，在芯片级封装组件的非聚合物支承结构与相邻元件之间还采用粘合剂材料。通常，采用热膨胀系数(CTE)接近于基板热膨胀系数的非聚合物支承结构，使焊接点上的热应力效应减至最小。
图3示出根据所揭示方法和装置的一个实施例的芯片级封装设计的截面图，其中在半导体模片52与包括两层柔性电路带(或柔性电路或TAB带)58的中间电路之间设置有一非聚合物支承结构50。在本实施例中，非聚合物支承结构50通过粘合层64与模片52实现结构耦合。正如这里所采用的，“结构耦合”意指利用任何合适的方式(如通过淀积、采用粘合剂或其它焊接形式)使两个元件直接耦合或者间接耦合(例如，用位于二者之间的插入层或其它元件)。正如图3所示，半导体模片52通常有模片焊接片或触点84。第二粘合层56将非聚合物衬垫50附着到柔性带58上。尽管图3示出采用两层柔性电路带的芯片级封装设计的一个实施例，但是，应当明白，本公开内容的好处在于，采用其它类型的中间电路，例如具有三层或多层的非柔性电路条带或柔性电路带的实例也是可以的。例如，图3C示出采用三层带19和引线焊接的一个实施例。在这一实施例中，三层带19包括电介质层60、导电层59和第二电介质层(通常为聚酰亚胺)60a。在层59与60a之间采用粘合层60b。
中间电路通常包括与诸如PCB的基板相电学连接的互连阵列。在图3所示的实施例中，两层柔性电路带58通常包括有图案化的电介质层60和具有各个导电焊接垫片59a的有图案平面导电层59。焊球导电焊接垫片59a通常直径约在200微米至600微米之间，二者之间的间距约在300微米至1250微米之间。图案化导电层59可以由适合于形成基本平面的电路的任何可形成图案的导电材料组成，包括诸如硅和多晶硅、钨、钛、铝、基于铝的金属(如铝合金)、铜和合金以及其组合等的金属或导体，但不限于此。(对于本公开内容，术语“金属”限定为包括金属、耐熔金属、金属互化物等及其组合)。最典型的有图案导电层59是铜。图案化的电介质层60可以是由适合于使导电层59绝缘的任何可形成图案的介质材料组成，包括聚酰亚胺或聚酯，但不限于此。最典型的电介质层60是聚酰亚胺，如“DUPONT KAPTON”或“UBE UPILEX”。图案化的导电层59的厚度通常约在12.5微米至37.5微米之间。图案化的电介质层60的厚度通常约在25-75微米之间。
为了形成球形格栅阵列57，导电焊球(或焊柱)54被附着到柔性带58上并通过在电介质层60中图案形成的开孔(或通孔)62与各个焊接垫片59a电学接触。以与各个导电焊接垫片59a互补的方式形成开孔62图案，使得每个开孔覆盖各个导电焊接垫片59a。焊球54可以是适合于通过开孔62与焊接垫片59a连接的任何形状和尺寸。通常，焊球54基本是球形的，直径在250微米至750微米之间，最常用的在300微米至600微米之间。焊球通常是利用诸如红外、对流或汽相的传统炉回流固定的。以这样的方式使开孔62的形状和尺寸适合于接受焊球54，即可以与焊接垫片59a相电学接触。通常，开孔62是圆形的，直径在250微米至600微米之间，最常用的在300微米至500微米之间。导电焊球可以由任何合适的导电材料构成，包括金、焊剂或铜，但不限于此。
在图3所示的实施例中，有图案的导电层59通常具有多个焊接引线82、每个焊接引线与导电焊接垫片59a电耦合。通常，焊接引线82的宽度在25微米至100微米之间。引线82是通过例如内引线焊接在模片衬垫84上实现与半导体模片52的电连接，因此配置与模片衬垫84相似的间距，长度足以允许引线82与衬垫84之间的配对。然而，也可以引线82，利用图3A中所示的引线焊接82a使衬垫83引线焊接到半导体模片52上。在两种情况中，当每个焊接引线82被电学连接到各个模片84上时，在每个焊球54与相应模片衬垫84之间实现一个电路。当为形成球形格栅阵列而如此构成时，设计的每个焊球54被用作使基板76上各个模片衬垫84与相应焊接垫片75电学连接的各个“管脚”。如图6所示，球形格栅阵列57和相应的基板焊接模片衬垫75的间距，通常在300微米至1250微米之间。通常，基板是印刷电路板(“PCB”)，但是也可以是任何其它电路，包括柔性电路、硅、晶片等，但不限于此。
正如图3所示，模片52的边缘和内引线连接区通常被密封剂86所密封，密封剂86放在密封封壳88内。密封剂86可以是本领域技术人员所熟知的任何合适的密封剂，包括环氧树脂和硅酮，但不限于此。密封剂封壳88可以是任何合适的密封剂存放结构，包括例如环氧树脂、粘合剂带等。尽管图3所示的实施例示出采用单层图案化的导电层59的芯片级封装设计，但是，应当明白，本发明的好处在于，实施例也可以采用两层或多层图案化(或非图案化)的导电层。
在图3的实施例中，非聚合物衬垫50可以是适当坚固以便于处理和/或热膨胀系数接近于基板热膨胀系数以使焊接点上的应力减至最小的任何材料。利用这样的非聚合物衬垫结构，可以减少或基本消除在模片附着粘合剂64中形成空隙。这是因为用粘合剂64直接将模片52焊接到非聚合物衬垫60上，因此，不存在来自聚合物材料的湿气，和不能进入这两个元件之间的接口处。
除了减小热应力和空隙形成外，所揭示的方法和装置的非聚合物衬垫结构还提供其它的重要优点。例如，包括非聚合物支承结构10的芯片级封装条带提供的表面，其平整度和表面均匀性比传统弹性体衬垫有所提高。格栅阵列支承结构表面的平整度是保证所有焊球54与基板76上衬垫75接触的一个重要因素。比较理想地，芯片级封装支承结构的共面性为50微米(2密耳)或更低，更理想地，为25微米(1密耳)或更低。这种共面性是采用传统软弹性体衬垫难以实现的。非聚合物支承结构为焊球附着提供了更平的表面，因此允许半导体模片与基板之间的连接更可靠。
除了上述的好处外，可以采用导热非聚合物(如金属片即金属箔)作为非聚合物支承结构50，为从图3中半导体模片52的正面(或图3A中半导体模片52的背面)的热耗散提供良好的热通路。这种导热非聚合物支承结构50还可以有效地把热传导到焊球54上。
通常采用的一种类型的导热非聚合物是金属片即金属箔，铜是特别适合于此的金属。除了导热以外，金属片还可以改善导电层59的电屏蔽和有有助于使交扰减至最小。此外，金属片提供适合于用作接地平面的表面。因此，金属片还可以用于提供一种方便的接地平面(患者，如果需要的话，是供电平面)，例如通过使焊球54a与金属片53直接电连接，如图3B所示。这可以例如通过导电衬垫59b中的通孔55和下方的粘合剂层56进行，使得所选接地连接焊球54a可以与金属片53相电连接。然后，通过内引线或者通过引线焊接82b使模片中的接地衬垫与接地焊球54a连接，如图3B所示。有利地，当采用诸如铜箔的金属片时，可以用相对较低的成本获得这些优点。合适的金属片包括提供足够硬度和/或热膨胀质量的任何图案化的金属箔，包括由铜、不锈钢、合金42、钨、钛、铝、基于铝的金属(如铝合金)、和合金及其组合等制成的金属箔，但不限于此。也可以给铜箔涂覆薄的焊接镀层，提供良好的焊接能力、低的成本和/或降低氧化。合适的镀层的例子包括电镀镍、镍/硼、黑铜氧化物、锡/铅(如高于37％铅的高铅含量的锡/铅合金)、或贵金属，如银或金的表面镀层，但是不限于此。最通常地，非聚合物支持结构是厚度在100-250微米之间的图案化的铜箔，较通常地，厚度在125-175微米之间。铜合金通常用作引线框，如194，最适合于本应用。
当采用合适硬度的非聚合物衬垫时，用引线框常用的典型箱盒馈送设备处理芯片级封装条带可能是有利的。“合适的硬度”，这是指模量大于6.89×106kPA(1×106磅/平方英寸，或1Mpsi)。具有合适硬度的非聚合物材料的例子包括陶瓷、和诸如上述这些的金属箔。然而，应当明白，利用模量小于约6.89×106kPA的非聚合物也可以实现所揭示方法和装置的好处。这些好处包括文中别处所述的那些好处。
参考图3，粘合剂层56和64可以是适合将非聚合物衬垫50固定到柔性带58和半导体模片52上的任何粘合剂。通常，粘合剂层56和64选自介质材料，介质材料与非聚合物衬垫50一起的作用是具有使模片52与基板(或PCB)76相隔离或“去耦合”，因此进一步缓解焊接点上的应力和改善可靠性。这种粘合剂的作用还有为插入插座提供少量的Z轴柔量。合适的粘合剂的例子包括丙烯酸PSA、热塑性聚酰亚胺(如DuPont的“KJ”材料)、聚烯烃、DuPont公司的“PYRALUX”、环氧树脂、及其混合物，但不限于此。通常采用热塑性聚酰亚胺作为粘合剂层56和64。
可以用适合于在弹性体衬垫与相邻表面，如模片或电路踪迹之间形成焊接的任何厚度将粘合剂施加于非聚合物衬垫上。通常，粘合剂层56和64的厚度在25-75微米之间，更常用的厚度在25-50微米之间。
尽管示出的实施例采用单个非聚合物支承结构，但是，应当理解，本发明的好处在于，在层叠的芯片级封装带组件中可以采用一个以上的非聚合物支承结构。例如，可以采用两个或多个电学隔离的金属支承结构，将其用于形成分别的电路通路(如接地平面和供电平面二者)，或者金属与非金属非聚合物支承结构的组合也是可以是，如环氧树脂印刷电路板材料。
在图3D所示的另一实施例中，可将安装层351连同所淀积的非聚合物材料层350一起进行图案化处理，并用在半导体模片352与附属电路之间。例如，安装层351可以用粘合剂层356粘合到两层柔性电路带318或者其它中间电路上，和用粘合剂层364粘合到半导体电路芯片352上。当不是采用以上所述的非聚合物支承结构实施例时，非聚合物层350的作用是通过基本阻止湿气逃逸到模片附着粘合剂364中而降低或基本消除空隙的形成。用许多方法可以有利地制造出连同非聚合物材料一起图案化的安装层，包括作为单独的带式元件或者附着到TAB带上，但不限于此。在有些情况下，利用同非聚合物材料一起图案化的安装层可能比前面所述的非聚合物支承结构的实施例更低廉。
仍参考图3D，非聚合物层350可以由适合于阻止湿气迁移到粘合剂层364中的任何非聚合物材料组成，包括为用作非聚合物支承结构而列出的这些材料。安装层351可以是适合于形成非聚合物层350图案或淀积的任何材料，包括为用作可形成图案的介电材料而列出的这些介质材料。同样，粘合剂层356和364可以是任何合适的粘合剂或附着手段，包括为供非聚合物支承结构使用而列出的这些。通常的非聚合物层350是厚度在1微米至50微米之间的铜层，安装层351是厚度在25-75微米之间的聚酰亚胺层。更一般地，非聚合物层350是厚度在5微米至10微米之间的铜层，安装层351是厚度为50微米的聚酰亚胺层。
图3D示出在类似于图3A所示的非聚合物支承结构应用中，使用了连同非聚合物层350一起图案化的安装层351。与非聚合物支承结构的实施例一样，对于图3D所示的构造可以作出许多变化。例如，导电非聚合物层350可以用作接地平面、供电平面或者完成其它类型的电路通路，如以类似于图3B为非聚合物支承结构所示出的方式。安装层351和非聚合物层351也可以与具有三层或更多层的中间电路一起使用，如与图3C为非聚合物支承结构所示出的实施例相似。此外，可以采用一个以上的非聚合物层350。
芯片级封装元件的制造和组装
用许多方法可以形成具有非聚合物支承结构(或“衬垫”)的本发明所揭示方法和装置的芯片级封装器件，并将其用于许多不同应用中。例如，构造具有非聚合物衬垫的芯片级封装带的一种方法包括步骤：将粘合剂叠合到非聚合物材料(如金属箔)的滚筒上，以所需形状冲压或模压非聚合物材料，使柔性电路(或电路踪迹)与非聚合物对准和粘合，形成芯片级封装带(例如以条带的形式)。在另一不同的方法中，通过将非聚合物材料(如金属箔)冲压成所需形状，将粘合剂薄膜冲压成相同的形状，使薄膜和箔片二者与电路踪迹对准，以及使结构叠合起来，可以形成芯片级封装带。在这两种情况中，电路踪迹与非聚合物支承结构的对准是准确的，也是比较低廉的。可以进行多种不同的步骤，利用刚才所述的芯片级封装条带或带形成芯片级封装器件。这些步骤包括：模片附着、引线和/或内引线焊接、上模和/或焊球附着步骤。有利地，根据这些过程的芯片级封装器件的组装是比较有效、直接和经济有效的。
图4示出粘合剂层56和64叠合到铜片(或箔)50的薄卷筒的两侧。通常，采用具有覆盖层(或防粘衬里)的粘合剂叠层，防粘衬里被留在粘合剂层56和64背离铜箔50的这一侧上。合适的加有防粘衬里的粘合剂叠层包括丙烯酸PSA型粘合剂。如图4所示，用于形成粘合剂层56和64的叠合粘合剂通常是利用滚筒叠层100施加的。然而，应当明白，本发明的好处在于，可以利用任何的合适的方法，包括(但不限于)丝网印刷和喷洒淀积法，来施涂诸如前面所述的这些粘合剂。
图5示出已经与粘合剂层56和64叠合在一起的非聚合物片50的俯视图。在图5中，已经将非聚合物片50冲压或模压形成具有被连接槽区域110环绕的模片方块51的图案。模片方块51构造成具有与半导体模片52相互补的形状和更小的面积，给引线82(或者引线焊接)连接到连接槽区域110中的模片衬垫84留有间隙。连接槽110为利用内引线焊接、引线焊接或其它的合适连接方法连接到模片衬垫84上提供空间。合起来，模片方块51和连接槽110的尺寸为半导体模片52提供各个平台。
应当理解，本发明的好处在于，在所揭示的方法中模压或冲压操作可以利用任何适合于集成电路封装的任何冲压或模压方法进行。通过化学刻蚀，利用钢尺模片或利用化学刻蚀模片也可以使非聚合物形成图案。在片50中也可以冲压工具孔112，以有助于电路的准确对准。
接着，如图6所示，利用工具孔112使具有接受焊球的通孔62的柔性带58对准并叠合到铜片50的一侧上。电路的叠合可以用许多方法进行，包括用滚筒一滚筒方法(如利用链齿孔的滚筒-滚筒方法)或者以压印方法。在本实施例中，通常在叠合前从粘合剂层56上撕去防粘衬里，利用对准用的工具孔112，将电路的面板或条带叠合到片50上。然而，可以采用其它的粘合和叠合方法，如前面所述的那些方法。
此时，集成电路的附着和焊接可以不中断地继续，或者可将非聚合物片50和所附着的柔性带58送往别处，以供进一步组装。在后一种情况中，通常在输送前将非聚合物片50和附着的柔性带58切割成条带形式。用条带形式，单个芯片级封装条带通常具有若干个分别的模片方块51。在这两种情况中，进一步的组装通常涉及从粘合剂层64上去除第二防粘衬里，为将模片安装到非聚合物片50上作准备。在条带形式工艺的情况中，将非聚合物片的条带和附着的电路装载到处理用的料箱中。然后将模片放置在非聚合物条带的粘性侧面(与有电路的侧面相对)，如果需要的话使之固化。然而，应当明白，本发明的好处在于，模片也可以被检起并放置在一卷非聚合物片上(与条带相对)，半导体模片可以与其电路一起放置，与非聚合物片相邻或者相对。也可以使非聚合物条带的模片侧面留下裸露的粘合剂，并用模片附着粘合剂(通常为基于环氧树脂的材料)来粘附固定模片。
接着，使条带(包括电路和一个或多个模片)倒装和放置到标准料箱中，将其装载到例如引线焊接机或者热压焊接机中。如图7所示，利用例如焊接工具124将来自带的每个引线120焊接到模片衬垫122上。利用固定器126支承柔性带(包括模片)，从而使引线120在焊接过程期间在易碎部分(或刻痕)126断裂。如图8所示，然后，通过用密封剂132填充槽110可以使条带上模。通常，密封剂被阻挡部件130所包容，利用合适的固化方法，如紫外或热方法进行固化。或者，如图9所示，可以将条带倒装在固定器表面140上，用密封剂132从条带的模片一侧填充槽110，无需密封剂阻挡部件。正如图3A和3B所示，模片52也可以利用引线焊接82a连接到电路轨迹层59上，例如，当半导体模片是“倒装片”时，使得电路层和半导体模片的模片衬垫取向为背离支承结构的方向。图6A示出这个实施例的俯视图。
如图10所示，接着可以将焊球(或焊柱)54装在开孔(或通孔)62，这些开孔可例如通过在聚酰亚胺层60中刻蚀而形成。利用适合于在球54与导电焊接衬垫59a之间形成牢固电学连接的任何方法，包括例如利用诸如红外、对流或汽相的任何传统手段进行加热和回流，可以使焊球54附着到条带上。尽管图中未示出，但是，通孔62在焊球附着之前也可以这样处理：即经通孔进行镀敷(PTH)和/或用各种导电填充剂材料填充。
此时，可以对条带或卷筒进行切割，形成单个或多个模片的芯片级封装(图10示出一个单个模片的封装150)。这可以利用诸如冲压、切割或其它类似过程的任何合适的切除方法来完成。
在图11中显示了一个实例，其中集成电路158的有源电路一侧朝向非聚合物中间层(interposer)50，并且通过粘合剂150a而粘合于该中间层。在该实例中，集成电路158具有中央导电部件(粘合垫)153，而不是上面所述的周边导电部件。在非聚合物中间层50上形成一槽154，使槽口与从集成电路158中央向下伸出的粘合垫153对齐。这种类型的电路结构是众多电路中常见的，例如在动态随机存取存储器(DRAM)集成电路中。一电路构件159通过粘合剂150b而粘合于非聚合物中间层50上与集成电路158相对的另一侧，该电路构件159包括至少一层沉积在非导电基板161上的图案化导电层160。在该电路构件159上的第一组粘合垫162与非聚合物中间层50的槽154相邻。在集成电路158和第一组粘合垫162之间的电连接是通过引线连接152进行，或者通过柔性电路引线的内引线焊接而实现(未示出)。通常用聚合物材料的密封剂151(沉积入槽154区域)来保护电连接免受环境影响。第一组粘合垫162，通过导电的电路踪迹156而与位于槽154区域以外的阵列中的第二组更大的粘合垫155相连。导电部件如焊球157附着于第二组粘合垫155。通过这些导电部件，可以使该封装连于最终的印刷电路板。
应当明白，本发明的好处在于，利用这一方法，可以制备其它的芯片级封装的结构，包括具有一个以上半导体模片的封装。此外，利用所公开的方法和装置概念可以制造诸如传统BGA封装的非芯片级封装的结构。还应当明白，虽然刚才所描述和示出的方法是为了利用条带形式制造集成电路，但是，当被用于利用其它过程和形式制造集成电路时，包括利用滚筒-滚筒(或者卷筒-卷筒)形式形成集成电路，但不限于此，也可以获得这些方法的好处。在这方面，以与现行工业基础结构相兼容的形式和使用当前所发展的更新的形式可以实现所所揭示方法和装置的好处。还应当明白，上述的封装过程可以与仍在基片形式中的模片一起进行。例如，可以使非聚合物片对准和直接粘合到进行焊接的基片和芯片上。如前所述，然后用密封剂151填充槽154，附着焊球157以及冲压或锯开各个封装件。
本发明可以适合于各种不同的改进和变化形式，这里，通过举例的方式已经示出并描述了具体的实施例。然而，应当明白，不希望本发明被限于所公开的具体形式。而是，本发明覆盖落在所附权利要求书中所限定的本发明的精神和范围内的所有的改进、等效和替代形式。

Claims (12)

1.一种电子封装，其特征在于，它包括：
一集成电路，它具有至少一个位于集成电路第一侧面中央的电接触部位；
一包括电互连阵列的柔性中间电路；
具有第一和第二侧面的至少一层非聚合物层，所述非聚合物层的第一侧面与所述集成电路的第一侧面是结构耦合的，所述非聚合物层的第二侧面与所述中间电路是结构耦合的；
延伸通过该中间电路和该非聚合物层的中央部分的槽，该槽与集成电路的至少一个电接触部位相对齐；
其中所述集成电路的至少一个位于中央的电接触部位被选自下组的导电部件而电耦合于所述中间电路的至少一个电互连上：引线焊接和热压焊接。
2.如权利要求1所述的电子封装，其特征在于，所述的非聚合物层是导电的，且所述的非聚合物层被电耦合到所述集成电路上，形成供电或接地平面。
3.如权利要求1所述的电子封装，其特征在于，所述的非聚合物层是弹性模量大于6.89×106kPA的非聚合物支承结构。
4.如权利要求1所述的电子封装，其特征在于，所述的非聚合物层是由厚度在100-250微米之间的金属箔构成的非聚合物支承结构。
5.如权利要求1所述的电子封装，其特征在于，所述的非聚合物层是由铜箔构成的非聚合物支承结构。
6.如权利要求1所述的电子封装，其特征在于，进一步包括具有第一和第二侧面的安装层，所述安装层的第一侧面与所述非聚合物层的第二侧面相结构耦合，所述安装层的第二侧面与所述中间电路相结构耦合。
7.如权利要求6所述的电子封装，其特征在于，所述的安装层是厚度在25-75微米之间的聚酰亚胺层，所述的非聚合物层是厚度在1微米至50微米之间的铜层。
8.如权利要求1所述的电子封装，其特征在于，所述的中间电路具有第一和第二侧面，所述中间电路的第一侧面与所述非聚合物层的第二侧面相结构耦合；和
进一步包括多个与所述中间电路相电气耦合的焊球或焊柱；所述的多个焊球或焊柱与所述中间电路的第二侧面相结构耦合。
9.一种电子封装，其特征在于，它包括：
一柔性电路，它具有图案化的导电层和至少一层图案化的电介质层，这些层的每个层具有第一和第二侧面；
具有第一和第二侧面的非聚合物支承结构，所述支承结构的第二侧面和所述柔性电路的所述导电层的第一侧面相结构耦合；
一半导体器件，该半导体器件的第一侧面被结构耦合到所述非聚合物支承结构的第一侧面，所述半导体器件包括多个位于中央的电接触部位，所述的接触部位被电耦合到所述柔性电路的所述导电层上。
10.如权利要求9所述的电子封装，其特征在于，所述导电层被图案化处理以形成导电区域，所述电介质层被图案化处理以形成穿过所述电介质层延伸的多个开孔，所述开孔中的每一个被配置为接收一个焊球，这里所述导电层的第二侧面被连接到所述电介质层的第一侧面，从而使所述电介质层中的所述多个开孔与所述导电层的至少部分所述导电区域相对准。
11.如权利要求9所述的电子封装，其特征在于，进一步包括设置在所述柔性带的所述电介质层的第二侧面上的多个焊球或焊柱，所述焊球或焊柱中的每一个被定位在所述电介质层中所述多个开孔的一个开孔中并被电连接到所述柔性电路的所述导电层的所述导电区上。
12.如权利要求9所述的电子封装，其特征在于，所述的非聚合物支承结构是厚度在100-250微米之间的铜箔。
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