CN1284230C - 高频模块 - Google Patents
高频模块 Download PDFInfo
- Publication number
- CN1284230C CN1284230C CNB021180768A CN02118076A CN1284230C CN 1284230 C CN1284230 C CN 1284230C CN B021180768 A CNB021180768 A CN B021180768A CN 02118076 A CN02118076 A CN 02118076A CN 1284230 C CN1284230 C CN 1284230C
- Authority
- CN
- China
- Prior art keywords
- mentioned
- insulative resin
- frequency
- metallic film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K9/00—Screening of apparatus or components against electric or magnetic fields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15159—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
Abstract
在本发明的高频模块中,形成绝缘性树脂,以便于封住在基板的一个表面上搭载的高频半导体元件以及电子部件,而且,在该绝缘性树脂的表面上形成金属薄膜。通过该金属薄膜来得到电磁波屏蔽效果。
Description
技术领域
本发明涉及高频模块及其制造方法。
背景技术
在主要用于携带电话等移动通信装置的高频模块中,在基板上形成高频半导体元件和周边电路组成的高频电路,为了进行高频半导体元件的保护和电磁波屏蔽,多配置金属罩,以便于覆盖住配置了高频电路的基板表面。一般,现有的高频模块,如图12所示的那样,在基板101上安装高频半导体元件102和芯片电阻、芯片电容器等电子部件103,它们通过金属细线104和布线图形(图中省略了详细情况)进行电连接,而形成高频电路。金属罩120被嵌入基板101中,并且,进行焊接固定。
但是,在图12所示的现有的高频模块中,金属罩120成为封装低背化的障碍。当减薄金属罩120时,不能维持金属罩120的强度,容易弯曲而发生与高频电路相接触的问题。为了防止金属罩120与高频电路的接触产生短路,必须在金属罩120的下方设置考虑到金属罩120的弯曲的间隙。如果列举一例,当需要金属罩120的厚度为100μm左右时,必须设计成确保80μm作为内部的间隙。如果能够削减其合计约0.2mm的厚度,就能推进高频模块的低背化。
发明概述
本发明的高频模块,其特征在于,包括:基板;高频电路,搭载在上述基板的一个表面上并包含高频半导体元件;绝缘性树脂,形成为至少封住上述高频半导体元件;金属薄膜,形成在上述绝缘性树脂的表面上。其中,所谓高频半导体元件是在频率400Mhz以上使用的半导体元件。
在该高频模块中,通过金属薄膜而缓和了电磁波对高频电路的影响。而且,由于绝缘性树脂支撑着金属薄膜,因此,即使减薄金属薄膜的厚度,在减薄金属罩的情况下,强度和弯曲也不会发生问题。如果使用绝缘性树脂,能够削减设在金属罩下方的间隙。这样,能够实现高频模块的低背化。
本发明提供在基板的表面上电气连接布线图形和金属薄膜的高频模块的制造方法。该制造方法,其特征在于,通过在对绝缘性树脂使用金属模具来成型或者绝缘性树脂的成型之后进行的激光照射或者机械磨削,形成为布线图形的一部分从基板的表面露出。
在上述制造方法中,当在绝缘性树脂的成型后进行激光照射等加工时,为了提高加工的位置精度,通过在高频电路所配置的基板的一个表面的相对面上预先形成的标记(例如,用于把基板母板分割成基板的划线等的凹部、用于与外部的电连接的电极等的异种材料露出部)来确定位置,进行激光的照射或机械磨削。该方法在使用避免因烧结所产生的变形的陶瓷材料作为基板材料的情况下特别有效。在此情况下,在烧结基板之前,形成标记,在烧结基板之后,一边通过标记确定位置,一边进行由激光的照射等所进行的加工。
附图的简要说明
图1是本发明的高频模块的一个形态中部分地切下绝缘性树脂和金属薄膜来表示的部分切下的透视图;
图2是本发明的高频模块的另一个形态的部分切下的透视图;
图3是本发明的高频模块的另一个形态的部分切下的透视图;
图4是本发明的高频模块的另一个形态的部分切下的透视图;
图5是本发明的高频模块的另一个形态的部分切下的透视图;
图6是通过模块断面图来说明本发明的高频模块的制造工序的图;
图7是表示从基板表面侧看本发明的高频模块的制造工序的一个阶段中的例子的状态的透视图;
图8是表示从基板里面侧看图7所示的一个阶段的状态的透视图;
图9是表示从基板表面侧看本发明的高频模块的制造工序的一个阶段中的另一个例子的状态的透视图;
图10是表示从基板里面侧看图9所示的一个阶段的状态的透视图;
图11是比较高频模块的电磁波屏蔽特性来表示的曲线图;
图12是现有的高频模块的一个形态的部分切下的透视图。
用于实施发明的最佳形态
在本发明的高频模块中,为了提高电磁屏蔽的效果,最好在基板的一个表面上,把与高频半导体元件一起构成高频电路的布线图形与金属薄膜进行电连接。具体地说,在基板的上述一个表面上设置形成绝缘性树脂的第一区域和不形成绝缘性树脂的第二区域,可以把在上述第二区域的基板表面上露出的布线图形与金属薄膜进行电连接。
当在绝缘性树脂上设置开口而使布线图形露出时,绝缘性树脂的开口部可以形成为0.2mm以上5mm以下的最短口径。当最短口径过小时,难于确保与金属薄膜的稳定的电气接触,当最短口径过大时,使安装面积受到限制,不利于模块小型化。
与金属薄膜电连接的布线图形可以是不传导高频信号的布线图形,不管电位的高度,如果成为与接地电位相连接的布线图形,能够得到更高的电磁波屏蔽效果。
金属薄膜的厚度最好为1μm以上300μm以下。当膜厚过薄时,不能得到足够的电磁波屏蔽的效果,当膜厚过厚时,不能把模块充分低背化。
下面对本发明的最佳实施例进行说明。
图1是为了表示内部构造而除去绝缘性树脂的一部分来表示本发明的高频模块的一个形态的部分切除透视图。与现有技术相同,在基板1上配置高频半导体元件2、芯片电阻、芯片电容器等的电子部件3。这些元件2和电子部件3通过省略了详细图示的布线图形相互连接起来。高频半导体元件2通过金属细线4与布线图形电连接。而且,基板1的表面被绝缘性树脂5覆盖,在该绝缘性树脂5的表面上形成金属薄膜6。
如果用绝缘性树脂5气密地密封高频半导体元件2和电子部件3,与例如使用金属罩的情况相比,提高了耐湿性、耐冲击性等特性。金属罩需要焊接固定的工序,但是,随着无铅焊锡的使用,焊接必须在高温下进行,由此的加热会对高频模块的各部件和基板产生不希望的影响。但是,如果使用绝缘性树脂5,不需要这样的焊接工序。
而且,绝缘性树脂5成为支撑金属薄膜6的稳定的「基础」。在该基础上,适当使用蒸镀、溅射、电镀等各种薄膜形成法来形成金属薄膜6。如从后述的测定结果所看到的那样,为了得到实用的电磁波屏蔽效果,所需要的金属薄膜的膜厚(图1:H1)比现有技术所使用的金属罩小两个数量级。而且,对绝缘性树脂5的形成方法没有特别限制,可以通过转模、印刷、喷射成型等来形成。
如果使用本发明的高频模块,例如当使用6mm见方、厚1mm(图1:H3)的陶瓷基板时,能够使模块高度(图1:H1+H2+H3)为1.65mm以下。该模块的厚度在相同条件下与使用金属罩来得到电磁波屏蔽效果时的模块的厚度相比,至少减小了0.2mm。
绝缘性树脂5、金属薄膜6的种类、材料等依本发明的目的而没有特别限制,例如,可以使用环氧树脂等热固性树脂作为绝缘性树脂5,使用金、银、铜、镍等作为金属薄膜6。金属薄膜6并不仅限于单层,可以为多层的。例如,当通过电镀来形成金属薄膜6时,当使金属薄膜6从绝缘性树脂5侧成为铜/镍/闪蒸金的多层构成时,在使金属薄膜6和绝缘性树脂5的紧密接触性良好的同时,能够使金属薄膜6低片电阻化。当该多层构造为使例如各层的厚度依次为1μm、0.5μm、0.05μm(总厚度1.5~1.6μm)时,能够得到与非电解镍镀3μm相同程度的电磁波屏蔽效果。在使用上述那样6mm见方、厚度1mm的陶瓷基板的高频模块的情况下,为了得到在宽广面积上均匀的电磁波屏蔽效果,金属薄膜6的膜厚的最小值最好为2~3μm,而且,为了使用各种薄膜形成方法而形成的金属薄膜6的大量生产性以及低背化,膜厚的最大值最好为10μm。
对于基板1、高频半导体元件2、各电子部件3,可以使用现有技术所使用的,而没有特别限制。通常使用树脂基板和陶瓷基板作为基板1。
金属薄膜6,如图1所示的那样,即使在电气悬浮状态下,也在某种程度上屏蔽电磁波,但是,为了提高其屏蔽效果,可以与基板表面的布线图形相连接。下面表示了金属薄膜6与布线图形的连接的例子。
在图2所示的高频模块中,在绝缘性树脂5上设置圆形的孔(开口部)7以使布线图形10露出,通过形成在该孔7的内表面(底面和侧面)上的金属薄膜,绝缘性树脂5的表面的金属薄膜6与布线图形10电连接。布线图形10最好作为与接地电位相连接的接地线。
在图3所示的高频模块中,设置从平面看为矩形的槽(开口部)8,来取代从平面看设置成圆形的孔。在此,与图2相同,通过形成在该槽8的内表面上的金属薄膜,金属薄膜6与布线图形10电连接,提高了金属薄膜6的电磁波屏蔽效果。而且,孔7、槽8等的开口部的形状并不仅限于圆形、矩形,也可以为椭圆等其他形状。
绝缘性树脂5不需要形成为覆盖基板1表面的全部区域,至少封住高频半导体元件2,而且,最好形成为封住该元件2和构成处理高频信号的电路的电子部件3。因此,上述孔7等除了这些元件2等所配置的区域之外,最好典型地按图示那样设在基板表面的周边部。在本发明的高频模块中,如图2、图3所示的那样,接地图形等的布线图形10被引出基板表面周边部,在该周边部上形成孔7等开口部,在该开口部中,金属薄膜6与布线图形10电连接。
孔7等的开口部其最短口径(与基板表面平行的面上的开口直径的最短部长度,例如图3中对槽8所示的W)形成为0.2mm以上,以便于在其内部易于形成金属薄膜。当最短口径不足0.2mm时,例如电镀液难于进入内部。另一方面,当使上述最短口径大于5mm时,妨碍了模块小型化。
开口部可以通过例如激光照射和切割机(旋转锯)等所进行的机械磨削加工来设置,对形成方法并没有限制。由激光所进行的切削的速度随材料而不同。例如,由YAG(yttrium aluminum garnet)激光所进行的环氧树脂的切削速度显著大于镍等金属的切削速度。利用其,配置在基板表面上的布线图形的露出加工变得容易。
在绝缘性树脂5的侧部设置缺口,或者使侧部后退来使布线图形10露出。图4和图5是从设在绝缘性树脂5上的缺口9的表面露出布线图形10的高频模块的另一种形态的部分切除透视图。在这些模块中,例如,通过用于转模的金属模具的形状,在绝缘性树脂5的周边部上形成缺口9,布线图形10从该缺口9露出。如果在这样设置缺口9的绝缘性树脂5的表面(包含缺口9的部分的表面)和从缺口9露出的布线图形10上形成金属薄膜6,能够确保金属薄膜6和布线图形10的电连接。
如图5所示的那样,当在缺口9的侧壁的一部分上附加锥形时,在该表面上易于形成金属薄膜6,易于确保与布线图形10的电连接。这样,在本发明的高频模块中,特别是在电连接的稳定性容易出问题的情况下(尤其是采用蒸镀、溅射等气相成膜法的情况下),最好在绝缘性树脂5的开口部和缺口部的至少一部分的侧面上附加锥形(侧面和基板表面在绝缘性树脂5侧构成锐角的锥形)。例如,在图3的槽8的情况下,可以使断面成为V字形、U字形等。
在上述图1~图5中,表示不是在绝缘性树脂5的侧面的整个表面上形成金属薄膜6的形态。本发明的高频模块并不仅限于这些形态,但当用适合于大量生产的方法来进行制造时,成为这样的模块的情况较多。在该方法中,在被分割成多个基板的板材(基板母材)上安装高频半导体元件2、电子部件3等,用绝缘性树脂5封住它们,在接着形成金属薄膜6之后,基板母材被分割成基板。下面参照图6来说明该方法的例子。
首先,如按现有技术进行的那样,在基板母材11上在预定位置上搭载芯片电阻、芯片电容器等电子部件3(图6(a)、(b))。该搭载例如通过使用焊膏的反流法来进行。接着,同样通过焊接等来搭载高频半导体元件2(图6(c)),进行使用金属细线4的线粘接(图6(d))。接着,把环氧树脂等的绝缘性树脂5通过转模等成型为预定的形状(图6(e))。接着,通过激光的照射等,在基板母材11的分割预定线13上的绝缘性树脂上设置开口14(图6(f))。如上述说明的那样,该开口14的形成可以使用金属模具与树脂的成型一起设置。接着,在形成开口14的绝缘性树脂5的表面上通过例如电镀等形成金属薄膜6(图6(g))。最后,当沿着分割预定线13来分割基板母材11时,而得到图5所示那样的部分切下树脂侧部的模块。
开口14可以形成为沿着分割预定线13伸长的槽部。在此情况下,在基板1的表面的周边部上,绝缘性树脂5后退,而得到布线图形10从该后退部露出的高频模块。
在上述例示的制造方法中,如图7和图8所示的那样,可以在基板母材11的内表面(形成高频电路的表面的相对面)上沿着分割预定线13形成划线12。一般,可以在分割预定线13上排列通孔,但是,在通孔排列成缝纫机孔状的分割预定线13上,存在树脂从表面侵入或者漏出到内表面上的情况。
当使用陶瓷基板时,存在由于伴随着烧结的基板的稍稍变形而使激光照射位置偏移的情况。但是,如果把划线作为基准,例如,在图7、图8所示的形态下,沿着划线12从相对面照射激光,通过基板的烧结,即使布线图形10部分地左右摆动,沿着该弯曲的布线图形10,也能精度良好地进行由激光所进行的磨削。而且,当使用陶瓷基板时,在未烧结的状态下(例如,氧化铝的生片),例如使用金属模具来形成划线等,然后,例如在800~1300℃进行烧结。
取代划线12,为了与外部的电连接,可以把在基板的内表面侧排列而形成的地电极15作为定位用的标记,来进行激光照射等加工。如图9和图10所示的那样,地电极15不需要设在基板内表面上,可以形成为沿着划线12排列的凹部,在基板侧面上露出。
下面,表示测定由金属薄膜6所产生的电磁波屏蔽的效果的例子。作为金属薄膜6,使用通过无电解电镀形成的镍金属薄膜,厚度为3μm。作为绝缘性树脂5,使用环氧树脂,其厚度约为1mm。与使用金属罩120的情况(相当于图12的形态)一起,在图1中表示:仅在形成金属薄膜6的情况下(相当于图1的形态)、把金属薄膜6与布线图形10相连接的情况下(相当于图2的形态,对布线图形10的电压为3V)、把金属薄膜6连接到接地电位的布线图形10(GND布线图形)上的情况下(相当于图4的形态)的各个模块中的电磁波屏蔽效果。金属罩120的厚度约为300μm。而且,在图11中,把使基板表面露出的状态作为基准(透过0dB),相对地表示电磁波的透过。
如上述那样的那样,根据本发明,能够提供在屏蔽电磁波的同时具有有利于低背化的构造的高频模块。
虽然本发明的优选实施例已经进行了表示和说明,但是,应当知道,本领域的技术人员可以在不背离本发明的精神的条件下进行变化和变型,本发明的范围由权利要求书限定。
Claims (11)
1.一种高频模块,其特征在于,包括:
基板;
高频电路,搭载在上述基板的一个表面上并包含高频半导体元件;
绝缘性树脂,形成为至少封住上述高频半导体元件;
金属薄膜,和高频半导体元件没有电连接,形成在上述绝缘性树脂的表面上。
2.根据权利要求1所述的高频模块,其特征在于,上述高频电路进一步包含不传导高频信号的布线图形,使上述布线图形与上述金属薄膜电连接。
3.根据权利要求2所述的高频模块,其特征在于,
上述基板的上述一个表面具有形成上述绝缘性树脂的第一区域和不形成上述绝缘性树脂的第二区域,
在上述第二区域中在上述基板的上述一个表面上露出的上述布线图形与上述金属薄膜进行电连接。
4.根据权利要求2所述的高频模块,其特征在于,上述绝缘性树脂包含为了使上述布线图形露出而设置的开口部,上述开口部具有0.2mm以上5mm以下的最短口径。
5.根据权利要求2所述的高频模块,其特征在于,在接地电位上所连接的上述布线图形和上述金属薄膜被电连接。
6.根据权利要求1所述的高频模块,其特征在于,上述金属薄膜的膜厚为3μm。
7.根据权利要求1所述的高频模块,其特征在于,上述金属薄膜是多层构成。
8.根据权利要求4所述的高频模块,其特征在于,上述绝缘性树脂的开口部设在上述基板的上述一个表面的周边部上。
9.根据权利要求2所述的高频模块,其特征在于,上述绝缘性树脂在其侧部包含用于使上述布线图形露出的缺口部。
10.根据权利要求4所述的高频模块,其特征在于,在上述绝缘性树脂的开口部的至少一部分的内侧面上附加上述内侧面和基板表面在绝缘性树脂侧构成锐角的锥形。
11.根据权利要求9所述的高频模块,其特征在于,在上述绝缘性树脂的缺口部的至少一部分的侧面上附加上述内侧面和基板表面在绝缘性树脂侧构成锐角的锥形。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP76373/01 | 2001-03-16 | ||
JP2001076373A JP3718131B2 (ja) | 2001-03-16 | 2001-03-16 | 高周波モジュールおよびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1378420A CN1378420A (zh) | 2002-11-06 |
CN1284230C true CN1284230C (zh) | 2006-11-08 |
Family
ID=18933321
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB021180768A Expired - Fee Related CN1284230C (zh) | 2001-03-16 | 2002-03-16 | 高频模块 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7081661B2 (zh) |
JP (1) | JP3718131B2 (zh) |
KR (1) | KR100486400B1 (zh) |
CN (1) | CN1284230C (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102543909A (zh) * | 2012-03-01 | 2012-07-04 | 日月光半导体制造股份有限公司 | 不规则形状的封装结构及其制造方法 |
Families Citing this family (149)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6930256B1 (en) | 2002-05-01 | 2005-08-16 | Amkor Technology, Inc. | Integrated circuit substrate having laser-embedded conductive patterns and method therefor |
US9691635B1 (en) | 2002-05-01 | 2017-06-27 | Amkor Technology, Inc. | Buildup dielectric layer having metallization pattern semiconductor package fabrication method |
US7548430B1 (en) | 2002-05-01 | 2009-06-16 | Amkor Technology, Inc. | Buildup dielectric and metallization process and semiconductor package |
US7633765B1 (en) | 2004-03-23 | 2009-12-15 | Amkor Technology, Inc. | Semiconductor package including a top-surface metal layer for implementing circuit features |
US7187060B2 (en) | 2003-03-13 | 2007-03-06 | Sanyo Electric Co., Ltd. | Semiconductor device with shield |
JP4051326B2 (ja) * | 2003-08-26 | 2008-02-20 | 京セラ株式会社 | 電子装置の製造方法 |
JP2005117009A (ja) * | 2003-09-17 | 2005-04-28 | Denso Corp | 半導体装置およびその製造方法 |
DE10359885B4 (de) * | 2003-12-19 | 2006-05-04 | Pepperl + Fuchs Gmbh | Verfahren zur Herstellung eines Schaltgeräts sowie Baugruppe für ein Schaltgerät |
JP4335661B2 (ja) | 2003-12-24 | 2009-09-30 | Necエレクトロニクス株式会社 | 高周波モジュールの製造方法 |
US20070102831A1 (en) * | 2003-12-24 | 2007-05-10 | Shuntaro Machida | Device and method of manufacturing the same |
US11081370B2 (en) | 2004-03-23 | 2021-08-03 | Amkor Technology Singapore Holding Pte. Ltd. | Methods of manufacturing an encapsulated semiconductor device |
US10811277B2 (en) | 2004-03-23 | 2020-10-20 | Amkor Technology, Inc. | Encapsulated semiconductor package |
US7629674B1 (en) * | 2004-11-17 | 2009-12-08 | Amkor Technology, Inc. | Shielded package having shield fence |
JP2006165109A (ja) * | 2004-12-03 | 2006-06-22 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP4408082B2 (ja) * | 2005-01-14 | 2010-02-03 | シャープ株式会社 | 集積回路パッケージの設計方法および製造方法 |
JP2006210480A (ja) * | 2005-01-26 | 2006-08-10 | Nec Electronics Corp | 電子回路基板 |
US7265034B2 (en) * | 2005-02-18 | 2007-09-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of cutting integrated circuit chips from wafer by ablating with laser and cutting with saw blade |
EP1715520B1 (fr) * | 2005-04-21 | 2010-03-03 | St Microelectronics S.A. | Dispositif de protection d'un circuit électronique |
JP4589170B2 (ja) * | 2005-04-28 | 2010-12-01 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
JP4810904B2 (ja) | 2005-07-20 | 2011-11-09 | ソニー株式会社 | 高周波スイッチ回路を有する高周波装置 |
US8959762B2 (en) | 2005-08-08 | 2015-02-24 | Rf Micro Devices, Inc. | Method of manufacturing an electronic module |
US8053872B1 (en) | 2007-06-25 | 2011-11-08 | Rf Micro Devices, Inc. | Integrated shield for a no-lead semiconductor device package |
US7451539B2 (en) * | 2005-08-08 | 2008-11-18 | Rf Micro Devices, Inc. | Method of making a conformal electromagnetic interference shield |
US8061012B2 (en) * | 2007-06-27 | 2011-11-22 | Rf Micro Devices, Inc. | Method of manufacturing a module |
US8062930B1 (en) * | 2005-08-08 | 2011-11-22 | Rf Micro Devices, Inc. | Sub-module conformal electromagnetic interference shield |
KR100651465B1 (ko) * | 2005-08-09 | 2006-11-29 | 삼성전자주식회사 | 전자 회로 모듈 및 집적 회로 장치의 제작 방법과 그를이용한 전자 회로 모듈 |
JP4467506B2 (ja) * | 2005-11-24 | 2010-05-26 | 三菱電機株式会社 | パッケージおよびそれを用いた電子装置 |
JP2007157763A (ja) * | 2005-11-30 | 2007-06-21 | Mitsumi Electric Co Ltd | 回路モジュール |
US7626247B2 (en) * | 2005-12-22 | 2009-12-01 | Atmel Corporation | Electronic package with integral electromagnetic radiation shield and methods related thereto |
TWI283056B (en) * | 2005-12-29 | 2007-06-21 | Siliconware Precision Industries Co Ltd | Circuit board and package structure thereof |
KR100737098B1 (ko) * | 2006-03-16 | 2007-07-06 | 엘지이노텍 주식회사 | 전자파 차폐장치 및 그 제조 공정 |
JP4944024B2 (ja) * | 2006-03-22 | 2012-05-30 | 三菱電機株式会社 | 送受信装置 |
KR100691629B1 (ko) * | 2006-04-21 | 2007-03-12 | 삼성전기주식회사 | 금속벽을 이용한 고주파 모듈 및 그 제조 방법 |
US7309912B1 (en) * | 2006-06-28 | 2007-12-18 | Altera Corporation | On-package edge-mount power decoupling and implementation with novel substrate design for FPGA and ASIC devices |
TWM308497U (en) * | 2006-10-03 | 2007-03-21 | Lingsen Precision Ind Ltd | Microelectromechanical module package structure with reduced noise interference |
FR2907633B1 (fr) * | 2006-10-20 | 2009-01-16 | Merry Electronics Co Ltd | Boitier de systeme micro-electromecanique. |
US7550857B1 (en) | 2006-11-16 | 2009-06-23 | Amkor Technology, Inc. | Stacked redistribution layer (RDL) die assembly package |
KR100844790B1 (ko) * | 2006-11-29 | 2008-07-07 | 엘지이노텍 주식회사 | 전자파 차폐장치 및 이를 갖는 고주파 모듈과 고주파 모듈제조방법 |
KR100844791B1 (ko) | 2006-11-29 | 2008-07-07 | 엘지이노텍 주식회사 | 전자파 차폐장치 및 이를 갖는 고주파 모듈과 고주파 모듈제조방법 |
WO2008062982A1 (en) * | 2006-11-21 | 2008-05-29 | Lg Innotek Co., Ltd | Electromagnetic shielding device, radio frequency module having the same, and method of manufacturing the radio frequency module |
KR101349546B1 (ko) * | 2007-02-06 | 2014-01-08 | 엘지이노텍 주식회사 | Rf송수신 시스템 |
KR100834684B1 (ko) * | 2007-02-12 | 2008-06-02 | 삼성전자주식회사 | 전자 회로 패키지 |
FI20070415L (fi) * | 2007-05-25 | 2008-11-26 | Elcoteq Se | Suojamaadoitus |
US7701040B2 (en) * | 2007-09-24 | 2010-04-20 | Stats Chippac, Ltd. | Semiconductor package and method of reducing electromagnetic interference between devices |
US20090091907A1 (en) * | 2007-10-09 | 2009-04-09 | Huang Chung-Er | Shielding structure for electronic components |
US7989928B2 (en) | 2008-02-05 | 2011-08-02 | Advanced Semiconductor Engineering Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8350367B2 (en) * | 2008-02-05 | 2013-01-08 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8212339B2 (en) * | 2008-02-05 | 2012-07-03 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8022511B2 (en) | 2008-02-05 | 2011-09-20 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
KR100877551B1 (ko) * | 2008-05-30 | 2009-01-07 | 윤점채 | 전자파 차폐 기능을 갖는 반도체 패키지, 그 제조방법 및 지그 |
US7772046B2 (en) * | 2008-06-04 | 2010-08-10 | Stats Chippac, Ltd. | Semiconductor device having electrical devices mounted to IPD structure and method for shielding electromagnetic interference |
JP2008288610A (ja) * | 2008-07-17 | 2008-11-27 | Taiyo Yuden Co Ltd | 回路モジュールの製造方法 |
US8410584B2 (en) | 2008-08-08 | 2013-04-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8242616B1 (en) * | 2008-08-29 | 2012-08-14 | Renesas Electronics Corporation | Method for manufacturing semiconductor device and molded structure |
TW201013881A (en) * | 2008-09-10 | 2010-04-01 | Renesas Tech Corp | Semiconductor device and method for manufacturing same |
JP5321592B2 (ja) * | 2008-10-07 | 2013-10-23 | 株式会社村田製作所 | 電子部品モジュールの製造方法 |
WO2010047007A1 (ja) * | 2008-10-23 | 2010-04-29 | 株式会社村田製作所 | 電子部品モジュールの製造方法 |
US20100110656A1 (en) * | 2008-10-31 | 2010-05-06 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
JP4539788B2 (ja) * | 2008-12-10 | 2010-09-08 | 株式会社村田製作所 | 高周波モジュール |
US20170117214A1 (en) | 2009-01-05 | 2017-04-27 | Amkor Technology, Inc. | Semiconductor device with through-mold via |
US7923739B2 (en) | 2009-06-05 | 2011-04-12 | Cree, Inc. | Solid state lighting device |
US8598602B2 (en) * | 2009-01-12 | 2013-12-03 | Cree, Inc. | Light emitting device packages with improved heat transfer |
WO2010082449A1 (en) * | 2009-01-16 | 2010-07-22 | Semiconductor Energy Laboratory Co., Ltd. | Regulator circuit and rfid tag including the same |
DE102009000427A1 (de) * | 2009-01-27 | 2010-07-29 | Robert Bosch Gmbh | Verfahren zur Herstellung eines Sensormoduls |
US20100207257A1 (en) * | 2009-02-17 | 2010-08-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and manufacturing method thereof |
US8110902B2 (en) | 2009-02-19 | 2012-02-07 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
US7960827B1 (en) | 2009-04-09 | 2011-06-14 | Amkor Technology, Inc. | Thermal via heat spreader package and method |
US8623753B1 (en) | 2009-05-28 | 2014-01-07 | Amkor Technology, Inc. | Stackable protruding via package and method |
US8686445B1 (en) | 2009-06-05 | 2014-04-01 | Cree, Inc. | Solid state lighting devices and methods |
US8860043B2 (en) * | 2009-06-05 | 2014-10-14 | Cree, Inc. | Light emitting device packages, systems and methods |
US8222538B1 (en) | 2009-06-12 | 2012-07-17 | Amkor Technology, Inc. | Stackable via package and method |
US8212340B2 (en) | 2009-07-13 | 2012-07-03 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
US8471154B1 (en) | 2009-08-06 | 2013-06-25 | Amkor Technology, Inc. | Stackable variable height via package and method |
US8796561B1 (en) | 2009-10-05 | 2014-08-05 | Amkor Technology, Inc. | Fan out build up substrate stackable package and method |
US8030750B2 (en) * | 2009-11-19 | 2011-10-04 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8378466B2 (en) | 2009-11-19 | 2013-02-19 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with electromagnetic interference shielding |
US8368185B2 (en) * | 2009-11-19 | 2013-02-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
US9691734B1 (en) | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
US8536462B1 (en) | 2010-01-22 | 2013-09-17 | Amkor Technology, Inc. | Flex circuit package and method |
TWI411075B (zh) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US8300423B1 (en) | 2010-05-25 | 2012-10-30 | Amkor Technology, Inc. | Stackable treated via package and method |
US8294276B1 (en) | 2010-05-27 | 2012-10-23 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US8648359B2 (en) | 2010-06-28 | 2014-02-11 | Cree, Inc. | Light emitting devices and methods |
US8269244B2 (en) | 2010-06-28 | 2012-09-18 | Cree, Inc. | LED package with efficient, isolated thermal path |
USD643819S1 (en) * | 2010-07-16 | 2011-08-23 | Cree, Inc. | Package for light emitting diode (LED) lighting |
US8338229B1 (en) | 2010-07-30 | 2012-12-25 | Amkor Technology, Inc. | Stackable plasma cleaned via package and method |
TWI540698B (zh) | 2010-08-02 | 2016-07-01 | 日月光半導體製造股份有限公司 | 半導體封裝件與其製造方法 |
US8717775B1 (en) | 2010-08-02 | 2014-05-06 | Amkor Technology, Inc. | Fingerprint sensor package and method |
US9137934B2 (en) | 2010-08-18 | 2015-09-15 | Rf Micro Devices, Inc. | Compartmentalized shielding of selected components |
US9007273B2 (en) | 2010-09-09 | 2015-04-14 | Advances Semiconductor Engineering, Inc. | Semiconductor package integrated with conformal shield and antenna |
US8337657B1 (en) | 2010-10-27 | 2012-12-25 | Amkor Technology, Inc. | Mechanical tape separation package and method |
US8482134B1 (en) | 2010-11-01 | 2013-07-09 | Amkor Technology, Inc. | Stackable package and method |
US9748154B1 (en) | 2010-11-04 | 2017-08-29 | Amkor Technology, Inc. | Wafer level fan out semiconductor device and manufacturing method thereof |
US8525318B1 (en) | 2010-11-10 | 2013-09-03 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
WO2012072795A2 (en) * | 2010-12-03 | 2012-06-07 | ALERE TECHNOLOGIES GmbH | Transformation of material into an optically modulating state via laser radiation |
US8557629B1 (en) | 2010-12-03 | 2013-10-15 | Amkor Technology, Inc. | Semiconductor device having overlapped via apertures |
US8535961B1 (en) | 2010-12-09 | 2013-09-17 | Amkor Technology, Inc. | Light emitting diode (LED) package and method |
US8610140B2 (en) | 2010-12-15 | 2013-12-17 | Cree, Inc. | Light emitting diode (LED) packages, systems, devices and related methods |
USD679842S1 (en) | 2011-01-03 | 2013-04-09 | Cree, Inc. | High brightness LED package |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
TWI525782B (zh) * | 2011-01-05 | 2016-03-11 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
TW201251140A (en) | 2011-01-31 | 2012-12-16 | Cree Inc | High brightness light emitting diode (LED) packages, systems and methods with improved resin filling and high adhesion |
WO2012109225A1 (en) | 2011-02-07 | 2012-08-16 | Cree, Inc. | Components and methods for light emitting diode (led) lighting |
US9721872B1 (en) | 2011-02-18 | 2017-08-01 | Amkor Technology, Inc. | Methods and structures for increasing the allowable die size in TMV packages |
US8835226B2 (en) | 2011-02-25 | 2014-09-16 | Rf Micro Devices, Inc. | Connection using conductive vias |
US9627230B2 (en) | 2011-02-28 | 2017-04-18 | Qorvo Us, Inc. | Methods of forming a microshield on standard QFN package |
US9013011B1 (en) | 2011-03-11 | 2015-04-21 | Amkor Technology, Inc. | Stacked and staggered die MEMS package and method |
KR101140113B1 (ko) | 2011-04-26 | 2012-04-30 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 |
JP5480923B2 (ja) | 2011-05-13 | 2014-04-23 | シャープ株式会社 | 半導体モジュールの製造方法及び半導体モジュール |
US8653674B1 (en) | 2011-09-15 | 2014-02-18 | Amkor Technology, Inc. | Electronic component package fabrication method and structure |
US8633598B1 (en) | 2011-09-20 | 2014-01-21 | Amkor Technology, Inc. | Underfill contacting stacking balls package fabrication method and structure |
US9029962B1 (en) | 2011-10-12 | 2015-05-12 | Amkor Technology, Inc. | Molded cavity substrate MEMS package fabrication method and structure |
US8541883B2 (en) | 2011-11-29 | 2013-09-24 | Advanced Semiconductor Engineering, Inc. | Semiconductor device having shielded conductive vias |
JP2013161831A (ja) * | 2012-02-01 | 2013-08-19 | Mitsumi Electric Co Ltd | 電子モジュール及びその製造方法 |
US8937376B2 (en) | 2012-04-16 | 2015-01-20 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages with heat dissipation structures and related methods |
US8786060B2 (en) | 2012-05-04 | 2014-07-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package integrated with conformal shield and antenna |
US8704341B2 (en) | 2012-05-15 | 2014-04-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages with thermal dissipation structures and EMI shielding |
US8653634B2 (en) | 2012-06-11 | 2014-02-18 | Advanced Semiconductor Engineering, Inc. | EMI-shielded semiconductor devices and methods of making |
US9153542B2 (en) | 2012-08-01 | 2015-10-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor package having an antenna and manufacturing method thereof |
JP2014063806A (ja) * | 2012-09-20 | 2014-04-10 | Toshiba Corp | 半導体装置 |
US9799592B2 (en) | 2013-11-19 | 2017-10-24 | Amkor Technology, Inc. | Semicondutor device with through-silicon via-less deep wells |
KR101366461B1 (ko) | 2012-11-20 | 2014-02-26 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
US9978688B2 (en) | 2013-02-28 | 2018-05-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package having a waveguide antenna and manufacturing method thereof |
US9837701B2 (en) | 2013-03-04 | 2017-12-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor package including antenna substrate and manufacturing method thereof |
US9129954B2 (en) | 2013-03-07 | 2015-09-08 | Advanced Semiconductor Engineering, Inc. | Semiconductor package including antenna layer and manufacturing method thereof |
US9172131B2 (en) | 2013-03-15 | 2015-10-27 | Advanced Semiconductor Engineering, Inc. | Semiconductor structure having aperture antenna |
KR101488590B1 (ko) | 2013-03-29 | 2015-01-30 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
US9807890B2 (en) | 2013-05-31 | 2017-10-31 | Qorvo Us, Inc. | Electronic modules having grounded electromagnetic shields |
CN103400825B (zh) | 2013-07-31 | 2016-05-18 | 日月光半导体制造股份有限公司 | 半导体封装件及其制造方法 |
JP5576542B1 (ja) * | 2013-08-09 | 2014-08-20 | 太陽誘電株式会社 | 回路モジュール及び回路モジュールの製造方法 |
KR101607981B1 (ko) | 2013-11-04 | 2016-03-31 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지용 인터포저 및 이의 제조 방법, 제조된 인터포저를 이용한 반도체 패키지 |
US9691949B2 (en) | 2014-05-30 | 2017-06-27 | Cree, Inc. | Submount based light emitter components and methods |
US9666930B2 (en) * | 2014-10-23 | 2017-05-30 | Nxp Usa, Inc. | Interface between a semiconductor die and a waveguide, where the interface is covered by a molding compound |
USD777122S1 (en) * | 2015-02-27 | 2017-01-24 | Cree, Inc. | LED package |
USD772181S1 (en) * | 2015-04-02 | 2016-11-22 | Genesis Photonics Inc. | Light emitting diode package substrate |
USD778848S1 (en) * | 2015-04-07 | 2017-02-14 | Cree, Inc. | Solid state light emitter component |
USD783547S1 (en) * | 2015-06-04 | 2017-04-11 | Cree, Inc. | LED package |
CN105140138B (zh) * | 2015-09-16 | 2017-10-27 | 江苏长电科技股份有限公司 | 一种电磁屏蔽封装方法及其封装结构 |
US10934157B2 (en) | 2016-03-21 | 2021-03-02 | Murata Manufacturing Co., Ltd. | Packaged circuit system structure |
JP1566953S (zh) * | 2016-04-28 | 2017-01-16 | ||
JP6683542B2 (ja) * | 2016-06-11 | 2020-04-22 | 新日本無線株式会社 | 電磁シールドを備えた半導体装置の製造方法 |
US9960328B2 (en) | 2016-09-06 | 2018-05-01 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
US10957736B2 (en) | 2018-03-12 | 2021-03-23 | Cree, Inc. | Light emitting diode (LED) components and methods |
US11127689B2 (en) | 2018-06-01 | 2021-09-21 | Qorvo Us, Inc. | Segmented shielding using wirebonds |
US11219144B2 (en) | 2018-06-28 | 2022-01-04 | Qorvo Us, Inc. | Electromagnetic shields for sub-modules |
US11114363B2 (en) | 2018-12-20 | 2021-09-07 | Qorvo Us, Inc. | Electronic package arrangements and related methods |
US11515282B2 (en) | 2019-05-21 | 2022-11-29 | Qorvo Us, Inc. | Electromagnetic shields with bonding wires for sub-modules |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6464298A (en) * | 1987-09-03 | 1989-03-10 | Nec Corp | Hybrid integrated circuit |
JPH0412593A (ja) * | 1990-05-01 | 1992-01-17 | Taiho Kogyo Kk | 電磁波シールド方法 |
JPH0458596A (ja) | 1990-06-28 | 1992-02-25 | Nippon Telegr & Teleph Corp <Ntt> | 電磁シールド方法 |
JPH05291787A (ja) * | 1992-04-14 | 1993-11-05 | Nitto Denko Corp | 高周波用多層配線板及びその製造方法 |
JPH0763115B2 (ja) * | 1993-03-25 | 1995-07-05 | 日本電気株式会社 | 高周波モジュール装置及びその製造方法 |
JPH0846073A (ja) * | 1994-07-28 | 1996-02-16 | Mitsubishi Electric Corp | 半導体装置 |
JPH08288686A (ja) * | 1995-04-20 | 1996-11-01 | Nec Corp | 半導体装置 |
WO1997002596A1 (fr) * | 1995-06-30 | 1997-01-23 | Kabushiki Kaisha Toshiba | Composant electronique et son procede de fabrication |
US6159770A (en) | 1995-11-08 | 2000-12-12 | Fujitsu Limited | Method and apparatus for fabricating semiconductor device |
US6072239A (en) | 1995-11-08 | 2000-06-06 | Fujitsu Limited | Device having resin package with projections |
JP3074264B2 (ja) | 1997-11-17 | 2000-08-07 | 富士通株式会社 | 半導体装置及びその製造方法及びリードフレーム及びその製造方法 |
US6329711B1 (en) | 1995-11-08 | 2001-12-11 | Fujitsu Limited | Semiconductor device and mounting structure |
US6376921B1 (en) | 1995-11-08 | 2002-04-23 | Fujitsu Limited | Semiconductor device, method for fabricating the semiconductor device, lead frame and method for producing the lead frame |
JP2938820B2 (ja) | 1996-03-14 | 1999-08-25 | ティーディーケイ株式会社 | 高周波モジュール |
US6150193A (en) * | 1996-10-31 | 2000-11-21 | Amkor Technology, Inc. | RF shielded device |
JP3500268B2 (ja) * | 1997-02-27 | 2004-02-23 | 京セラ株式会社 | 高周波用入出力端子ならびにそれを用いた高周波用半導体素子収納用パッケージ |
US6566596B1 (en) * | 1997-12-29 | 2003-05-20 | Intel Corporation | Magnetic and electric shielding of on-board devices |
JP2000223647A (ja) | 1999-02-03 | 2000-08-11 | Murata Mfg Co Ltd | 高周波モジュールの製造方法 |
US6362961B1 (en) * | 1999-04-22 | 2002-03-26 | Ming Chin Chiou | CPU and heat sink mounting arrangement |
JP2001244688A (ja) | 2000-02-28 | 2001-09-07 | Kyocera Corp | 高周波モジュール部品及びその製造方法 |
-
2001
- 2001-03-16 JP JP2001076373A patent/JP3718131B2/ja not_active Expired - Lifetime
-
2002
- 2002-03-13 US US10/098,895 patent/US7081661B2/en not_active Expired - Lifetime
- 2002-03-14 KR KR10-2002-0013785A patent/KR100486400B1/ko not_active IP Right Cessation
- 2002-03-16 CN CNB021180768A patent/CN1284230C/zh not_active Expired - Fee Related
-
2004
- 2004-10-06 US US10/960,161 patent/US7125744B2/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102543909A (zh) * | 2012-03-01 | 2012-07-04 | 日月光半导体制造股份有限公司 | 不规则形状的封装结构及其制造方法 |
CN105977223A (zh) * | 2012-03-01 | 2016-09-28 | 日月光半导体制造股份有限公司 | 不规则形状的封装结构及其制造方法 |
CN105977223B (zh) * | 2012-03-01 | 2018-11-27 | 日月光半导体制造股份有限公司 | 不规则形状的封装结构及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP3718131B2 (ja) | 2005-11-16 |
KR100486400B1 (ko) | 2005-04-29 |
US20020153582A1 (en) | 2002-10-24 |
KR20020073409A (ko) | 2002-09-26 |
JP2002280468A (ja) | 2002-09-27 |
US7081661B2 (en) | 2006-07-25 |
US7125744B2 (en) | 2006-10-24 |
CN1378420A (zh) | 2002-11-06 |
US20050056925A1 (en) | 2005-03-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1284230C (zh) | 高频模块 | |
US7161252B2 (en) | Module component | |
US7261596B2 (en) | Shielded semiconductor device | |
CN1295951C (zh) | 电磁屏蔽电路设备及其屏蔽方法 | |
US7180012B2 (en) | Module part | |
CN1158757C (zh) | 封装的表面声波部件及其制造方法 | |
CN1198486C (zh) | 具有用于安装电子部件的空腔的印刷线路板 | |
CN1237861C (zh) | 密封电子元件的电子器件及其制造方法和宜用于该电子器件的印刷线路板 | |
CN1332599A (zh) | 平面安装型电子电路组件 | |
CN1229330A (zh) | 混合模块及其制造方法与其安装方法 | |
CN1497717A (zh) | 电路装置及其制造方法 | |
CN1530978A (zh) | 芯片式电容及其制造方法以及模制模具 | |
US11871523B2 (en) | Electronic component module and method for manufacturing electronic component module | |
JP3404375B2 (ja) | 多数個取り配線基板 | |
JP4605945B2 (ja) | 多数個取り配線基板、電子装置の製造方法 | |
CN111052352B (zh) | 多连片式布线基板、电子部件收纳用封装件、电子装置以及电子模块 | |
CN113394170B (zh) | 封装结构及其制造方法 | |
JP4272506B2 (ja) | 多数個取り配線基板 | |
JPH0878954A (ja) | 発振器およびその製造方法 | |
CN1262159C (zh) | 电子部件及其安装结构 | |
JP2003347689A (ja) | 多数個取り配線基板 | |
CN1503279A (zh) | 小型电子零件 | |
JP3798992B2 (ja) | 多数個取りセラミック配線基板 | |
JP2005159083A (ja) | 多数個取り配線基板 | |
JP2006128297A (ja) | 多数個取り配線基板および電子装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20200601 Address after: Kyoto Japan Patentee after: Panasonic semiconductor solutions Co.,Ltd. Address before: Osaka Japan Patentee before: Panasonic Corp. |
|
TR01 | Transfer of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20061108 Termination date: 20210316 |
|
CF01 | Termination of patent right due to non-payment of annual fee |