CN1305623A - 具有与物品集成的天线的射频识别标签 - Google Patents

具有与物品集成的天线的射频识别标签 Download PDF

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CN1305623A
CN1305623A CN99807203A CN99807203A CN1305623A CN 1305623 A CN1305623 A CN 1305623A CN 99807203 A CN99807203 A CN 99807203A CN 99807203 A CN99807203 A CN 99807203A CN 1305623 A CN1305623 A CN 1305623A
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antenna
radio frequency
frequency identification
circuit chip
substrate
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诺埃尔H·埃伯哈特
桑贾·格埃姆
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Motorola Solutions Inc
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    • GPHYSICS
    • G08SIGNALLING
    • G08BSIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B13/00Burglar, theft or intruder alarms
    • G08B13/02Mechanical actuation
    • G08B13/14Mechanical actuation by lifting or attempted removal of hand-portable articles
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B65CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65DCONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
    • B65D5/00Rigid or semi-rigid containers of polygonal cross-section, e.g. boxes, cartons or trays, formed by folding or erecting one or more blanks made of paper
    • B65D5/42Details of containers or of foldable or erectable container blanks
    • B65D5/4212Information or decoration elements, e.g. content indicators, or for mailing
    • B65D5/4233Cards, coupons, labels or the like formed separately from the container or lid
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743External electrical contacts
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773Antenna details
    • G06K19/07786Antenna details the antenna being of the HF type, such as a dipole
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B65CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65DCONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
    • B65D2203/00Decoration means, markings, information elements, contents indicators
    • B65D2203/10Transponders
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate

Abstract

一种射频识别标签(14),利用与物品、包装、包装容器、标签和/或认证证章(10)结合形成并且因而集成的天线(22)。在优选实施例中,射频识别标签电路芯片组件(12)固定在物品(10)上并且与形成在物品(10)上的天线电耦合。使用导电墨水印刷导电图形形成优选天线。

Description

具有与物品集成的天线的射频识别标签
本申请与下列共同转让的在先美国专利申请有关。Ted Geiszler等人于1995年10月11日提交的申请序号为08/540813的“远端供电电子标签和相关激励器/读取器和有关方法”,代理记录号IND00701;Victor Allen Vega等人于1998年2月27日提交的申请序号为09/031848的“利用为耦合接地设计的标签的射频识别标签系统”,代理记录号IND10153;Victor Allen Vega等人于1998年3月12日提交的申请序号为09/041480的“为磁存储标签状态信息设计的射频识别标签”,代理记录号IND10146;以及Victor Allen Vega等人于1998年3月20日提交的申请序号为09/045357的“具有可编程电路状态的射频识别标签”,代理记录号IND10174;这些在先申请在此引用作为参考,如同在此将这些公开内容一字不差地进行阐述所具有的相同效果。
本发明总的涉及射频识别标签领域,包括但不限于具有物品集成天线的射频识别标签。
射频识别标签和射频识别标签系统是公知的,并且有许多应用。例如,射频识别标签经常用于自动门卫应用中的人员识别,保护建筑或地区的安全。在射频识别标签中存储的信息识别寻求进入被保卫建筑的人。射频识别标签系统方便地提供在短距离内利用射频(RF)数据传输技术从射频识别标签中读取信息。通常,用户简单地手持或将射频识别标签放在接近基站处,该基站向包含在射频识别标签中的射频识别标签的供电电路发射激励信号。该电路响应于激励信号,将存储的信息从射频识别标签传送给基站,由基站接收和解码该信息。通常,射频识别标签能够保持和在工作中发射丰富的信息一一足够用于唯一识别个人,包装,库存等的信息。
供电和读取射频识别标签的典型技术是电感耦合或电感电源耦合和电容数据耦合的组合。电感耦合利用射频识别标签中的线圈元件。该线圈元件被来自基站的激励信号所激励,为射频识别标签电路提供电源。射频识别标签线圈,或第二线圈,可以用于在射频识别标签和基站之间发射和接收所存储的信息。依赖电感耦合的射频识别标签对射频识别标签相对基站的方向敏感,因为由激励信号产生的电场必须与线圈元件以基本上直角相交才能有限耦合。电感耦合装置的读取范围一般在几个厘米数量级。对于某些应用,例如电子宠物识别、行李跟踪、包裹跟踪和库存管理应用需要更长的读取距离。
对射频识别标签供电和读取的另一个技术是静电耦合,例如在上述参考应用中所公开的射频识别标签系统和射频识别标签中所采用的。这些系统有利地提供了对于现有技术的那些应用明显增加的读/写距离。从所公开的系统和标签的使用获得的另一个优点是用户不需要将射频识别标签靠近基站或将标签对着基站方向。因此,有可能将基站的天线合并到例如门口或门厅、包裹传送机或物品分类系统中,以在更大距离上对标签供电和读取标签信息。
为在基站和射频识别标签之间耦合电感或静电信号,标签必须包括一个具有至少一个,通常为两个的天线单元的天线。通常,标签电路芯片和天线电连接并粘合到标签基片上。由标签基片尺寸所决定的标签尺寸一般保持非常小。因此,天线通常受尺寸限制。可是,更小的天线不利地影响了读取范围。天线也必须与标签基片形成在同平面上,这潜在地使标签对方向敏感。因为不希望,通常也不现实,将射频识别标签制造得更大,有效的天线尺寸仍然受限制。通常平面的标签设计也限制了天线是平面的、方向敏感的构形。
如今,射频识别标签已经制造成为自含式单元,即标签电路芯片、天线和基片成为单一组件。因此,不仅天线的尺寸和构形已经引起了射频识别标签性能方面的问题,天线还明显影响了整个标签的成本。
射频识别标签的应用包括个人认证证章、物品和/或包装认证标签和电子物品监视标签。在许多这样的应用中,认证证章、物品和/或包装基本上大于用于提供识别信息的射频识别标签。可是,认证证章、物品或包装的尺寸并不提供增加尺寸或减少自含式射频识别标签天线的方向敏感性的机会。
这样,需要一种改进的射频识别标签。
在附图中说明本发明的优选示范性实施例,在图中相似的参考标号代表相似的部件。
图1是按照本发明优选实施例的射频识别标签分解装配图。
图2是图1沿2-2线的截面图。
图3是射频识别标签电路芯片组件的透视图,其被部分分离以展示在此形成的导体元件。
图4是图3沿线4-4的截面图。
图5是按照本发明优选实施例的射频识别标签分解装配图。
图6是图5沿线6-6的截面图。
图7是射频识别标签电路芯片组件的透视图。
图8是图7沿线8-8的截面图。
图9是按照本发明另一个优选实施例的射频识别标签分解装配图。
图10是图9沿线10-10的截面图。
图11是与图10类似的截面图,表示本发明的另一个优选实施例。
图12是按照本发明另一个优选实施例的射频识别标签截面图。
图13是按照本发明另一个优选实施例的射频识别标签截面图。
图14是按照本发明另一个优选实施例的射频识别标签截面图。
图15是按照本发明另一个优选实施例的没有组装包装容器的透视图。
图16是按照本发明另一个优选实施例的组装后包装容器的透视图。
按照本发明优选实施例的射频识别标签利用了与物品、包装、包装容器、标签和/或认证证章(“物品”)结合形成并集成的天线。在本发明的优选实施例中,射频识别标签电路芯片组件被固定在物品中并且与形成在物品上的天线电连接。利用导电墨水在物品上印刷导电图形形成优选天线。
参照图1,所表示的分解装配图中射频识别标签14包括物品10和射频识别标签电路芯片组件(“芯片组件”)12。所示物品10一般是由具有第一表面18和第二表面20的薄片材料形成的基片16。应当理解该基片16可以形成个人认证证章、标签、包装容器(例如盒子或信封)等的基础。另外,基片材料可以是适合于特定应用的任何材料例如塑料(包括聚酯或金属化聚酯材料),纸,合成纸,强化纸,卡片,合成纸涂层卡片等。如同下面对本发明另一个优选实施例的描述,射频识别标签电路芯片可以直接附着在安排有集成形成的天线的基片上。芯片组件12的设计有利地提供了制造上的方便,因为可以利用自动化技术大批生产许多芯片组件。芯片组件12相对小,在1-2cm见方数量级,因此与其所附着的物品相比容易存储、运输和处理。另外,如同所要描述的,芯片组件12为射频识别标签电路芯片附着在物品上提供了简化的方式,并且随着将物品连接到集成形成的天线上。
形成在第一表面18上的天线22包括第一天线单元24和第二天线单元26。第一天线单元24和第二天线单元26的每个由导电材料形成,并且被粘合否则被固定因而被集成在物品10上。最好,第一天线单元24和第二天线单元26的每个通过利用合适的可印刷导电介质印刷形成。例如,当印刷到纸和/或卡片上时,碳/石墨基的导电墨水形成有效天线22。另外可以使用合成和涂层纸,但增加成本。为在塑料材料上进行印刷,可以使用银或其他贵金属墨水,但由于较高的材料成本而不是优选的。所示的天线22一般具有断开H型,适合于用在静电信号应用中。应当理解更适合于例如电感耦合的其它图形可以被印刷而不脱离本发明的范围。第一天线单元24和第二天线单元26的每个分别包括通常在断开H图形中央的第一耦合区28和第二耦合区30。最好,天线22可以制造得基本上大于传统射频识别标签结构,而接近表面18的表面面积。第一耦合区28和第二耦合区30的每个包括导电焊盘区用于通过各向异性黏合剂层34与芯片组件12电连接(图2)。
优选的各向异性黏合剂是可以从3M公司获得的3M 9703黏合剂。优选黏合剂是各向异性的其中只在“Z”或垂直方向导电(图1)。将黏合剂制成包括黏合剂基质中的金属涂层微小球,使黏合剂层34的顶表面对底表面电接触。电接触不在X或Y方向,即黏合剂层34的平面方向形成。因此,黏合剂可以施加在整个层上,而不使相邻导体短接。
然后参照图2和进一步参照图3和图4,芯片组件12包括基片36,其上形成导电图形37包括第一导电元件38和第二导电元件40。基片36最好是薄、柔性纸、塑料、合成纸或其它具有纸的类似材料片,并且最好是低成本基片材料。第一导电元件38和第二导电元件40的每个优选地通过利用适合的可印刷导电介质在基片36上印刷导电图形37形成。适合的导电墨水包括含有碳/石墨墨水、含有贵金属墨水和所选择的与基片36相容的类似墨水。
如图3所见,通过第一导电元件38和第二导电元件40形成的优选导电图形37是断开H型,提供了连接天线22的基本面积和分别提供了第一芯片耦合区42和第二芯片耦合区44。射频识别标签电路芯片(“电路芯片”)46通过层34固定在基片36上并且耦合到第一和第二耦合区42和44。
在读/写实施例中,电路芯片46可以由TEMIC e5550电路芯片方便地构成(可以从TEMIC NORTH AMERICA公司获得,BaskingRidge,New Jersey)。在只读实施例中,可以使用Indala1341电路芯片(可以从MOTOROLA INDALA公司获得,San Jose,California)。利用为耦合到导电图形37而设计的第一导电焊盘48和第二导电焊盘50形成电路芯片46。如同所示,第一导电焊盘48和第二导电焊盘50是“凸起”焊盘。即,它们从电路芯片46的表面向外突出与“表面”焊盘相反,它基本上与电路芯片外表面同平面形成。当固定在基片36上时,第一导电焊盘48接触第一芯片耦合区42而导电焊盘50接触第二芯片耦合区44,提供了它们之间的有效电连接。层34的小区域52在电路芯片46和基片36之间被稍微压缩,形成电路芯片46与基片36的强力机械粘合。并没有特别偏好使用凸起焊盘,根据成本和特定的应用可以选择凸起焊盘、表面焊盘或凹槽焊盘(即,把形成的导电焊盘凹进电路芯片46的外表面中)。
如同从前面讨论所理解的,按照本发明优选实施例,通过将电路芯片组件12连接到具有集成形成的天线22的物品10上来形成射频识别标签14。因此,对于天线22的唯一尺寸限制是物品10上非金属化和/或非导电表面的面积。以此方式,可以实现明显比传统射频识别标签所可能实现的更大的天线。直接好处包括增加读取距离和减少潜在的方向敏感性。另外,天线22可以使用不昂贵包含碳/石墨导电墨水印刷在物品上,并且可以形成在大量与物品10非共平面和/或非平行平面上,由此减少了方向敏感性。这样,以降低的成本来实现改善的性能。
现在参照图5,所示分解装配图的射频识别标签114包括一个物品110和一个射频识别标签电路芯片组件(“芯片组件”)112。所示物品110一般是由具有第一表面118和第二表面120的薄片材料形成的基片116。应当理解,基片116可以形成个人认证证章、标签、包装容器(例如盒子或信封)等的基础。另外,基片材料可以是任何适合于特定应用的材料,例如纸、塑料(包括聚酯或金属化聚酯)、合成纸、加强纸,卡片,合成纸涂层卡片以及具有能提供合适的低成本和优选基片材料的纸等。
形成在第一表面118上的天线122包括第一天线单元124和第二天线单元126。第一天线单元124和第二天线单元126的每个由粘合或固定在并因此集成在物品110上的导电材料形成。更好地,第一天线单元124和第二天线单元126的每个利用合适的可印刷的导电介质通过印刷而形成。例如,当印刷到纸、卡片、涂层卡片和/或合成纸上时,由碳/石墨基导电墨水形成有效天线122。为在塑料材料上进行印刷可以特别使用银或其他贵金属墨水,但由于较高的材料成本而不是优选的。所示的天线122一般具有断开H型,适合于用在静电信号应用中。应当理解更适合于例如电感耦合的其它图形可以被印刷而不脱离本发明的范围。第一天线单元124和第二天线单元126的每个分别包括通常在断开H图形中央的第一耦合区128和第二耦合区130。最好,天线122可以制造得基本上大于传统射频识别标签结构,而接近表面118的表面面积。第一耦合区128和第二耦合区130的每个包括导电焊盘区用于通过黏合剂层134和黏合剂层135与芯片组件112电连接(图6)。因为黏合剂层134和黏合剂层135在芯片组件112上相互隔离,可以使用各向异性黏合剂。优选的各向异性黏合剂是可从ADHESIVES RESEARCH公司获得的#8001。
参照图6和进一步参照图7和图8,芯片组件112包括基片136,其上形成的导电图形137包括第一导电元件138和第二导电元件140。基片136最好是纸、塑料、合成纸或其它类似材料的柔软的薄片。第一导电元件138和第二导电元件140的每个优选地利用适合的可印刷的导电介质通过在基片136上印刷导电图形137而形成。适合的导电墨水包括含有碳/石墨墨水、含有贵金属墨水和所选择的与基片136相容的类似物。
如图7所见,通过第一导电元件138和第二导电元件140形成的优选导电图形137是断开H型,提供了连接天线122的基本面积和分别提供了第一芯片耦合区142和第二芯片耦合区144。射频识别标签电路芯片(“电路芯片”)146利用适合的黏合剂例如环氧黏合剂固定在基片136上。
在读/写实施例中,电路芯片146可以由TEMIC e5550电路芯片方便构成,而在只读实施例中,由Indala1341电路构成。利用耦合到天线例如天线22的第一导电焊盘和第二导电焊盘形成电路芯片146。第一导电焊盘和第二导电焊盘按需要可以是“表面”焊盘,“凹槽”焊盘,或“凸起”焊盘。用第一和第二导电焊盘将电路芯片146背靠背地固定在基片36上。一旦固定在基片136上,一层导电黏合剂148将第一导电焊盘电耦合到第一芯片耦合区142,而一层导电黏合剂150将第二导电焊盘电耦合到第二芯片耦合区144,提供了它们之间的有效电连接。
类似射频识别标签14,通过将电路芯片组件112连接到具有集成形成的天线122的物品110上形成射频识别标签114。因此,对于天线122的唯一尺寸限制是物品10上非金属化、或非导电表面的面积。以此方式,可以实现明显比传统射频识别标签所可能实现的更大的天线。通过将天线122形成在非平行表面上也可以减少方向敏感性。直接的好处包括增加读取距离,潜在地减少了方向敏感性并降低成本。
通过层34和层134和层135可以将多个芯片组件12或112准备和固定在透明介质(未表示)上。透明介质允许芯片容易拆装,并且可以是片或卷型材料。芯片组件可以从透明介质上拆下然后固定到物品上。例如,在库存和包装工作中,当进行包装时,当需要跟踪这种包装就可以应用芯片组件。
现在参照图9,所示分解装配图的射频识别标签214是通过将射频识别标签电路芯片组件(“芯片组件”)246直接连接到具有集成形成的天线222的物品210上所形成。所示物品210一般是由具有第一表面218和第二表面220的片材料形成的基片216。应当理解,基片216可以形成个人认证证章、标签、包装容器(例如盒子或信封)等的基础。另外,基片材料可以是任何适合于特定应用的材料,例如纸、塑料(包括聚酯和金属化聚酯材料)、合成纸、加强纸,卡片,涂层卡片和等。
形成在第一表面218上的天线222包括第一天线单元224和第二天线单元226。第一天线单元224和第二天线单元226的每个由粘合或固定并且因此集成在物品210的导电材料形成。更好地,第一天线单元224和第二天线单元226的每个利用合适的可印刷的导电介质通过印刷形成。例如,当印刷到纸、卡片、合成纸或合成纸涂层卡片上时由碳/石墨基导电墨水形成有效天线222。为在塑料材料上进行印刷可以特别使用银或其他贵金属墨水,但由于较高的材料成本而不是优选的。所示的天线222一般具有断开H型,适合于用在静电信号应用中。应当理解更适合于例如电感耦合的其它图形可以被印刷而不脱离本发明的范围。第一天线单元224和第二天线单元226的每个分别包括通常断开H图形中央的第一耦合区228和第二耦合区230。最好,天线222可以制造得基本上大于传统射频识别标签结构,而接近物品210表面218的表面面积。
现在参照图10通过各向异性黏合剂层234将电路芯片246粘合到物品210上。在读/写实施例中,电路芯片246可以由TEMIC e5550电路芯片有利构成,而在只读实施例中,由Indala1341电路构成。利用耦合到天线222的第一导电焊盘248和第二导电焊盘250形成电路芯片246。第一导电焊盘248和第二导电焊盘250是“凸起”焊盘,然而也可以使用在电路芯片246上形成的表面焊盘、凹槽焊盘或其它合适的导电焊盘。导电焊盘248和导电焊盘250设计为用于分别电接触第一芯片耦合区242和第二芯片耦合区244,提供它们之间的有效电连接。层234的小区域252在电路芯片246和基片216之间被稍微压缩形成坚固的机械粘合。保护片(未示出)然后可以施加在电路芯片246和层234上。
参照图11,表示了按照另一个优选实施例的射频识别标签314,针对上述射频识别标签214相似的元件用相同的参考数字代表。因此,如图11所见,射频识别标签314通过直接将电路芯片246连接到具有集成形成天线222的物品310上而形成。物品310包括一个基片316,该基片具有局部挤压区域317,电路芯片246定位和固定在物品310的该区域内。以此方式,电路芯片246定位得稍低于表面218并因此在物品310使用期间获得保护以免损伤。应当进一步理解,物品310可以利用上述挤压区域形成并且设计为容纳电路芯片组件,例如上述的电路芯片组件12或电路芯片组件112。一旦固定到区域317内,电路芯片246可以由填充材料360包围和/或覆盖。填充材料最好是紫外线固化聚合材料,该材料可以安置在区域317中电路芯片246上和周围,并且通过对紫外线曝光快速固化。也可以利用保护覆盖而固定在电路芯片246上。
图12表示了射频识别标签514,包括按照本发明优选实施例构成的射频识别标签电路芯片512,被固定在基片516的凹槽517内。凹槽517形成为基片516的被压缩部分,达到足以将芯片组件512安置到低于基片516表面518的深度。在基片518上形成的天线522包括第一导电部分524和第二导电部分526。最好通过将沉积导电墨水印刷在基片518上形成天线522。最好使用各向异性黏合剂(未示出)将芯片组件512粘结在凹槽517内,以便芯片组件512有效地电连接到天线522。精确使用的各向异性黏合剂也可以用于将芯片组件512粘结并且电连接而不脱离本发明的范围。应当进一步理解,芯片组件512可以是射频识别标签电路芯片而不脱离本发明的范围。一旦芯片组件512被粘结到凹槽517内,盖子560被粘结到表面518上和天线522上,形成具有薄而基本上平面构形的射频识别标签514。实际上,射频识别标签514的总厚度基本上不大于芯片组件512的厚度。应当还理解,基片516和盖子560可以组成物品的一部分。例如,基片516和盖子560可以形成薄片状包装例如卡片盒子、标签、信封、证件、货运单等壁的一部分。
参照图13,射频识别标签614包括按照本发明优选实施例构成的射频识别标签电路芯片组件612,被固定在基片616的凹槽617内。凹槽617形成为基片616的被压缩部分,压缩深度达到芯片组件612厚度的一半,或换句话说,以便将芯片组件612的上部安置得高于表面618。在基片618上形成的天线622包括第一导电部分624和第二导电部分626。最好通过将沉积导电墨水印刷在基片618上形成天线622。最好使用各向异性黏合剂(未示出)将芯片组件612粘结在凹槽617内,以便芯片组件612有效地电连接到天线622。精确使用的各向异性黏合剂也可以用于将芯片组件612粘结并且电连接而不脱离本发明的范围。应当进一步理解,芯片组件612可以是射频识别标签电路芯片而不脱离本发明的范围。形成盖子660包括盖子凹槽662。盖子凹槽662形成为盖子660的被压缩部分,压缩深度达到大约从表面664计算的芯片组件612厚度的一半。一旦芯片组件612被粘结到凹槽617内,盖子660被粘结到表面618上和具有与凹槽517对准的盖子凹槽662的天线622上,则一起形成具有薄而基本上平面构形的射频识别标签614。实际上,射频识别标签614的总厚度基本上不大于芯片组件612的厚度。应当还理解,基片616和盖子660可以组成物品的一部分。例如,基片616和盖子660可以形成薄片状包装例如卡片盒子、标签、信封、证件、货运单等壁的一部分。
参照图14,射频识别标签714包括按照本发明优选实施例构成的射频识别标签电路芯片组件712,被固定在基片716上。在基片716上表面718上形成的天线722包括第一导电部分724和第二导电部分726。最好通过将沉积导电墨水印刷在基片718上形成天线722。最好使用各向异性黏合剂(未示出)将芯片组件712粘结在表面718上,以便芯片组件712有效地电连接到天线722。精确使用的各向异性黏合剂也可以用于将芯片组件712粘结并且电连接而不脱离本发明的范围。应当进一步理解,芯片组件712可以是射频识别标签电路芯片而不脱离本发明的范围。形成盖子760包括盖子凹槽762。盖子凹槽762形成为盖子760的被压缩部分,压缩深度从表面764测算达到大于芯片组件712厚度的厚度。一旦芯片组件712被粘结到表面718上,盖子760被粘结到表面718和具有围绕芯片组件712的盖子凹槽762的天线722上,就形成了具有薄而基本上平面构形的射频识别标签714。实际上,射频识别标签714的总厚度基本上不大于芯片组件712的厚度。应当还理解,基片716和盖子760可以组成物品的一部分。例如,基片716和盖子760可以形成薄片状包装例如卡片盒子、标签、信封、证件、货运单等壁的一部分。
按照本发明另一个方面,并且参照图15和图16,适合用于射频识别标签系统(未示出)的包装容器410包括集成形成的天线422。图15表示了在未组装状态的包装容器410。包装容器410包括一个包装介质416,由纸、卡片或涂层卡片材料、利用通过优选低成本的简单纸或卡片形成。在包装介质416上形成多个切口456和多个刻痕458,允许包装介质416按照众所周知的技术折叠成为盒子形状454(图16)。
在包装介质416第一表面418上形成的天线422包括第一天线单元424和第二天线单元426。第一天线单元424和第二天线单元426的每个由粘结或否则被固定并且因而被集成到包装容器410上的导电材料形成。最好,第一天线单元424和第二天线单元426的每个利用适合的可印刷的导电介质通过印刷而形成。例如,当印刷在纸、卡片和/或涂层卡片上时,碳/石墨基导电墨水形成有效天线422。所示的天线422一般覆盖了表面418的所有有效区域,第一天线单元424和第二天线单元426的每个包括在包装介质416中心的第一耦合区428和第二耦合区430。第一耦合区428和第二耦合区430的每个设计成用于将按照本发明的射频识别标签芯片组件或射频识别标签电路芯片电连接。
包装容器410提供的主要优点是天线表面面积基本数量。天线422的面积大于传统射频识别标签中可以使用的数量级。另外,由于天线422基本上覆盖了包装容器410的整个内部表面418,大大减少了方向敏感性。天线422可以利用相对便宜的含碳/石墨墨水印刷,仅在需要时,并当组装包装容器410时才加上芯片组件,因而降低了成本。
总之,参照图1,已经公开了一种射频识别标签14,包括一个固定在物品10内的射频识别标签电路芯片46。形成的物品10包括一个天线22和电连接到该天线上的射频识别标签电路芯片46。
参照图2,射频识别标签电路芯片46优选地构成射频识别标签电路芯片组件12。电路芯片组件12包括一个包含导电图形37的基片16,和固定在基片16上并且与导电图形耦合的一个射频识别标签电路芯片46。导电图形37设计成用于将集成形成的该天线22耦合到物品10上。
参照图12,在本发明的另一个优选实施例中,射频识别标签514包括在其表面518内形成有凹槽517的基片516和形成在基片上的天线522。射频识别标签电路芯片组件512固定在凹槽内并且与该天线电连接。盖子固定在该表面上。
参照图13,本发明的另一个优选实施例中,射频识别标签614包括形成的基片616,包括在其表面618中的凹槽617和形成在表面上的天线622。射频识别标签电路芯片646固定在凹槽内并且与该天线电连接。盖子660固定在该表面上,和将该盖子形成为包括盖子凹槽662,和将盖子凹槽设计为与该凹槽对准。
参照图14,在本发明的另一个优选实施例中,射频识别标签714包括具有形成在其表面718上的一个天线722的基片716。射频识别标签电路芯片组件712固定在该表面上并且与该天线电连接。盖子760固定在该表面上,和盖子形成为包括盖子凹槽762,将该盖子凹槽设计为围绕射频识别标签电路芯片。
参照图15,本发明的另一个方面提供了一种包装容器,设计用于射频识别标签系统,包括包装介质416和形成在包装介质表面418上的天线422。
在本发明中通过将天线形成为要跟踪物品一部分并且将射频识别标签电路芯片组件固定在该物品上而克服射频识别标签天线尺寸和方向的限制。该天线通过将导电墨水印刷在物品表面上而方便地构成。可以经济地大批生产射频识别标签电路芯片组件。
通过利用作为物品一部分的所形成的基本上大面积的天线,增加读取范围。
通过在物品非平行表面上形成该天线,减少方向敏感性。
通过利用便宜导电墨水在物品上形成该天线减少射频识别标签成本。
通过提供基片凹槽区、电路芯片组件固定在该基片内并且与该天线连接,避免了电路芯片组件的无意移动。
在不脱离本发明范围和精神的前提下,可以进行许多另外改变和修改。上面讨论了这些改变的范围。对于所附的权利要求书而言其它修改范围是显而易见的。

Claims (13)

1.一种天线,设计用于射频识别标签电路芯片,该天线包括:
基片,该基片形成物品的一部分,和
形成在该基片上的导电图形,该导电图形包括第一耦合区和第二耦合区,用于将该天线耦合到询问器,该基片具有在第一耦合区和第二耦合区附近的局部压缩区域。
2.权利要求1的天线,该物品是证章、包装,容器和标签之一。
3.权利要求1的天线,该导电图形是印刷在该基片上的导电墨水。
4.权利要求1的天线,第一耦合区和第二耦合区与射频识别标签电路芯片电连接。
5.权利要求1的天线,第一耦合区和第二耦合区设计为用于静电耦合到询问器。
6.权利要求1的天线,该基片包括第一表面和第二表面,第一表面和第二表面是不平行的,并且该导电图形形成在第一表面和第二表面上。
7.一种包装容器,设计为用于射频识别标签电路芯片,该包装容器包括:
包装介质,和
形成在包装介质上的导电图形,该导电图形包括第一耦合区和第二耦合区,用于将该包装耦合到询问器,并且该包装介质具有在第一耦合区和第二耦合区附近的局部压缩区域。
8.权利要求7的包装容器,该导电图形形成用于射频识别标签电路芯片的天线。
9.权利要求7的包装容器,该导电图形是印刷在包装介质上的导电墨水。
10.权利要求7的包装容器,第一耦合区和第二耦合区电连接到射频识别标签电路芯片。
11.权利要求7的包装容器,第一耦合区和第二耦合区设计为用于电容性耦合到询问器。
12.一种射频识别标签,包括:基片,形成为包括在其表面上的凹槽和形成在表面上的天线;固定在凹槽内并且电耦合到该天线的射频识别标签电路芯片,该天线电容性耦合到询问器;以及固定在表面上的盖子。
13.一种射频识别标签,包括:基片,形成为包括在其表面上的凹槽和形成在表面上的天线;固定在凹槽内并且电耦合到该天线的射频识别标签电路芯片,该天线静电耦合到询问器;以及安置在凹槽内并且围绕射频识别标签电路芯片的填充材料。
CN99807203A 1998-06-09 1999-06-08 具有与物品集成的天线的射频识别标签 Pending CN1305623A (zh)

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CN1832169B (zh) * 2005-03-08 2010-09-29 株式会社半导体能源研究所 无线芯片以及具有该无线芯片的电子设备
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WO2015135410A1 (zh) * 2014-03-11 2015-09-17 田艺儿 一种盖章式射频电子印章
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WO1999065002A1 (en) 1999-12-16
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CA2334156C (en) 2002-11-12
JP2002517870A (ja) 2002-06-18
KR20010052681A (ko) 2001-06-25
AU4422399A (en) 1999-12-30
EP1093644A4 (en) 2002-11-20
CA2334156A1 (en) 1999-12-16
US6107920A (en) 2000-08-22
RU2001101456A (ru) 2003-01-10

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