CN1308374A - 晶片整合刚性支持环 - Google Patents

晶片整合刚性支持环 Download PDF

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Publication number
CN1308374A
CN1308374A CN00133852A CN00133852A CN1308374A CN 1308374 A CN1308374 A CN 1308374A CN 00133852 A CN00133852 A CN 00133852A CN 00133852 A CN00133852 A CN 00133852A CN 1308374 A CN1308374 A CN 1308374A
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China
Prior art keywords
solder stack
additional
wafer
contact
peripheral chip
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Granted
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CN00133852A
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CN1199263C (zh
Inventor
H·D·科希
D·P·丹尼尔
L·J·加德基
A·J·格雷戈里特斯奇三世
R·A·M·朱利亚内勒
C·H·基勒
D·P·普拉斯基
M·A·谢弗
D·L·史密斯
D·J·斯佩希特
A·E·维尔辛
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Core Usa Second LLC
GlobalFoundries Inc
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International Business Machines Corp
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Publication of CN1308374A publication Critical patent/CN1308374A/zh
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Publication of CN1199263C publication Critical patent/CN1199263C/zh
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Abstract

一个障板用于沉积焊料堆,包括附加虚设孔,位于晶片上相应于多数周边芯片的孔附近。附加虚设物提供了晶片触点更均匀的等离子体蚀刻,改善了周边芯片触点的蚀刻,并降低了周边芯片触点的触点电阻。多余孔还提供了周边芯片外的焊料堆,可以用于支持第二障板,它用于附加材料,如锡,沉积在回流焊料堆上,用于以低的温度将芯片安装在塑料基底上。改善的对齐辅助工具避免对检测探针的损坏,并提供改善的对齐过程。

Description

晶片整合刚性支持环
本发明通常是关于用焊料堆互连的半导体晶片。特别是关于蒸发脱水的焊料堆。更特别的是关于改善的用于蒸发脱水焊料堆的障板。
半导体晶片的制作是形成连接晶片上电路的触点。由焊料堆形成的叩焊晶片结合被越来越多地用作触点，因为大量触点可以在区域阵列内提供。人们一直通过对由钼薄层做成的障板进行蒸发脱水或溅射，形成焊料堆。
传统地，高可靠性的焊料堆连接可通过提供铅含量非常高的焊料堆实现。这已经被接受用作陶瓷基底的焊料堆触点，陶瓷基底可以承受熔化高铅含量焊料的高温。但是，对低温基底，例如塑料基底的连接来说，需要在标准回流高铅成分焊料堆上，提供低熔点锡帽的成分，如在公开的美国专利5,729,896到Dalal及其它所描述，这里引入参考。形成这些锡帽焊料堆的两多孔障板过程在公开的美国专利5,922,496到Dalal及其它中描述，这里引入参考。但是，本发明的发明者发现，用于锡帽沉积的第二多孔障板会损坏在第一多孔障板步骤形成的高熔点焊料堆。这样，需要一种解决方案改善过程，避免对在第一多孔障板步骤形成的焊料堆的损坏。
而且，本发明还提供解决另一问题的解决方案。在第一障板被定位后，晶片被送到等离子体蚀刻步骤，去除可能覆盖在触点垫上的氧化物，减少触点垫与位于焊料堆之下的球界特性冶金间的触点电阻。当位于多孔障板孔之下的触点被送到等离子体中并将氧化物去除时，由钼多孔障板覆盖的晶片部分被保护在等离子体外。但是，整个晶片上氧化物去除的均匀性是个问题，晶片的部分区域被发现比其它区域具有较低的触点电阻。这样，需要提供一种等离子体蚀刻的一个较好的解决方案的方法，来在整个晶片上提供更均匀的低触点电阻。提供充分改善的触点电阻均匀性，同时如果第二多孔障板和沉积步骤被使用时，避免焊料堆的损坏，这种方法在下面的发明中被提供。
这样本发明的一个目标是提供一个具有周边芯片的晶片，其中附加虚设焊料堆位于每个周边芯片的附近。
本发明的另一个目标是提供一个障板，用于在晶片的芯片上沉积球界特性冶金和焊料堆，其中附加孔被提供在多孔障板上所有周边芯片附近。
本发明的另一个目标是通过在多孔障板上所有周边芯片附近提供的附加孔，由障板的孔改善芯片触点等离子体蚀刻的均匀性。
本发明的另一个目标是当障板被放置在晶片上，通过在晶片上所有周边芯片附近提供附加焊料堆，进行第二焊料沉积时，避免对芯片焊料堆的损坏。
本发明的一个特点是，在附加焊料堆上提供界线实现晶片分块。
本发明的一个特点是，甚至如果产品芯片上的焊料堆阵列没有被完全填充时，附加焊料堆完全填充的阵列被提供在分块界线间，至少沿晶片外围伸到去除区。
本发明的一个优点是，电离区的均匀性保持在超过晶片上周边芯片的半径之外。
本发明的一个优点是，触点电阻的均匀性被改善，并且周边芯片的触点电阻被减小。
本发明的一个优点是，当第二焊料沉积被通过第二障板提供时，对周边芯片焊料堆的损坏被减少或避免，因为附加焊料堆对第二障板提供支持。
本发明的这些和其它目标、特点和优点通过晶片实现，晶片包括一组具有触点的芯片阵列。触点包括焊料堆。芯片阵列包括沿晶片外围伸出的周边芯片。附加虚设焊料堆位于多数周边芯片的附近，其中附加虚设焊料堆用于改善周边芯片的触点工艺。
改善的触点工艺是通过附加焊料沉积到焊料堆上的第二多孔障板过程中以避免损坏。还包括芯片金属和球界特性冶金间较低的触点电阻，作为位于沿芯片阵列周边触点的较好的溅射蚀刻结果。球界特性冶金包括如铬、铜、金这样的金属。
本发明的第二个方面是障板，包括相应于晶片上芯片阵列的触点在障板上的孔阵列。芯片阵列包括沿晶片外围伸出的周边芯片。附加虚设孔在障板上，位于相应于多数周边芯片的孔附近。附加虚设孔用于改善周边芯片的触点工艺。
本发明前面和其他的目标、特点和优点，通过本发明下面如附图中所说明的具体描述将变得更加明显的，其中：
图1a是晶片的顶视图，包括具有焊料堆的芯片；
图1b是图1a所示晶片的剖视图，画出了晶片金属界线和焊料堆触点的接线端金属间的氧化物，焊料堆位于图1a所示晶片的周边芯片上；
图2a是现有技术的障板的顶视图，包括钼层上的孔，用于在晶片上真空沉积接线端金属；
图2b是本发明障板的顶视图，包括图2a所示多孔障板的孔，加上晶片上周边芯片位置之外的附加孔；
图2c是图2b部分的扩展视图；
图2d是相应于图2b所示多孔障板部分的晶片的顶视图；
图2e是具有相应于产品芯片上阵列的，附加焊料堆阵列的晶片部分的顶视图；
图3a是在焊料堆已被回流后夹在晶片上的第二障板的剖面图，画出了晶片周边芯片上焊料堆的损坏；
图3b是在焊料堆被回流后夹在晶片上的第二障板的剖面视图，具有附加虚设焊料堆，画出了附加虚设焊料堆的损坏，但不损坏晶片周边芯片上的焊料堆；
图4a是现有技术对齐条的顶视图，位于晶片上周边芯片位置之外，用来将多孔障板与晶片对齐；
图4b是本发明对齐孔的顶视图，用来将多孔障板与晶片对齐；
图4c是印刷在晶片上的对齐标记的顶视图，用于与图4a的对齐条或图4b的对齐孔对齐；
图4a′是图4c晶片对齐标记的顶视图，是它们沿图4a的对齐条在X射线下的视图；
图4b′是图4c晶片对齐标记的顶视图，是它们沿图4b的对齐孔在X射线下的视图；
图5是C4多孔障板检查工具基准的顶视图，位于晶片周边芯片位置之外，本发明的多孔障板之上，并超过去除区，用于为多孔障板检查对齐；
图6是堆叠在本发明障板上的多孔障板的顶视图，以可选的对齐方法用于多孔障板检查；
图7a是夹在晶片上的障板的剖面图，准备用于溅射清洗和接线端金属沉积；
图7b是在溅射清洗和铬、铜和金以高的温度沉积后，图7a所示障板和晶片的剖面图；
图7c是在铅和锡以低于铬、铜和金沉积温度沉积后，图7b所示障板和晶片的剖面图；
图7d是在多孔障板被去除后，图7c所示障板和晶片的剖面图；
图7e是在焊料回流后，图7d所示障板和晶片的剖面图；
图8a是图7e所示步骤完成后，并且第二障板被夹在晶片上，用于锡帽沉积之后，晶片的剖视图
图8b是锡帽沉积完成后，第二障板和晶片的剖视图；并且
图8c是在第二障板被去除，留下锡覆盖的焊料堆后，图8b所示晶片的剖视图。
本发明的发明者发现，在普通产品的半导体晶片如晶片24中，周边芯片22的触点20具有比中心芯片26高的触点电阻，如图1a所示。我们发现较高的触点电阻与遗留在周边芯片22的触点20上的氧化物28有关，氧化物在氩等离子体蚀刻步骤，将接线端金属29在触点20进行真空沉积所产生，如图1b所示。氧化物28位于最终金属层30与接线端金属第一层，即铬层31之间。周边芯片22是晶片层24上最外面的完整印刷芯片。接线端金属29还包括铬层31上的铜和金和焊料堆32。最终金属层30由铜、铝或其它半导体组成。
发明者认识到，在氩等离子体蚀刻步骤，氧化物28没有沿晶片24外围38的金属层30上被完全去除。他们还认识到等离子体能量低于晶片24的外围38，因为障板34的几何形状在沿多孔障板外围46的孔39a处，不同于在多孔障板中心区域48的孔39b，如图2a所示。一个解释是等离子体能量相对于电流密度成比例增加。电流密度在多孔障板外围46较低，因为暴露于等离子体的多孔障板34的表面区域在多孔障板外围46较大，这是因为相应于晶片24上的周边芯片22，超出多孔障板34的周边芯片区域49，多孔障板34上没有用于触点的孔。由于没有孔意味着多孔障板半导体较高的区域，存在较低的电流密度。较低的电流密度提供了较低的能量密度，这样沿多孔障板34外围46的本地区域产生较少的蚀刻。还可能有其它的解释，但发明者发现通过在多孔障板34上提供附加的孔，以减少在周边芯片边缘的部分独立的孔，这样确实改善了触点净化。
发明者依据实验发现，在多孔障板外围46具有附加孔50的多孔障板34′上，如图2b和2c所示，减小了周边芯片22的触点20的触点电阻，解决了触点电阻的不均匀问题，有效地改善了在周边芯片22的触点20的氧化物28的蚀刻，提高了产出。
使用具有附加孔50的障板34′，氧化物层28在周边芯片22如同在晶片24更中间的芯片26一样被去除了。发明者发现，由于在障板34′上存在附加孔50，在周边芯片区域49的本地等离子体能量，随电流密度增加而成比例增加。发明者发现，多孔障板上周边芯片区域49附近的附加孔，改善了晶片24上等离子体的均匀性，所以周边芯片22具有与中心芯片26大约相等的能量密度。在半径超出多孔障板34的周边芯片区49处，附加孔50使等离子体电离区均匀，这样，改善了整个晶片24上触点蚀刻的均匀性。结果是，周边芯片22的触点电阻减小，整个晶片上触点电阻的均匀性显著改善。
甚至在发现多孔障板34′的附加孔50可以改善氧化物的去除之前，发明者发现位于晶片24上周边芯片22之外的附加焊料堆32′，可以解决他们在用锡覆盖的焊料堆制作晶片时发现的问题。发明者发现，在夹紧第二障板60(见图3a)，将低熔点焊料沉积在第一回流焊料堆触点32的锡覆盖过程，位于晶片24上周边芯片22上的焊料堆触点32经常损坏，锡覆盖过程在公开的美国专利5,729,896中描述，这里引入参考。他们还发现焊料堆的损坏，可以通过在晶片24上所有周边芯片22附近，提供几行附加焊料堆32′来避免。附加焊料堆32′对第二障板60在周边芯片22外提供支持。他们发现当这些附加堆32可能被损坏时，在功能周边芯片22上所需的焊料堆32由于它们的存在而免于受损。附加焊料堆通过在障板34′上提供附加孔50而形成，如上所述。这样，发明者发现一个解决方法——在多孔障板34′上提供附加孔50——解决了两个完全独立的问题。其中触点电阻问题是一个影响所有焊料堆晶片的问题，而焊料堆损坏问题是一个只影响到具有接受锡帽的焊料堆的晶片的问题。
在锡帽真空沉积之前，在将第二障板60夹到晶片24上的过程中，产生周边芯片22上焊料堆的损坏，，如图3a所示。在常规生产过程中，夹具69使多孔障板60靠着晶片24的裸露表面64变平。作为夹环69向下弯折第二障板60的结果，回流焊料堆32a的前几行可能被损坏，。如图3b所示，如果附加虚设焊料堆提供在晶片24上周边芯片22附近的空间，这一损坏可以避免。现在这些附加虚设焊料堆65可以被多孔障板34损坏，但芯片焊料堆32a本身保持原来的状况。通过在用于沉积原始焊料堆触点32的同一个障板34’上，提供附加孔50形成附加虚设焊料堆。
发明者还发现，在附加焊料堆32′的阵列内提供分块界线62可以实现分块。这样，产品芯片间的分块界线通过附加焊料堆连续，所以附加焊料堆不与分块锯刃相互干涉。
相似的，附加焊料堆32′的阵列在其它结构所需的区域被去掉，如多孔障板34上的条形图型101或孔型图型103，用来将多孔障板34与晶片24对齐，如图4a和图4b所示。具有条形图型101或孔型图型103的多孔障板34被放置在晶片24上，将图型105在晶片24上对齐，如图4c所示。晶片24上的图型105以用于开放触点20的相同光刻多孔障板形成。现有技术中条形图型101的一个问题是，回流后形成的焊料堆比触点焊料堆高，它们可能与用于检测晶片34的探针相互干涉。焊料堆较高是因为条形图型101的条107的长度和宽度比普通触点焊料堆32a的直径大的多，并且焊点在回流后凸起。发明者发现孔型图型是有利的，因为在晶片24上回流后形成堆的焊料高度，与在晶片24上形成的其它焊料堆32a的高度是一样的。而且发现，图型105通过孔型图型101的可见性比通过条形图型103的要好。孔型图型103的孔109紧凑在一起，使它们与圆形图型105的边界在晶片24上重叠。孔型图型103的孔113可以与晶片24的圆形图型115对中。这些因素的每一个导致多孔障板32′与晶片24的对齐的过程，比现有技术的条形图型所能达到的要好。孔型图型103的孔最好具有比用于产品芯片的孔相同或较小的尺寸。
他们还发现，在超过多孔障板34′的附加孔50处提供去除区64，可以实现用真空工具处理晶片24，使其精确地将晶片24放置在分块位置。多孔障板34和34′的去除区64将焊料堆沿晶片24外围38限制在去除区66以外。他们还发现在分块界线间附加焊料堆阵列填充所有位置，并伸出去除区66外，在晶片24上提供了焊料堆阵列，对第二阴影模提供了很好的支持，甚至如果芯片22、26上的焊料堆没有完全填充的焊料堆阵列也是如此。他们还发现在多孔障板34′的孔50中较高的填充，不会相反地影响触点电阻的均匀性。当然，在多孔障板34″上的孔和晶片24上的附加焊料堆的排行可以相应于产品芯片22、26上的布置，如图2e所示。这些部分芯片32′中每个的孔形图型伸展到去除区。如果晶片处理用非上述真空方法的其他方法完成，可以去除图2b、2c和2d所示的去除区。
障板34、34′制作的步骤之一被检查，本发明的发明者发现，附加孔50的存在可以与使用自动检查工具检查的多孔障板对齐发生相互干涉。这一检查工具，名为C4多孔障板检查工具B型，在普通受让的美国专利4,570,180中描述，这里引入参考。C4多孔障板检查工具与用于检查的多孔障板对齐，需要排行在图型的方形角的一组孔的存在。这个图型可以在现有技术多孔障板34的周边芯片的边缘得到，但是多孔障板34′的附加孔50可以去掉方形角图型。在一些情况中，一些附加孔50的去除产生多孔障板分块界线62′，这一去除提供了为C4多孔障板检查工具对齐步骤所需的方形角排行。但是，这依靠设计的特点，方形排行并不总是产生。
本发明的发明者采用的一项解决方法是，在图型上增加更多的附加孔到多孔障板上，如图2b所示，并且在图5中放大更高的倍数。附加孔用于对齐检查的工具，并且这个图型名为C4多孔障板检查工具基准68。如图2b所示，这些基准中的几个排行在多孔障板的周边，实现对齐。但是发明者认识到，如果C4多孔障板检查工具基准确实将焊料堆印刷在晶片外围的去除区，这是不希望的，因为这将与后面将晶片24放置在粘性膜上进行分块的真空处理相互干涉。这样，发明者将C4多孔障板检查工具基准放置在多孔障板位置，多孔障板位置是将多孔障板34′夹到晶片24上的夹环69所覆盖的位置。这样C4多孔障板检查工具基准，被安置在C4多孔障板检查工具的检查工具识别的区域之内，但是暴露于真空沉积的多孔障板区域之外，因为这些位置由保护环覆盖。C4多孔障板检查工具基准在所有设计中位于同一位置，并包含于用于其它标准特征的所有多孔障板的基本框架数据中。
一个同样工作很好的可选解决方案是，在多孔障板检查过程中为附加孔提供一个盖。这一用于附加孔的盖由胶带纸构成。它还可以由环70构成，具有剪切块72，与周边芯片22外侧边缘形状相匹配，如图6所示。环70只在多孔障板检查步骤中使用。环70的设计根据多孔障板设计数据，使用标准电路板生成软件，如Infinite Graphics公司的PAR软件。而另一解决方案是在附加的完全虚设芯片上加孔，这些芯片夹在有源周边芯片22和去除区64的孔之间。这些完全虚设芯片提供C4多孔障板检查工具检查所需的工具的合适角度的图型。伸到去除区64的部分芯片还可以解决第二阴影多孔障板的支持问题和等离子体能量问题，但这些一般不提供C4检查工具检查所需的合适角度的图型，如图2d所示。这样，部分芯片可以用于C4检查芯片检查所不需要或另外容纳的位置。
当多孔障板和晶片在接线端金属29沉积过程中处于高的温度，多孔障板34、34′上必须带有定位孔，因此这些孔可以定位在正确位置上。在室温时，多孔障板不如此对齐(除了在多孔障板中心)，如图7a所示。最高温度发生在铬、铜、金接线端金属29的沉积过程，并且多孔障板34、34′上必须具有定位孔，使它们通常在这一高温沉积过程中，与相应的晶片24上的触点20对中，如图7b所示。图7a-7e中是并非成比例的或极度夸大的多孔障板34′和晶片24在室温的非对齐情况。在晶片24夹到多孔障板32′后进行的氩溅射清洗步骤中，根据非对齐情况的实际温度不足以模糊触点，如图7a所示。
多孔障板34′由环69和夹具(未画出)夹到晶片24上。然后，在焊料沉积过程中，温度较低，于是接线端金属29的焊料堆部分32、32′偏心沉积，如图7c和图7d所示，特别是沿着晶片24的外围区域。图7d画出了接线端金属29在多孔障板32′去除后的情况。然而，在后续的回流步骤中，焊料堆部分32、32′将自身对中在铬-铜-金上，提供回流焊料堆32a、32a′和接线端金属29a、29a′，如图7e所示。
相似的，用于锡帽沉积的第二障板78，必须使自身上的孔80对温度进行热补偿，这里温度是指晶片和多孔障板在回流的焊料堆32a、32a′上进行锡帽沉积达到的温度，如图8b所示。图8a画出了室温时放置在晶片24上的多孔障板，画出了第二障板孔84不直接位于回流焊料堆32a、32a′上，特别是沿晶片24的外围的情况。在锡帽82沉积后，多孔障板78被去除，将锡帽82留在回流焊料堆32a、32a′上。
本发明的几个实施例还有其改型在这里已经予以具体描述，并由所附图示说明，很明显具有共同设计构思的各种进一步改型是可能的，这些可能的改型也包括在本发明的范围之内。上述说明书中的叙述不会将发明限制在比所附的权利要求更窄的范围内，给出的例子只用于说明而不是排除。

Claims (50)

1一种晶片，包括：
一个芯片阵列，具有触点，所述触点包括焊料堆，所述芯片阵列包括沿晶片外围伸出的周边芯片；和
附加虚设焊料堆，位于多数所述周边芯片附近，其中所述附加虚设焊料堆用于改善所述周边芯片的触点工艺。
2如权利要求1所述的晶片，其特征在于，所述附加虚设焊料堆对障板提供支持，障板用于在所述焊料堆上沉积材料，使所述障板不会损坏周边芯片的焊料堆。
3如权利要求2所述的晶片，其特征在于，所述焊料堆包括一层所述材料。
4如权利要求3所述的晶片，其特征在于，所述材料包括锡。
5如权利要求3所述的晶片，其特征在于，所述材料沉积在回流堆上。
6如权利要求1所述的晶片，其特征在于，所述附加虚设焊料堆在锯刃线处被去除。
7如权利要求6所述的晶片，其特征在于，所述附加虚设焊料堆在沿所述晶片外围的环形去除区处被去除。
8如权利要求7所述的晶片，其特征在于，所述附加虚设焊料堆在对齐辅助工具区域被去除。
9如权利要求8所述的晶片，其特征在于，所述对齐辅助工具包括一个焊料堆图型。
10如权利要求9所述的晶片，其特征在于，所述焊料堆图型包括一个图型，具有比用于触点的更紧凑的焊料堆空间。
11如权利要求7所述的晶片，其特征在于，周边芯片附近的所述附加虚设焊料堆，在所述锯刃线外所述阵列的所有位置，以堆的规则阵列排行，并填满所述去除区。
12如权利要求1所述的晶片，其特征在于，所述附加虚设焊料堆包括一个在所述周边芯片附近的单行堆。
13如权利要求1所述的晶片，其特征在于，所述附加虚设焊料堆包括相应于部分芯片的堆的附加图型。
14如权利要求1所述的晶片，其特征在于，所述改善所述周边芯片的触点工艺是，在晶片上触点绝缘体更均匀的等离子体蚀刻，和周边芯片更低的电阻。
15如权利要求1所述的晶片，其特征在于，所述周边芯片的触点具有与非周边芯片大约相等的触点电阻。
16如权利要求1所述的晶片，其特征在于，所述周边芯片的触点具有与非周边芯片大约相等的绝缘体。
17一种障板，包括：
一个在障板上的孔阵列，相应于晶片上芯片阵列的触点，所述芯片阵列包括沿晶片外围伸出的周边芯片；和
附加在障板上的虚设孔，在相应于多数所述周边芯片孔的附近，其中所述附加虚设孔用于改善所述周边芯片的触点工艺。
18如权利要求17所述的障板，其特征在于，所述附加虚设孔用于提供附加虚设焊料堆，以支持第二障板，它用于将附加材料层沉积到所述堆上，使所述第二障板不损坏周边芯片焊料堆。
19如权利要求18所述的障板，其特征在于，所述用于沉积附加材料层的孔位于用于补偿沉积锡时的温度的位置。
20如权利要求18所述的障板，其特征在于，所述附加材料层用于通过所述第二障板，将锡沉积到芯片的回流焊料堆上。
21如权利要求17所述的障板，其特征在于，所述附加虚设孔在锯刃线处去除。
22如权利要求21所述的障板，其特征在于，所述附加虚设孔在沿所述障板外围，超出所述周边芯片和超出所述虚设孔的环形去除区去除。
23如权利要求17所述的障板，其特征在于，所述周边芯片的所述改善触点工艺是将与所述周边芯片触点接触的绝缘体去除，和所述周边芯片的更低的触点电阻。
24如权利要求17所述的障板，其特征在于，所述附加虚设孔位于实质上所有所述周边芯片孔的附近。
25如权利要求17所述的障板，其特征在于，所述孔相应于所述周边芯片，位于补偿沉积铬、铜、金时的温度的位置。
26一种制作半导体晶片的方法，包括步骤：
(a)提供一种晶片，包括一组具有触点的芯片阵列，所述触点包括焊料堆，所述芯片阵列包括沿晶片外围伸出的周边芯片；并且
(b)提供附加虚设焊料堆，位于多数所述周边芯片附近，其中所述附加虚设焊料堆用于改善所述周边芯片的触点工艺。
27如权利要求26所述的制作半导体晶片的方法，其特征在于，所述步骤(b)包括步骤：
1)提供一个包括触点的晶片，；
2)提供一个阴影多孔障板，包括相应于所述附加虚设焊料堆的附加孔，并将所述多孔障板的孔与所述晶片的触点对齐；
3)通过所述多孔障板上的所述孔，等离子体蚀刻所述触点的氧化物，其中周边芯片触点上的氧化物，也同非周边芯片触点大约一样被蚀刻，作为所述附加孔存在的结果；并且
4)在所述孔中沉积用于焊料堆的焊料和球界特性冶金。
28如权利要求27所述的制作半导体晶片的方法，其特征在于，所述周边芯片的所述改善的触点工艺是，在晶片上触点氧化物的更均匀的等离子体蚀刻，和周边芯片更低的触点电阻。
29如权利要求28所述的制作半导体晶片的方法，其特征在于，所述周边芯片的触点具有与非周边芯片大约相等的触点电阻。
30如权利要求28所述的制作半导体晶片的方法，其特征在于，所述周边芯片的触点具有与非周边芯片大约相等的氧化物。
31如权利要求27所述的制作半导体晶片的方法，其特征在于，还包括回流所述焊料堆的步骤。
32如权利要求31所述制作半导体晶片的方法，其特征在于，还包括提供一个焊料堆冒障板，其中提供附加虚设焊料堆的所述步骤(b)，是用来对所述焊料堆冒障板提供支持，多孔障板用于在所述焊料堆上沉积材料，使所述焊料堆冒障板不损坏周边芯片焊料堆。
33如权利要求32所述的制作半导体晶片的方法，其特征在于，还包括通过所述焊料堆冒障板沉积一层所述材料在所述焊料堆上。
34如权利要求33所述的制作半导体晶片的方法，其特征在于，所述材料包括锡。
35如权利要求26所述的制作半导体晶片的方法，其特征在于，所述附加虚设焊料堆在锯刃线处去除。
36如权利要求26所述的制作半导体晶片的方法，其特征在于，所述附加虚设焊料堆在沿晶片外围的环形去除区去除。
37如权利要求26所述的制作半导体晶片的方法，其特征在于，所述附加虚设孔位于实质上所有所述周边芯片孔的附近。
38一种用于制作障板的方法，包括如下步骤：
a)提供一个在障板上的孔阵列，相应于晶片上芯片阵列的触点，所述芯片阵列包括沿晶片外围伸出的周边芯片，
b)提供在障板上的附加虚设孔，位于相应于多数所述周边芯片的孔附近，其中所述附加虚设孔用于改善所述周边芯片的触点工艺。
39如权利要求38所述的制作障板的方法，其特征在于，所述改善所述周边芯片的触点工艺是，附加虚设焊料堆支持第二障板，它用于在所述焊料堆上沉积附加层材料，使所述第二障板不损坏周边芯片焊料堆。
40如权利要求38所述的制作障板的方法，其特征在于，所述附加虚设孔在锯刃线处去除。
41如权利要求40所述的制作障板的方法，其特征在于，所述附加虚设孔在环形去除区，沿所述障板外围超出周边芯片和超出虚设孔的位置去除。
42如权利要求40所述的制作障板的方法，其特征在于，还包括检查多孔障板的步骤，沿分块界线边缘使用虚设孔，将障板与检查设备对齐。
43如权利要求40所述的制作障板的方法，其特征在于，还包括使用附加孔的图型检查多孔障板的步骤，所述附加孔超过相应于所述周边芯片的孔，所述附加孔用于将障板与检查工具对齐，其中所述附加孔图型不印在晶片上。
44如权利要求43所述的制作障板的方法，其特征在于，所述附加孔的图型的位置使其可以被保护环覆盖。
45如权利要求40所述的制作障板的方法，其特征在于，还包括检查多孔障板的步骤，使用所述附加虚设孔的遮盖物实现。
46如权利要求40所述的制作障板的方法，其特征在于，所述用于附加孔的遮盖物是一个环，其内边缘相应于周边芯片的外边缘。
47如权利要求38所述的制作障板的方法，其特征在于，所述周边芯片的所述改善触点工艺是，晶片上触点更均匀的等离子体蚀刻和周边芯片较低的触点电阻。
48一种晶片，包括：
一个晶片阵列，具有焊料堆触点；和
一个焊料堆的图型，用于将晶片与焊料堆沉积多孔障板对齐，焊料堆图型包括堆，其直径大约等于或会小于所述焊料堆触点。
49如权利要求48所述的晶片，其特征在于，所述焊料堆的对齐具有比所述焊料堆触点更紧凑的空间。
50如权利要求48所述的晶片，其特征在于，所述焊料堆的对齐的位置相应于晶片上第二对齐图型的边缘。
CNB001338528A 1999-10-21 2000-09-16 晶片整合刚性支持环 Expired - Lifetime CN1199263C (zh)

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