CN1309070C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN1309070C
CN1309070C CNB2004100035435A CN200410003543A CN1309070C CN 1309070 C CN1309070 C CN 1309070C CN B2004100035435 A CNB2004100035435 A CN B2004100035435A CN 200410003543 A CN200410003543 A CN 200410003543A CN 1309070 C CN1309070 C CN 1309070C
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copper layer
film
semiconductor device
copper
lower floor
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CN1519923A (zh
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小田典明
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Renesas Electronics Corp
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NEC Corp
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Abstract

一种在半导体衬底上带有键合焊盘的半导体器件包括:形成在键合焊盘的下表面上的上层铜层,它们中间插有阻挡金属,并且其具有大于在其里面形成电路互连的层的铜面积比;以及与上层铜层电绝缘的下层铜层,并且其形成为比上层互连更靠近半导体衬底,其中,在上层铜层和下层铜层之间插入比低k膜硬的介电SiO2膜。

Description

半导体器件及其制造方法
技术领域
本发明涉及一种带有用于引线键合的键合焊盘的半导体器件以及制造这种半导体器件的方法。
背景技术
当在采用铜互连的现有技术的半导体器件中在铜互连上方形成键合焊盘时,在有些情况中,键合部位会位于偏移铜互连上方的位置上(参见公开号为2001-15516的日本专利申请,第4-5页,图2)。
图1是个剖面结构图,示出了现有技术的半导体器件的结构的示例,在形成在半导体衬底10上的铜互连700上提供多个铜焊盘,最顶层铝互连730形成在最顶层铜焊盘710上方,它们之间夹有阻挡金属720。最顶层铝互连730的键合部位735位于偏移铜互连700的位置上。因而,在键合时产生的压力被施加到位于键合部位735下面的钝化绝缘膜740以及层间介电膜750上。因此,键合时压力对铜互连700的影响能够得到降低以及表面上的铜互连700的暴露能够得到预防。
但是,现有技术的上述半导体器件存在几个缺点。
第一,由于这是一种键合部位位于偏移铜互连的位置上的结构,键合焊盘的面积大于键合部位位于铜互连的正上方的情况中的键合焊盘,因此这种结构会使芯片的尺寸变大。
其次,如果键合部位下面存在其介电常数相对低于氧化物膜的低k膜,则在检测或键合时加载探针会向下挤压键合焊盘且可能致使位于键合焊盘下面的层间介电膜中发生断裂或者可能致使键合焊盘中的膜剥落。
发明内容
为了解决现有技术的上述问题而开发出了本发明,且本发明的目标是提供一种半导体器件以及制造这种半导体器件的方法,这种半导体器件改善了在检测和键合时抵抗对键合焊盘的冲击的能力(在下文中称为“抗冲击能力”)。
用于实现上述目标的本发明的半导体器件包括:形成在半导体衬底上的键合焊盘;形成在这些键合焊盘的下表面上的上层铜层,它们中间夹有阻挡金属;以及下层铜层,其比上层铜层更靠近半导体衬底;其中,下层铜层具有小于上层铜层的铜面积比,其中,在上层铜层和下层铜层之间插入比低k膜硬的介电SiO2膜。
本发明的另一半导体器件包括:形成在半导体衬底上的键合焊盘;形成在键合焊盘的下表面上的上层铜层,它们中间夹有阻挡金属;以及下层铜层,其比上层铜层更靠近半导体衬底;其中,上层铜层与下层铜层电绝缘,且上层铜层的铜面积比大于形成在半导体衬底上的电路互连层。
在每种上述的半导体器件中,上层铜层的铜面积比可以是至少70%。
此外,键合焊盘和上层铜层的平面面积可以基本相同。
进而,上层铜层可以由多个铜层构成。在这种情况中,上层铜层中的每个铜层的铜面积比可以相同。此外,半导体器件还可以包括:位于上层铜层中的每个铜层之间的层间介电膜;以及由铜组成的通孔栓塞,其嵌入层间介电膜中;其中,上层铜层中的每个铜层通过通孔栓塞连接。进而,位于上层铜层的最顶层中的铜层的铜层图形和连接至这个铜层图形的通孔栓塞可以被嵌入由第一材料所组成的介电膜中。
下层铜层的铜面积比可以是至少15%且不大于95%。
下层铜层可以由多个铜层组成。在这种情况中,下层铜层中的每个铜层的铜面积比可以相同。进而,可以在下层铜层中的每个铜层之间插入由第一材料所组成的介电膜。下层铜层中的每个铜层可以由嵌入介电膜的铜层图形构成,其中,介电膜由其介电常数相对低于第一材料的第二材料组成。第二材料可以是比第一材料软的物质。进而,由第二材料所组成的介电膜可以包含下述膜中的任何一种:SiOC膜、碳化硅(SiC)膜、SiOF膜、多孔二氧化硅(SiO2)膜、多孔SiOC膜和带有梯型氢化硅氧烷的梯型氧化物膜。
可以在下层铜层中的每个铜层之间插入由其介电常数相对低于第一材料的第三材料所组成的介电膜。在这种情况中,第三材料可以是比第一材料软的物质。此外,由第三材料所组成的介电膜可以包含下述膜中的任何一种:SiOC膜、碳化硅(SiC)膜、SiOF膜、多孔二氧化硅(SiO2)膜、多孔SiOC膜和带有梯型氢化硅氧烷的梯型氧化物膜。
阻挡金属可以包含氮化钛(TiN)或氮化钽(TaN)。
半导体器件还可以包括:位于半导体衬底上的内部电路;以及电连接至内部电路的辅助铜互连;并且这些辅助铜互连可以通过通孔电连接至一部分键合焊盘。
在制造本发明的半导体器件的方法中,通过大马士革方法形成上层铜层和下层铜层。
在制造本发明的半导体器件的另一方法中,通过双大马士革方法形成位于上层铜层的最顶层中的铜层的铜层图形和连接至这个铜层图形的通孔栓塞。
如上面说明中所描述的本发明利用了铜的一个特性,即铜具有比氧化物膜大的弹性,弹性是可以回弹从外部施加的力的属性。换言之,本发明的半导体器件具有这样一种结构:位于键合焊盘下面的上层铜层和下层铜层起到抗冲击层的作用,其阻止了冲击被传递到键合焊盘的下面。
在上层铜层的铜面积比为至少70%的本发明中,检测和键合时的抗冲击能力得到较大的改善。
在键合焊盘和上层铜层的平面面积基本相同的本发明中,键合焊盘和上层铜层之间能够获得足够的接触面积。
在上层铜层由多个铜层构成的本发明中,冲击被分布在每个铜层中。此外,在上层铜层中的每个铜层的铜面积比相同的本发明中,冲击分布得更加均匀。
在上层铜层中的每个铜层通过通孔栓塞连接的本发明中,对最顶层的冲击可以更容易地分布到其它层中。
在由第一材料所组成并且嵌有上层铜层的最顶层介电膜和连接至这个最顶层的通孔栓塞的介电膜是硬质材料的本发明中,在键合时受到最大冲击的最顶层和通孔栓塞由硬质介电膜均匀地支持。
在下层铜层的铜面积比为至少15%且不大于95%的本发明中,可以获得对抗冲击能力的更大的改善。因而,下层铜层可以用作具有至少15%且至多95%的铜面积比的电路互连层,且键合焊盘下面的区域能够得到更有效的利用。
在下层铜层由多个铜层构成的本发明中,传递至下层铜层的冲击力被分布在每个铜层中。通过使下层铜层中的每个铜层的铜面积比相同,传递至下层铜层的冲击能够分布得更加均匀。
在下层铜层中的每个铜层之间包括入由第一材料所组成的介电膜的本发明中,下层铜层能够更加均匀地由介电膜支持。
在下层铜层中的每个铜层由嵌入介电膜中的铜层图形所构成的本发明中,同一铜层内的铜层图形之间的电容能够得到降低,其中,介电膜由其介电常数相对低于第一材料的第二材料所组成。
在由第三材料所组成的介电膜被用作下层铜层的层间介电膜的本发明中,形成在与下层铜层相同的水平上的多个互连层之间的电容能够得到降低,其中,第三材料包含其介电常数相对低于第一材料的材料。
在氮化钛(TiN)和氮化钽(TaN)中的任何一种被用作阻挡金属的本发明中,阻挡金属能够防止铝和铜在位于阻挡金属的上面和下面的层之间互相扩散。
在键合焊盘被连接至辅助铜互连的本发明中,即使当在键合时出现的冲击致使上层铜层中发生断裂并且导致缺陷连接的时候,也能够保证键合焊盘和内部电路之间的电连接。
参考附图,下面的描述将使本发明的上述和其它目标、特征和优点更加清晰明了,其中,附图示出了本发明的示例。
附图说明
图1是个剖面结构图,示出了现有技术的半导体器件的结构的一个示例。
图2A是个剖面结构图,示出了在作为本发明的第一实施例的半导体器件中包含键合焊盘的区域的结构。
图2B是个示意性视图,示出了第一上层铜层的虚拟图形的示例。
图2C是个示意性视图,示出了第一下层铜层的虚拟图形的示例。
图3是作为本发明的第二实施例的半导体器件的剖面结构图。
图4A是作为本发明的第三实施例的半导体器件的平面图。
图4B是示出了沿图4A中的A-A’虚线切开的部分的剖面结构图。
图5是个剖面结构图,示出了作为本发明的第四实施例的半导体器件的结构。
具体实施方式
本发明的半导体器件提供有:形成在键合焊盘下面的上层铜层,它们中间插有阻挡金属;以及与这个上层铜层电绝缘的下层铜层;其中,这些铜层作为抗冲击层。
第一实施例
图2A是个剖面结构图,示出了在作为本发明的第一实施例的半导体器件中包含键合焊盘的区域的结构。
现在,参考图2A,本实施例的半导体器件包括用于改善抗冲击能力的上层铜层100,这个形成在键合焊盘130下面的上层铜层100包括作为其主要组分且带有铝(Al)的金属膜,阻挡金属插在上层铜层100和键合焊盘130之间。提供的阻挡金属用于防止含在键合焊盘130中的铝与含在上层中的组分发生反应。上层铜层100与键合焊盘130具有基本相同的平面面积(指在制造误差的范围之内平面面积相同),且上层铜层100从下面均匀地支持键合焊盘130。
为了提供额外的抗冲击能力,在上层铜层100的下面提供了与上层铜层100电绝缘的下层铜层200,在它们中间插有氧化物膜(SiO2膜)32。二氧化硅膜(SiO2膜)32是比低k膜硬的介电膜。在上层铜层100和下层铜层200之间插入这个SiO2膜32能够防止在键合时由于施加的力而导致的凹陷。
上层铜层100由第一上层铜层110和第二上层铜层120组成,并且第一上层铜层110和第二上层铜层120通过主要由铜组成的通孔栓塞140进行电连接。因此,上层铜层100是双层结构,从而施加到键合焊盘130上面的冲击被分布到每个层之间并且获得了对抗冲击能力的改善。形成为上层铜层100的铜层的层数可以是三层或更多。
由于第二上层铜层120和通孔栓塞140受到在键合时施加的力中的大部分,优选采用比低k膜硬的介电膜(SiO2膜),作为埋置这些构成组分且由第一材料组成的介电膜。在本实施例中,第二上层铜层120和通孔栓塞140均分别埋置在二氧化硅(SiO2)膜42和44中,这些膜42和44由第一材料组成。二氧化硅(SiO2)膜42和44很硬,因此第二上层铜层120和通孔栓塞140由这些二氧化硅(SiO2)膜42和44均匀地支持。
下层铜层200由两层组成,即第一下层铜层210和第二下层铜层220,且第一下层铜层210和第二下层铜层220被二氧化硅(SiO2)膜22绝缘。对下层铜层200使用多个铜层提供了与上述上层铜层100相同的效果。
在第一下层铜层210的铜层图形之间插入由梯型氧化物膜和二氧化硅(SiO2)膜组成的叠层介电膜14。这种情况中的梯型氧化物膜是L-Ox(NEC电子公司的商标(现在正在申请之中)),它是带有梯型氢化硅氧烷的低k膜。类似地,在第二下层铜层220的铜层图形之间插入由L-Ox膜和二氧化硅(SiO2)膜所组成的叠层介电膜24。利用由其介电常数相对低于第一材料的第二材料所组成的介电膜(L-Ox膜)形成叠层介电膜14和24,降低了铜互连的互连之间的电容,铜互连与下层铜层200形成在同一水平上。
虽然未在图2A中示出,除了含有上述键合焊盘的区域之外,在半导体衬底10上还提供了包括诸如晶体管、电阻器和电容器等半导体元件和用于互连这些半导体元件的电路互连的内部电路。电路互连用诸如与上层铜层100或下层铜层200形成在同一层上的铜层的导电层、形成在半导体衬底10上面的扩散层以及掺有杂质的多晶硅来形成。键合焊盘130和内部电路之间的连接通过例如上层铜层100来实现。
接下来将对上层铜层100和下层铜层200的平面图形进行说明。根据上层铜层100和下层铜层200起到用于分布施加到键合焊盘130上的冲击的虚拟层的作用而不是构成内部电路的互连的观点,上层铜层100和下层铜层200在下面的说明中称为“虚拟图形”。
图2B是个示意性视图,示出了第一上层铜层110的虚拟图形(平面图形)的示例,剖面结构沿图2A中的A-A’虚线切开。第二上层铜层120的虚拟图形与第一上层铜层110的虚拟图形相同,因此在此略去对它的说明。
如图2B所示,在第一上层铜层110的虚拟图形中散布多个叠层介电膜34的正方形图形,使得铜的整体表面密度是均匀的。铜面积比是被铜占据的面积的比例(被铜占据的面积比),且抗冲击能力随着这个比例的增加而得到改善。在这种情况中,为了提高抗冲击能力,虚拟图形的铜面积比被做得大于形成有电路互连的铜层的铜面积比。根据目前所获得的实验结果,虚拟图形的铜面积比优选为至少70%。此外,为了防止在铜层的CMP(化学机械抛光)工艺中发生变形,虚拟图形的铜面积比优选为不大于95%。
图2C是个示意性视图,示出了第一下层铜层210的虚拟图形(平面图形)的示例,剖面结构沿图2A中的B-B’虚线切开。第二下层铜层220的虚拟图形与第一下层铜层210的虚拟图形相同,因此在此略去对这个虚拟图形的说明。
如图2C所示,在第一下层铜层210的虚拟图形中散布多个叠层介电膜14的交叉(cross)图形,使得整体铜表面密度是均匀的。为了改善抗冲击能力,第一下层铜层210的铜面积比优选为至少15%,进而,由于与根据上层铜层100所阐述的相同的原因,第一下层铜层210的铜面积比优选为不大于95%。
由于下层铜层200受到比上层铜层100小的键合时所产生的压力,优选地,下层铜层200的铜面积比等于或小于上层铜层100的铜面积比。
此外,下层铜层200的虚拟图形与上层铜层100电绝缘,因此,这个虚拟图形可以用作电路互连的图形。以这种方式把下层铜层200作为电路互连层使用,可以实现有效利用键合焊盘130下面的区域。但是,这种情况中的下层铜层200的铜面积比小于上层铜层100的铜面积比。
进而,第一下层铜层210和第二下层铜层220被层间介电膜电绝缘,但是这些层可以通过通孔栓塞进行电连接。
接下来将参考图2A对制造上述实施例的半导体器件的方法进行说明。下面的说明只涉及制造用于改善键合焊盘的抗冲击能力的组件的程序,这些组件具有本实施例的半导体器件的突出特性,因此略去对形成在与作为抗冲击层的每个铜层相同的水平上的电路互连的详细说明。
在半导体衬底10上形成诸如晶体管、电阻器和电容器(未在图中示出)的半导体元件,通过CVD方法在这些元件上形成300-500nm厚的二氧化硅(SiO2)膜12,作为层间介电膜,接着形成30-50nm厚的限位SiCN膜13,作为用于限止蚀刻的膜(在下文中称为“蚀刻限位膜”)。接下来,通过涂敷和烧结工艺在限位SiCN膜13上形成300-500nm厚的L-Ox膜并在这个L-Ox膜上生长100-200nm厚的二氧化硅(SiO2)膜,以形成由L-Ox膜和二氧化硅(SiO2)组成的叠层介电膜14。接下来通过光刻工艺在叠层介电膜14上形成抗蚀图形,接着以这个抗蚀图形作为掩膜进行蚀刻,以在叠层介电膜14上形成规定的虚拟图形和用于形成电路互连(未在图中示出)的互连沟槽。然后除去抗蚀图形。
接下来,在形成有虚拟图形和互连沟槽的叠层介电膜14上顺序形成30-50nm厚的阻挡金属和50-200nm厚的籽晶层,另外通过电镀方法在这些层上形成500-1000nm厚的铜膜。在采用CMP工艺对铜膜进行研磨直到暴露出叠层介电膜14的上表面之后,形成30-50nm厚的封盖SiCN膜15,作为用于防止铜扩散的膜。从而完成了如图2C所示的带有虚拟图形的第一下层铜层210。
在形成第一下层铜层210之后,在第一下层铜层210上形成300-500nm厚的二氧化硅(SiO2)膜22,并且通过与上述第一下层铜层210的制造过程相同的程序,形成第二下层铜层220。
接下来,在第二下层铜层220上形成300-500nm厚的二氧化硅(SiO2)膜32和30-50nm厚的限位SiCN膜33。然后,形成由300-500nm厚的L-Ox膜和100-200nm厚的二氧化硅(SiO2)膜组成的叠层介电膜34。接下来通过光刻工艺在叠层介电膜34上形成抗蚀图形,接着通过蚀刻工艺在叠层介电膜34上形成规定的虚拟图形和用于形成未在图中示出的电路互连的互连沟槽。然后除去抗蚀图形。
接下来,在形成有虚拟图形和互连沟槽的叠层介电膜34上顺序形成30-50nm厚的阻挡金属、50-100nm厚的籽晶层和600-1000nm厚的铜膜。接下来,通过CMP工艺对铜膜进行研磨直到暴露出叠层介电膜34的上表面,接着形成30-50nm厚的封盖SiCN膜35。通过这种方式,形成了如图2B所示的带有虚拟图形的第一上层铜层110。
接下来,在第一上层铜层110上顺序生长300-500nm厚的二氧化硅(SiO2)膜42、50-70nm厚的限位SiCN膜43和300-500nm厚的二氧化硅(SiO2)膜44。接下来通过光刻工艺在二氧化硅(SiO2)膜44上形成用于形成通孔栓塞140的抗蚀图形,并且以这个抗蚀图形作为掩膜进行蚀刻直到暴露出封盖SiCN膜35,以形成通孔部分,接着除去抗蚀图形。然后,通过光刻工艺在二氧化硅(SiO2)膜44上形成用于形成第二上层铜层120的抗蚀图形,并且以这个抗蚀图形作为掩膜进行蚀刻,以在二氧化硅(SiO2)膜44形成如图2B所示的虚拟图形。然后,在除去这个抗蚀图形之后,通过蚀刻除去作为通孔的底表面的封盖SiCN膜35。
接下来,顺序形成30-50nm厚的阻挡金属、50-100nm厚的籽晶层和600-1000nm厚的铜膜。然后,通过CMP工艺对铜膜进行研磨直到暴露出二氧化硅(SiO2)膜44的上表面,接着形成30-50nm厚的封盖SiCN膜45。通过这种方式,形成了如图2B所示的带有虚拟图形的第二上层铜层120。
接下来,在封盖SiCN膜45上形成300-500nm厚的二氧化硅(SiO2)膜52,并且通过光刻工艺在二氧化硅膜52上形成用于形成开口的抗蚀图形,其中,开口用于连接第二上层铜层120和键合焊盘130。接下来,以抗蚀图形作为掩膜对二氧化硅(SiO2)膜52和底层封盖SiCN膜45进行蚀刻,以形成开口。然后,在除去抗蚀图形之后,通过溅射工艺顺序形成作为阻挡金属的100-200nm厚的氮化钛(TiN)膜54、800-1000nm厚的Al-Cu膜(铝对铜的比例为99.5%至0.5%)和作为消反射涂层的50-100nm厚的氮化钛(TiN)膜64。
然后,通过蚀刻工艺在氮化钛(TiN)膜64上形成用于形成键合焊盘130的抗蚀图形,接着以这个蚀刻图形作为掩膜,对氮化钛(TiN)膜64、底层Al-Cu(铝对铜的比例为99.5%至0.5%)膜和氮化钛(TiN)膜54进行蚀刻。这次蚀刻后所留下的Al-Cu(0.5%)膜变成键合焊盘130。在形成键合焊盘130后除去抗蚀图形。接下来形成100-200nm厚的二氧化硅(SiO2)膜62,以覆盖键合焊盘130上的TiN膜64,然后进一步在二氧化硅(SiO2)膜62上形成800-1000nm厚的聚酰亚胺膜66。
最后,通过蚀刻工艺在聚酰亚胺膜66上形成用于形成开口的的抗蚀图形,其中,开口用于暴露出键合焊盘130的规定部位(实现键合的部位),并且以这个蚀刻图形作为掩膜,对聚酰亚胺膜66、底层二氧化硅(SiO2)膜62和氮化钛(TiN)膜64进行蚀刻,以暴露出键合焊盘130。从而获得了具有如图2A所示的结构的半导体器件。
根据如上所描述的本实施例的半导体器件,在键合焊盘130的下面形成其弹性(弹性是可以回弹从外部施加的力的属性)比氧化物膜高的铜层,它们中间插有阻挡金属,从而获得了能够排斥检测和键合时由探针所施加的力以及阻止冲击被传递到键合焊盘130下面的结构。因此,这种半导体器件的抗冲击能力能到改善,且即使当探针被放在键合焊盘上面时,焊盘也不会受到损坏。
此外,在键合焊盘130下面提供铜层使得超声波能够被充分地传递至金引线和键合焊盘130,而没有被诸如L-Ox膜的低k膜所吸收,其中,超声波用于在键合时实现金引线和键合焊盘130的共熔键合。因而,金引线和键合焊盘的紧密粘合得到加强且引线拉伸强度得到提高。
此外,键合焊盘部位的实际金属膜厚度是键合焊盘下面的铝和铜层的总厚度,从而进一步增强了对抗检测和键合的硬度。因而,能够降低施加到底层L-Ox膜的邻近处的负载并且能够防止在层间介电膜中发生断裂。
第二实施例
在上述第一实施例的结构中,键合焊盘和内部电路的连接通过上层铜层实现,但是也可以采用键合焊盘被连接至辅助铜互连的结构,其中辅助铜互连被连接至内部电路。接下来将对应用这种类型的连接结构的半导体器件进行说明。
图3是作为本发明的第二实施例的半导体器件的剖面结构图。如图3所示,在本实施例的半导体器件中,在与第二上层铜层120相同的水平上形成连接至内部电路的辅助铜互连125。辅助铜互连125和键合焊盘130通过通孔150电连接。这种结构的其它部分基本上与上述第一实施例的结构相同。
接下来将对制造本实施例的半导体器件的方法进行说明。下面的说明只限定于那些区别本实施例的部分,且略去对与第一实施例相同的步骤的详细说明。
从开始一直到第一上层铜层110的形成,半导体器件的制造与第一实施例中的程序相同。在形成第一上层铜层110之后,在如图2A所示的二氧化硅膜44中形成用于形成辅助铜互连125的沟槽,并且在形成第二上层铜层120的时候形成辅助铜互连125。然后,当在二氧化硅(SiO2)膜52上形成用于提供开口的抗蚀图形时,在这个抗蚀图形中包含入用于形成通孔150的图形,其中,开口用于连接第二上层铜层120和键合焊盘130,通孔150用于连接辅助铜互连125和键合焊盘130。通过与第一实施例相同的程序,顺序形成氮化钛(TiN)膜54、键合焊盘130、氮化钛(TiN)膜64、二氧化硅(SiO2)膜62和聚酰亚胺膜66。
在本实施例的半导体器件中,除了具有第一实施例中所描述的效果外,还具有下述的效果。如果在检测和键合时由于对键合焊盘的冲击而导致在第二上层铜层120中发生断裂,则可以预见在第一实施例的结构中不能保证第二上层铜层120和内部电路之间的导电。但是,在本实施例中,即使发生这种断裂,通过通孔150和辅助铜互连125,也能够保证键合焊盘130和内部电路之间的导电。
进而,在本实施例中,由于键合焊盘130通过辅助铜互连125电连接至内部电路,上层铜层100和内部电路无需连接。
此外,虽然在上面的说明中辅助铜互连125形成在与第二上层铜层120相同的水平上,本发明并不限定于这种形式,且辅助铜互连125也可以形成在与诸如第一上层铜层110的其它导电层相同的水平上。
第三实施例
可以在上述第二实施例的结构中排列多个键合焊盘。现在将对应用这种类型的结构的半导体器件进行说明。
图4A是作为本发明的第三实施例的半导体器件的平面图,且图4B是示出了沿图4A中的A-A’虚线切开的结构的剖面图。在图4A和图4B中,在键合焊盘130上形成如图2A中所示的氮化钛(TiN)膜64、二氧化硅(SiO2)膜62和聚酰亚胺膜66,但为了说明方便在此略去这些结构。
如图4A所示,本实施例的半导体器件是外部焊盘132和内部焊盘134沿不同的线排列的结构,其中,外部焊盘132是靠近划线600的键合焊盘,内部焊盘134是比外部焊盘132更靠近芯片的中心的键合焊盘。同时包含外部焊盘132和内部焊盘134的区域的剖面结构是接着将描述的如图4B所示的结构。
在与第一下层铜层210相同的水平上形成用于电路互连的第一下层铜互连212。在与第二下层铜层220相同的水平上形成用于电路互连的第二下层铜互连222。在与第二上层铜层120相同的水平上形成用于电路互连的第二上层铜互连122。
在外部焊盘132的下面形成第二上层铜层120、第一上层铜层110、第二下层铜层220、第一下层铜层210,作为抗冲击层。外部焊盘132通过辅助铜互连125和通孔栓塞140连接至第一下层铜互连212和第二下层铜互连222。
在内部焊盘134的下面形成第二上层铜层120和第一上层铜层110,作为抗冲击层。内部焊盘134连接至第二上层铜互连122,其构成辅助铜互连。
也可以在内部焊盘134的下面提供第二下层铜层220和第一下层铜层210。在这种情况下,提供第二下层铜层220用于预防相邻第二下层铜互连222之间的短路。第一下层铜层210具有相同的结构。
在本实施例的半导体器件中,与第二实施例相同,即使在检测和键合时由于对键合焊盘的冲击而导致在键合焊盘中发生断裂而导致不能在第二上层铜层120和键合焊盘之间获得足够的导电性时,通过辅助铜互连125,也能够为外部焊盘132和内部焊盘134保证键合焊盘和内部电路之间的导电。
第四实施例
在上述的每个实施例中,可以使用作为第三介电膜的SiOC膜,第三介电膜包含其介电常数相对低于第一材料的材料,以代替作为下层铜层的层间介电膜的二氧化硅(SiO2)膜。现在将对在如图3所示的半导体器件中应用这种类型的结构的示例进行说明。
图5是个剖面结构图,示出了作为本发明的第四实施例的半导体器件的结构。在本实施例的半导体器件中,上层铜层和下层铜层的铜面积比基本相等。上层铜层和上层铜层的上面部位如图2B所示。
如图5所示,下层铜层由四个层组成:第一下层铜层410、第二下层铜层412、第三下层铜层414和第四下层铜层416。这四个层由与如图2B所示的第一上层铜层110的虚拟图形类似的图形所构成。
在第一下层铜层410中插入叠层介电膜310,在第二下层铜层412中插入叠层介电膜314,在第三下层铜层414中插入叠层介电膜318,在第四下层铜层416中插入叠层介电膜322。叠层介电膜310、314、318和322都是由L-Ox膜和二氧化硅(SiO2)膜组成。
在第一下层铜层410和第二下层铜层412之间插入SiOC膜312,在第二下层铜层412和第三下层铜层414之间插入SiOC膜316,以及在第三下层铜层414和第四下层铜层416之间插入SiOC膜320。SiOC膜312、316和320都是层间介电膜。
根据本实施例的半导体器件,每个上层铜层和下层铜层的铜面积比基本相等,且构成上层铜层和下层铜层的每个铜层的铜面积比也基本相等。这种结构能够实现更加均匀地分布冲击并且更大地改善抗冲击能力。
此外,由于SiOC膜312、316和320都是低k膜,当在与四个铜层中的至少两个铜层相同的水平上形成互连层时,互连层之间的电容能够被降低,其中,这四个铜层是第一下层铜层410、第二下层铜层412、第三下层铜层414和第四下层铜层416。
虽然在本实施例中叠层介电膜310、314、318和322都是由L-Ox膜和二氧化硅膜组成,这些膜也可以由SiOC膜构成。
接下来对键合后的键合引线的拉伸强度的研究结果进行说明,即引线拉伸测试的结果,这些结果是把先前描述的现有技术的半导体器件与具有上述第一至第四实施例的结构的半导体器件中的每一种进行比较而得出的结果。
在引线拉伸测试中,键合引线被向上拉伸,如果引线断裂且诸如金或焊的球或键合焊盘在小于4gf的力的作用下剥落,则认为连接有缺陷。在如图1所示的现有技术的半导体器件中,当层间介电膜750是二氧化硅(SiO2)膜时,缺陷比是10%,且当层间介电膜750是SiOC膜时,缺陷比是20%。相反,对于所有第一至第四实施例,缺陷比是0%。
上述第一至第四实施例的结构以及制造方法只是本发明的示例,且在不背离本发明的要旨的范围内,可以适当地修改本发明。例如,上层铜层100和下层铜层200可以由非两个层或四个层的多个层构成。当上层铜层是多个层时,即上层铜层的层数是n,位于结构中的最顶层的第n铜层(n是等于或大于2的自然数)优选地根据改善抗冲击能力的观点而被采用,这种观点是至少第n铜层和通孔栓塞被嵌入由第一材料所组成的介电膜中。
此外,每个上层铜层100和下层铜层200也可以都是单层。在这种情况中,上层铜层100和下层铜层200中的任何一层也可以作为电路互连层。
当上层铜层100和下层铜层200是虚拟层时,这些层的虚拟图形并不限定于如图2B和图2C中所示的形状,且可以采用使得铜的表面密度大致均匀的其它图形。
此外,虽然通过双大马士革方法形成通孔栓塞140和第二上层铜层120,也可以采用单大马士革方法(也简称为“大马士革方法”)。当使用大马士革方法时,通孔栓塞140和第二上层铜层120被分开形成。
进而,虽然把二氧化硅(SiO2)膜作为带有第一材料的介电膜,也可以使用其它介电膜。
当带有第一材料的介电膜是二氧化硅膜时,则对带有第二材料的介电膜是L-Ox膜以及带有第三材料的介电膜是SiOC膜的情况进行了描述,但是可以使用其它介电膜作为带有第二和第三材料的介电膜。例如,带有第二和第三材料的介电膜可以是包含至少一种低k膜的膜,低k膜例如有:L-Ox膜、SiOC膜、碳化硅(SiC)膜、SiOF膜、多孔二氧化硅(SiO2)膜和多孔SiOC膜。
虽然以SiCN膜作为蚀刻限位膜和防铜扩散膜,但是也可以使用SiC膜或SiN膜。SiON膜也可以被用作蚀刻限位膜。当从在此所推荐的膜中选择蚀刻限位膜和防铜扩散膜时,可以通过下述的方式来选择材料:比较例如介电常数和蚀刻选择性,然后选择有利于图形处理而且是能够降低互连之间的电容的材料,其中,蚀刻选择性是蚀刻限位膜或防铜扩散膜和将被蚀刻的膜之间的蚀刻速率的比例。
可以提供包含比二氧化硅膜软的低k膜的膜,例如L-Ox膜或SiOC膜,以替代带有第一材料的介电膜,例如插在第二上层铜层120中的二氧化硅(SiO2)膜44。同样在这种情况中,键合时的抗冲击能力能够得到被改善至高于现有技术的半导体器件。
此外,可以使用氮化钽(TaN)膜,作为位于键合焊盘130下面的阻挡金属,而不是使用氮化钛(TiN)膜。在任何一种情况中,都能够预防铝和铜的扩散。
进而,构成上层铜层100和下层铜层200的每层铜层以及通孔栓塞可以是包含少量诸如硅和铝的其它组分的材料。
根据上述的本发明,在键合焊盘的下面形成其弹性(弹性是可以回弹从外部施加的力的属性)比氧化物膜高的铜层,它们中间插有阻挡金属,从而获得了能够排斥在检测和键合时由探针施加的力以及阻止冲击被传递到键合焊盘下面的结构。因而,抗冲击能力得到改善,且当探针被放在键合焊盘上面时对焊盘的损坏能够得到预防。
此外,在键合焊盘下面提供铜层使得超声波能够被充分地传递至金引线和键合焊盘,而没有被诸如L-Ox膜的低k膜所吸收,其中,超声波用于在键合时实现金引线和键合焊盘之间的共熔键合。因而,金引线和键合焊盘的紧密粘合得到加强并且引线拉伸强度得到提高。
最后,由于键合焊盘部位的实际金属膜厚度是键合焊盘下面的铝和铜层的总膜厚度,从而可以获得具有较大的对抗检测和键合的硬度的器件,因而,能够降低施加到底层L-Ox膜的邻近处的负载并且能够防止在层间介电膜中发生断裂。
虽然已使用了具体术语对本发明的优选实施例进行描述,但是这种描述只是作为示例性的,且应当理解,在不脱离所附权利要求书的精神或范围的情况下,可以作出改变和变化。

Claims (40)

1.一种半导体器件,包含:
形成在半导体衬底上的键合焊盘;
形成在所述键合焊盘的下表面上的上层铜层,它们中间夹有阻挡金属;以及
下层铜层,其形成地比所述上层铜层更靠近所述半导体衬底;
其中,所述键合焊盘下面的所述下层铜层的铜面积比低于所述上层铜层的铜面积比,
其中,在上层铜层和下层铜层之间插入比低k膜硬的介电SiO2膜。
2.如权利要求1所述的半导体器件,其中,所述上层铜层的铜面积比大于在所述半导体衬底上形成为电路互连的其它铜层的铜面积比。
3.如权利要求1所述的半导体器件,其中,所述上层铜层的铜面积比是至少70%。
4.如权利要求1所述的半导体器件,其中,所述键合焊盘和所述上层铜层的平面面积相等。
5.如权利要求1所述的半导体器件,其中所述上层铜层由多个铜层构成。
6.如权利要求5所述的半导体器件,其中,所述上层铜层中的每个铜层的铜面积比相同。
7.如权利要求5所述的半导体器件,进一步包含:
位于所述上层铜层中的每个铜层之间的层间介电膜;以及
由铜组成的通孔栓塞,其嵌入所述层间介电膜中;
其中,所述上层铜层中的每个铜层通过所述通孔栓塞连接。
8.如权利要求7所述的半导体器件,其中,位于所述上层铜层的最上面的铜层的铜层图形和连接至铜层图形的所述通孔栓塞被嵌入由第一材料所组成的介电膜中。
9.如权利要求1所述的半导体器件,其中,所述下层铜层的铜面积比至少为15%且不大于95%。
10.如权利要求1所述的半导体器件,其中所述下层铜层由多个铜层构成。
11.如权利要求10所述的半导体器件,其中,所述下层铜层中的每个铜层的铜面积比相等。
12.如权利要求10所述的半导体器件,其中,在所述下层铜层中的每个铜层之间插入由第一材料所组成的介电膜。
13.如权利要求12所述的半导体器件,其中,所述下层铜层中的每个铜层由嵌入介电膜的铜层图形构成,其中,介电膜由其介电常数相对低于所述第一材料的第二材料组成。
14.如权利要求13所述的半导体器件,其中所述第二材料比所述第一材料软。
15.如权利要求13所述的半导体器件,其中,由所述第二材料所组成的介电膜包含下述膜中的任何一种:SiOC膜、碳化硅膜、SiOF膜、多孔二氧化硅膜、多孔SiOC膜和带有梯型氢化硅氧烷的梯型氧化物膜。
16.如权利要求12所述的半导体器件,其中,在所述下层铜层中的每个铜层之间插入由其介电常数相对低于所述第一材料的第三材料所组成的介电膜。
17.如权利要求16所述的半导体器件,其中所述第三材料比所述第一材料软。
18.如权利要求16所述的半导体器件,其中,由所述第三材料所组成的介电膜包含下述膜中的任何一种:SiOC膜、碳化硅膜、SiOF膜、多孔二氧化硅膜、多孔SiOC膜和带有梯型氢化硅氧烷的梯型氧化物膜。
19.一种制造如权利要求1所述的半导体器件的方法,其中,通过大马士革方法形成所述上层铜层和所述下层铜层。
20.一种制造如权利要求8所述的半导体器件的方法,其中,通过双大马士革方法形成位于所述上层铜层的最上面的铜层的铜层图形和连接至这个铜层图形的通孔栓塞。
21.一种半导体器件,包含:
位于半导体衬底上的键合焊盘;
形成在所述键合焊盘的下表面上的上层铜层,它们中间夹有阻挡金属;以及
下层铜层,其比所述上层铜层更靠近所述半导体衬底;
其中,所述上层铜层与所述下层铜层电绝缘,且所述上层铜层的铜面积比大于在所述半导体衬底上形成为电路互连的其它铜层的铜面积比
其中,在上层铜层和下层铜层之间插入比低k膜硬的介电SiO2膜。
22.如权利要求21所述的半导体器件,其中,所述上层铜层的铜面积比是至少70%。
23.如权利要求21所述的半导体器件,其中,所述键合焊盘和所述上层铜层的平面面积相同。
24.如权利要求21所述的半导体器件,其中所述上层铜层由多个铜层构成。
25.如权利要求24所述的半导体器件,其中,所述上层铜层中的每个铜层的铜面积比相同。
26.如权利要求24所述的半导体器件,进一步包含:
位于所述上层铜层中的每个铜层之间的层间介电膜;以及
由铜组成的通孔栓塞,其嵌入所述层间介电膜中;
其中,所述上层铜层中的每个铜层通过所述通孔栓塞连接。
27.如权利要求26所述的半导体器件,其中,位于所述上层铜层的最上面的铜层的铜层图形和连接至这个铜层图形的所述通孔栓塞被嵌入由第一材料所组成的介电膜中。
28.如权利要求21所述的半导体器件,其中,所述下层铜层的铜面积比至少为15%且不大于95%。
29.如权利要求21所述的半导体器件,其中所述下层铜层由多个铜层构成。
30.如权利要求29所述的半导体器件,其中,所述下层铜层中的每个铜层的铜面积比相等。
31.如权利要求29所述的半导体器件,其中,在所述下层铜层中的每个铜层之间插入由第一材料所组成的介电膜。
32.如权利要求31所述的半导体器件,其中,所述下层铜层中的每个铜层由嵌入介电膜的铜层图形构成,其中,介电膜由其介电常数相对低于所述第一材料的第二材料组成。
33.如权利要求32所述的半导体器件,其中所述第二材料比所述第一材料软。
34.如权利要求32所述的半导体器件,其中,由所述第二材料所组成的介电膜包含下述膜中的任何一种:SiOC膜、碳化硅膜、SiOF膜、多孔二氧化硅膜、多孔SiOC膜和带有梯型氢化硅氧烷的梯型氧化物膜。
35.如权利要求31所述的半导体器件,其中,在所述下层铜层中的每个铜层之间插入由其介电常数相对低于所述第一材料的第三材料所组成的介电膜。
36.如权利要求35所述的半导体器件,其中所述第三材料比所述第一材料软。
37.如权利要求35所述的半导体器件,其中,由所述第三材料所组成的所述介电膜包含下述膜中的任何一种:SiOC膜、碳化硅膜、SiOF膜、多孔二氧化硅膜、多孔SiOC膜和带有梯型氢化硅氧烷的梯型氧化物膜。
38.如权利要求21所述的半导体器件,其中所述阻挡金属包含氮化钛或氮化钽。
39.如权利要求21所述的半导体器件,经一步包含:
位于所述半导体衬底上的内部电路;以及
电连接至所述内部电路的辅助铜互连;
其中,所述辅助铜互连通过通孔电连接至所述键合焊盘中的一部分。
40.一种制造如权利要求27所述的半导体器件的方法,其中,通过双大马士革方法形成位于所述上层铜层的最上面的铜层的铜层图形和连接至这个铜层图形的通孔栓塞。
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US20080290516A1 (en) 2008-11-27
US20080088023A1 (en) 2008-04-17
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