CN1319152C - 利用特定晶体管取向的cmos制造方法 - Google Patents

利用特定晶体管取向的cmos制造方法 Download PDF

Info

Publication number
CN1319152C
CN1319152C CNB018197612A CN01819761A CN1319152C CN 1319152 C CN1319152 C CN 1319152C CN B018197612 A CNB018197612 A CN B018197612A CN 01819761 A CN01819761 A CN 01819761A CN 1319152 C CN1319152 C CN 1319152C
Authority
CN
China
Prior art keywords
semiconductor wafer
described semiconductor
pmos
nmos
stressor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB018197612A
Other languages
English (en)
Other versions
CN1478297A (zh
Inventor
马克·阿姆斯特朗
格哈德·施罗姆
克林·J·库恩
保罗·A·帕茨卡恩
苏尼特·D·佳格
斯科特·E·汤普森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN1478297A publication Critical patent/CN1478297A/zh
Application granted granted Critical
Publication of CN1319152C publication Critical patent/CN1319152C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer

Abstract

互补金属氧化物半导体晶体管形成在硅基片上。基片具有{100}结晶取向。形成在基片上的晶体管的取向，是使电流在晶体管沟道内的流动方向平行于<100>方向。此外，在沟道上还施加纵向拉应力。

Description

利用特定晶体管取向的CMOS制造方法
本发明的技术领域
本发明涉及半导体晶体管，特别是涉及半导体晶体管结构取向，其取向使电流方向平行于特定的结晶方向。
本发明的背景技术
互补金属氧化物半导体(CMOS)集成电路既包括N型器件(NMOS)，也包括P型器件(PMOS)，前者利用电子作为载流子，而后者利用空穴作为载流子。CMOS技术被应用于目前所制造的大部分集成电路中。
CMOS集成电路的一个重要性能指标，是空穴和电子的迁移率。要提高PMOS和NMOS两者的性能，这两种载流子的迁移率都应当尽可能地高。CMOS电路的总体性能同样取决于NMOS和PMOS的性能，从而，取决于空穴和电子的迁移率。
公知的是，在半导体材料上施加应力，例如在半导体材料硅上施加应力，会改变电子和空穴的迁移率，从而，会改变半导体材料上所形成的NMOS和PMOS的性能。迁移率的提高会导致性能的提高。但人们还发现，电子和空穴的迁移率，并不总是对应力做出相同的反应，从而，使加工工艺复杂化。此外，迁移率与应力之间的关系，还取决于结晶半导体材料的表面取向和应力及电流的方向。例如，就沿着{100}平面上的<110>方向的电流而言，纵向拉应力往往会提高电子的迁移率而降低空穴的迁移率。相反，就沿着{100}平面上的<100>方向的电流而言，纵向拉应力往往会提高电子和空穴两者的迁移率。
目前，半导体器件被取向，以使电流沿着{100}硅上的<110>方向来流动。这一点可参看图2，图2为一个半导体晶片201的俯视图。半导体晶片201通常用“{100}硅”来表示，硅晶片是目前所使用的主要半导体晶片。在现有技术中，相对于半导体晶片201来说，NMOS和PMOS晶体管203被这样取向，以使源极与漏极之间的电流方向与<110>方向一致。因此，晶体管203的取向，是如图2中所示的那样。
就这种取向而言，电子和空穴的迁移率，对纵向应力所做出的反应是相反的。也就是说，当沿着电流方向给硅基片施加应力时，或是电子的迁移率提高而空穴的迁移率下降，或是空穴的迁移率提高而电子的迁移率下降。因此，就这种排列而言，CMOS电路的总体性能并没有提高。
为此，要在不降低一种类型器件的载流子的迁移率的情况下，提高另一种类型器件的载流子的迁移率，就必须利用硅材料的选择性加应力技术。从而，可在晶体管203a而不是在晶体管203b的位置上，给晶片201施加应力，反之亦然。这需要昂贵的加工步骤，可能包括形成掩模、淀积或刻蚀。
附图说明
图1为示意图，表示硅的三种结晶取向；
图2为示意图，表示现有技术的半导体晶片上CMOS器件的取向；
图3为示意图，表示本发明的半导体晶片上CMOS器件的取向；
图4A为曲线图，表示P型{100}硅基片的压力电阻系数与电流方向之间的函数关系；
图4B为曲线图，表示N型{100}硅基片的压力电阻系数与电流方向之间的函数关系；
图5表示一个承受纵向拉应力的晶体管；
图6表示一个承受横向拉应力的晶体管。
详细说明
硅(Si)是目前电子工业最重要的半导体材料。用来制造硅晶片的大多数硅，都是利用单晶硅来制成的。这类硅晶片作为基片，在上面形成CMOS器件。这类硅晶片也被称之为半导体基片或半导体晶片。
在结晶硅中，组成这种固体材料的原子，是周期性地排列。如果这种周期性排列贯穿在整个固体材料中，这种材料就被定义为是由单晶硅所构成。如果这种固体材料是由无数个单晶区域所构成，这种固体材料则被称之为多晶材料。
硅，在用于集成电路中时，可以是下述三种形式之一：(1)单晶硅；(2)多结晶硅(多晶硅)；以及(3)非晶硅。正如前面所描述过的那样，硅晶片是被制造成单晶形式。
在晶体中，原子的周期性排列被称之为晶格。晶格也有体积，这个体积代表整个晶格，并被称之为在整个晶体内有规则地重复的晶胞。
硅具有金刚石立方体晶格结构，能够表示为两个贯通的面心立方体晶格。从而，对立方体晶格的简单形象化分析，能够扩展到说明硅晶体的特征。在本说明书的描述中，提到了硅晶体中的各个平面，特别是提到了{100}、{110}和{111}平面。
这些平面说明了硅原子平面相对于主晶轴线的取向。标号{xyz}称之为密勒(Miller)指向，是由硅晶面与主晶轴线交汇(intersects)的点的倒数(reciprocals)来确定。从而，图1示出了硅晶面的3种取向。在图1A中，硅晶面与x轴相交在位置1，而且永远不会与y轴或z轴相交。因此，这种结晶硅的取向是{100}。同样，图1B示出了{110}结晶硅，而图1C示出了{111}结晶硅。{111}和{100}取向是商业上所用的两种主要晶片取向。
需要指出的是，对于立方体晶体的任何一个指定平面，都有5个其他等效平面。因此，构成晶体基本晶胞的立方体六个面，全部被认为是{100}平面。标号{xyz}表示所有六个等效平面。
在本说明书中，还提到了晶体方向，特别是提到了<100>、<110>和<111>方向。这些方向被定义为是垂直于各个平面的法线方向。因此，<100>方向是垂直于{100}平面的方向。标号<xyz>表示所有六个等效方向。
正如前面所描述过的那样，在现有技术中，制造在{100}硅上的大部分MOS晶体管，其栅极的取向使电流方向平行于<110>方向。这一点可参看图2。
根据本发明，如图3所示，MOS晶体管被取向，以使电流实质上沿着<100>方向来流动。图3为利用{100}硅所制成的半导体晶片301的俯视图。形成在半导体晶片301上的晶体管器件表现为晶体管303a和晶体管303b。晶体管303a和晶体管303b的取向，是使晶体管源极与漏极之间的电流实质上沿着半导体晶片301上的<100>方向来流动的取向。显然，晶体管303a和晶体管303b并不是按照比例绘出的，而仅仅是示意性的。
因此，根据本发明的一个实施例，形成在硅晶片上的器件具有一种特定的器件取向，而且采用了一种可在器件沟道区域引起纵向拉应力的生产工艺。这种作用在沟道上的纵向拉应力，将在不降低空穴迁移率的情况下，提高电子的迁移率。
在现有技术中，器件被取向，以使电流实质上沿着{100}硅上的<110>方向来流动。就这种取向而言，电子和空穴的迁移率，对纵向应力所做出的反应是相反的。从而，CMOS电路的总体性能并不会提高。为此，采用了硅材料的选择性加应力技术，以在不降低一种类型器件的载流子的迁移率的情况下，提高另一种类型器件的载流子的迁移率。
通过器件的取向使器件电流沿着<100>方向来流动，能够减轻或逆转由于应力所造成的这种情况：对应于一种类型器件的载流子的迁移率的一定量的提高，另一种类型器件的载流子的迁移率会出现相对下降。这就不需要利用选择性加应力技术来实现令人满意的总体性能增益。本发明的取向使应力能够作为一种工具来提高CMOS电路性能。
硅的压力电阻系数，相对于电流方向而言，是各向异性的。图4A示出了半导体基片p型区域的压力电阻系数与{100}平面上的电流方向之间的函数关系，而图4B示出了半导体基片n型区域的压力电阻系数与{100}平面上的电流方向之间的函数关系。由于公知的是，NMOS晶体管和n型区域不仅性能相似而且压力电阻系数也相似，而且对PMOS晶体管和p型区域来说，也是如此。从而，图4A和图4B适用于NMOS和PMOS晶体管。
在施加应力时，压力电阻系数的变化，与不同方向上电阻的变化有关。正值表示对应于应力，电阻提高。电阻的变化是与迁移率的变化成反比，而迁移率又是与晶体管的速度成正比。因此，电阻较高会导致晶体管较慢。
纵向拉应力的定义是：在与电流方向相同的方向上，“拉伸”沟道。例如，图5中所示了一个晶体管601，它有一个栅极603、一个源极605和一个漏极607。当给栅极603施加一个适当电压时，源极605与漏极607之间的电流，沿着箭头609的方向来流动。纵向拉应力，应当是要沿着方向610拉开源极605和漏极607的应力。此外，纵向压应力，应当是要沿着方向612来拉近源极605和漏极607的应力。
横向拉应力的定义是：在垂直于电流的方向上，“拉伸”沟道。例如，图6中示出了一个晶体管701，它有一个栅极703、一个源极705和一个漏极707。当给栅极703施加一个适当电压时，源极705与漏极707之间的电流，沿着箭头709的方向流动。横向拉应力，应当是在垂直于电流方向709的方向711上的应力。
如图4B所示，当将一个纵向拉应力(用实线401表示)施加于一个半导体晶片的n型区域时，压力电阻系数在<100>方向上为最小(约为-100单位)。如图4A所示，当将一个相同的纵向拉应力(用实线403表示)施加于一个半导体晶片的p型区域时，压力电阻系数仅仅比中性条件(0单位)稍高。
因此，根据本发明的一个实施例，晶体管的取向应当使电流在<100>方向上流动，并且在<100>方向上施加纵向拉应力。这将会提高NMOS晶体管的速度，而不会影响PMOS晶体管。这种取向优于现有技术的<110>取向，在现有技术的取向中，在施加这种应力时，PMOS晶体管的性能会下降，从而，要获得总体增益，需要一种麻烦的选择性加应力工艺。
根据本发明的另一个实施例，在施加横向应力(用虚线405和407表示)时，晶体管器件的取向能够使电流在<110>方向上流动。对于PMOS晶体管来说，这给出了一个大约-70的数值，而对于NMOS晶体管来说，这给出一个大约-25的数值。但实际上，这难以实现，原因是晶体管的宽度通常是长度的许多倍。因此，施加在沟道侧面上的力，会在沟道的中部被大大减弱。
在本技术领域，给基片施加纵向拉应力的具体技术是公知的，因此，在本说明书中，不再对此进行详细说明。举例来说，在一个实施例中，使用一种高拉伸的氮化物(nitride)电介质。这种高拉伸的氮化物电介质，在此也被称之为用来施加拉应力的“应力器”结构。此外，在另一个实施例中，“应力器”结构也可以是一种拉伸的浅沟槽隔离(STI)填充物。虽然这两种“应力器”是作为实例给出，但本说明书中所使用的名词“应力器”，是代表任何一种能够引起拉应力的结构。此外，形成电流在<100>方向上流动的取向晶体管，也是较为简单的。例如，相对于现有技术的取向技术(就{100}硅晶片而言)，或是将基底半导体晶片转动45°，或是将制造掩模转动45°，即能够做到这一点。
虽然本说明书展示和说明了本发明的具体实施例及应用，但应当知道，本发明并不仅仅局限于在此所公开的具体结构和部件。对于本领域的普通技术人员来说，在不偏离本发明精神和范围的情况下，对本发明所公开的方法和系统的布置、运用及具体细节进行各种改进、变化和变动，是显而易见的。
由于根据上述详细说明能够进行各种改进。因此，不应当把在附属权利要求中所使用的名词，认作为是将本发明局限于在说明书和权利要求中所描述的具体实施例。相反，本发明的范围完全根据权利要求的解释原则由附属权利要求来确定。

Claims (22)

1.一种集成电路，包括：
NMOS器件，形成在半导体基片上；
PMOS器件，形成在所述半导体基片上，其中，所述NMOS器件和所述PMOS器件被取向，以使电流沿着所述半导体基片上的<100>方向流动，其中所述半导体基片的至少一部分处在由高拉伸的氮化物电介质所引起的拉应力下。
2.根据权利要求1所述的集成电路，其中，所述半导体基片是用{100}硅制成的。
3.根据权利要求1所述的集成电路，其中，所述拉应力为纵向拉应力。
4.根据权利要求1所述的集成电路，其中，所述NMOS器件和PMOS器件为晶体管。
5.一种装置，包括：
用{100}硅所制成的半导体基片；
PMOS晶体管，形成在所述半导体基片上，所述PMOS晶体管有用来输送电流的PMOS沟道，而且所述PMOS晶体管被取向以使电流在<100>方向上流动；
NMOS晶体管，形成在所述半导体基片上，所述NMOS晶体管有用来输送电流的NMOS沟道，而且所述NMOS晶体管被取向以使电流在<100>方向上流动；以及
应力器，它在所述NMOS沟道或所述PMOS沟道上引起纵向拉应力。
6.根据权利要求5所述的集成电路，其中，所述应力器为高拉伸的氮化物电介质或拉伸的浅沟槽隔离填充物。
7.一种方法，包括：
在半导体晶片上形成NMOS器件和PMOS器件，所述NMOS器件和所述PMOS器件所具有的取向将使得电流沿着所述半导体晶片的<100>方向流动；以及
将纵向拉应力引入到所述半导体晶片的至少一部分中。
8.如权利要求7所述的方法，其中所述在所述半导体晶片上形成所述NMOS器件和PMOS器件的步骤包括将所述半导体晶片自所述半导体晶片的<110>方向转动45度。
9.如权利要求7所述的方法，其中所述在所述半导体晶片上形成所述NMOS器件和PMOS器件的步骤包括将所述制造掩模自所述半导体晶片的<110>方向转动45度。
10.如权利要求7所述的方法，其中所述将所述纵向拉应力引入到所述半导体晶片中的步骤包括沿着所述半导体晶片的所述<100>方向施加高拉伸的氮化物电介质。
11.如权利要求7所述的方法，其中所述将所述纵向拉应力引入到所述半导体晶片中的步骤包括沿着所述半导体晶片的所述<100>方向施加拉伸的浅沟槽隔离填充物。
12.一种方法，包括：
在半导体晶片上形成NMOS器件和PMOS器件，所述NMOS器件和所述PMOS器件所具有的取向将使得电流沿着所述半导体晶片的<110>方向流动；以及
将横向拉应力引入到所述半导体晶片的至少一部分中。
13.如权利要求12所述的方法，其中所述将所述横向拉应力引入所述半导体晶片的步骤包括在垂直于所述半导体晶片的所述<110>方向的方向上将所述横向拉应力引入到所述半导体晶片中。
14.如权利要求12所述的方法，其中所述将横向拉应力引入所述半导体晶片的步骤包括在垂直于所述电流将流动的方向的方向上将所述横向拉应力引入到所述半导体晶片中。
15.一种装置，包括：
在半导体晶片上形成的NMOS器件和PMOS器件，所述NMOS器件和所述PMOS器件所具有的取向将使得电流沿着所述半导体晶片的<100>方向流动；以及
应力器，所述应力器被施加到所述半导体晶片的至少一部分上，以将纵向拉应力引入所述半导体晶片中。
16.如权利要求15所述的装置，其中所述应力器包括高拉伸的氮化物电介质。
17.如权利要求15所述的装置，其中所述应力器包括拉伸的浅沟槽隔离填充物。
18.如权利要求15所述的装置，其中所述NMOS器件或者所述PMOS器件中的至少一个包括沟道区域，并且其中所述应力器被施加在所述沟道区域中。
19.一种装置，包括：
在半导体晶片上形成的NMOS器件和PMOS器件，所述NMOS器件和所述PMOS器件所具有的取向将使得电流沿着所述半导体晶片的<110>方向流动；以及
应力器，所述应力器被施加到所述半导体晶片的至少一部分上，以将横向拉应力引入所述半导体晶片中。
20.如权利要求19所述的装置，其中所述应力器包括高拉伸的氮化物电介质。
21.如权利要求19所述的装置，其中所述应力器包括拉伸的浅沟槽隔离填充物。
22.如权利要求19所述的装置，其中所述NMOS器件或者所述PMOS器件中的至少一个包括沟道区域，并且其中所述应力器被施加在所述沟道区域中。
CNB018197612A 2000-11-29 2001-11-06 利用特定晶体管取向的cmos制造方法 Expired - Fee Related CN1319152C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/727,296 2000-11-29
US09/727,296 US7312485B2 (en) 2000-11-29 2000-11-29 CMOS fabrication process utilizing special transistor orientation

Publications (2)

Publication Number Publication Date
CN1478297A CN1478297A (zh) 2004-02-25
CN1319152C true CN1319152C (zh) 2007-05-30

Family

ID=24922102

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB018197612A Expired - Fee Related CN1319152C (zh) 2000-11-29 2001-11-06 利用特定晶体管取向的cmos制造方法

Country Status (6)

Country Link
US (1) US7312485B2 (zh)
EP (1) EP1340253A2 (zh)
CN (1) CN1319152C (zh)
AU (1) AU2002219862A1 (zh)
TW (1) TW523818B (zh)
WO (1) WO2002045156A2 (zh)

Families Citing this family (133)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7227176B2 (en) * 1998-04-10 2007-06-05 Massachusetts Institute Of Technology Etch stop layer system
US6830976B2 (en) 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US7301180B2 (en) * 2001-06-18 2007-11-27 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
WO2003015142A2 (en) * 2001-08-06 2003-02-20 Massachusetts Institute Of Technology Formation of planar strained layers
US6974735B2 (en) 2001-08-09 2005-12-13 Amberwave Systems Corporation Dual layer Semiconductor Devices
US7138649B2 (en) * 2001-08-09 2006-11-21 Amberwave Systems Corporation Dual-channel CMOS transistors with differentially strained channels
WO2003017336A2 (en) * 2001-08-13 2003-02-27 Amberwave Systems Corporation Dram trench capacitor and method of making the same
AU2002349881A1 (en) * 2001-09-21 2003-04-01 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
WO2003028106A2 (en) 2001-09-24 2003-04-03 Amberwave Systems Corporation Rf circuits including transistors having strained material layers
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US20030227057A1 (en) 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US7138310B2 (en) * 2002-06-07 2006-11-21 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
WO2003105206A1 (en) 2002-06-10 2003-12-18 Amberwave Systems Corporation Growing source and drain elements by selecive epitaxy
US6982474B2 (en) 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
US7388259B2 (en) * 2002-11-25 2008-06-17 International Business Machines Corporation Strained finFET CMOS device structures
US20040154083A1 (en) * 2002-12-23 2004-08-12 Mcvicker Henry J. Sports pad closure system with integrally molded hooks
EP1602125B1 (en) * 2003-03-07 2019-06-26 Taiwan Semiconductor Manufacturing Company, Ltd. Shallow trench isolation process
US6870179B2 (en) 2003-03-31 2005-03-22 Intel Corporation Increasing stress-enhanced drive current in a MOS transistor
US7329923B2 (en) 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US7148559B2 (en) * 2003-06-20 2006-12-12 International Business Machines Corporation Substrate engineering for optimum CMOS device performance
US6911383B2 (en) * 2003-06-26 2005-06-28 International Business Machines Corporation Hybrid planar and finFET CMOS devices
US7279746B2 (en) * 2003-06-30 2007-10-09 International Business Machines Corporation High performance CMOS device structures and method of manufacture
US6891192B2 (en) * 2003-08-04 2005-05-10 International Business Machines Corporation Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions
US7410846B2 (en) * 2003-09-09 2008-08-12 International Business Machines Corporation Method for reduced N+ diffusion in strained Si on SiGe substrate
US6887751B2 (en) 2003-09-12 2005-05-03 International Business Machines Corporation MOSFET performance improvement using deformation in SOI structure
US7170126B2 (en) 2003-09-16 2007-01-30 International Business Machines Corporation Structure of vertical strained silicon devices
US6917093B2 (en) * 2003-09-19 2005-07-12 Texas Instruments Incorporated Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits
US7144767B2 (en) * 2003-09-23 2006-12-05 International Business Machines Corporation NFETs using gate induced stress modulation
US6872641B1 (en) * 2003-09-23 2005-03-29 International Business Machines Corporation Strained silicon on relaxed sige film with uniform misfit dislocation density
US7029980B2 (en) 2003-09-25 2006-04-18 Freescale Semiconductor Inc. Method of manufacturing SOI template layer
US7119403B2 (en) * 2003-10-16 2006-10-10 International Business Machines Corporation High performance strained CMOS devices
US7303949B2 (en) 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
US7037770B2 (en) * 2003-10-20 2006-05-02 International Business Machines Corporation Method of manufacturing strained dislocation-free channels for CMOS
US7319258B2 (en) * 2003-10-31 2008-01-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip with<100>-oriented transistors
US7129126B2 (en) * 2003-11-05 2006-10-31 International Business Machines Corporation Method and structure for forming strained Si for CMOS devices
US7015082B2 (en) 2003-11-06 2006-03-21 International Business Machines Corporation High mobility CMOS circuits
US7029964B2 (en) 2003-11-13 2006-04-18 International Business Machines Corporation Method of manufacturing a strained silicon on a SiGe on SOI substrate
US7122849B2 (en) 2003-11-14 2006-10-17 International Business Machines Corporation Stressed semiconductor device structures having granular semiconductor material
US7247534B2 (en) 2003-11-19 2007-07-24 International Business Machines Corporation Silicon device on Si:C-OI and SGOI and method of manufacture
TWI228293B (en) * 2003-12-02 2005-02-21 Univ Nat Taiwan A CMOS utilizing a special layout direction
US7198995B2 (en) * 2003-12-12 2007-04-03 International Business Machines Corporation Strained finFETs and method of manufacture
WO2005064680A1 (ja) * 2003-12-25 2005-07-14 Fujitsu Limited 半導体装置および半導体集積回路装置
US7482214B2 (en) 2003-12-30 2009-01-27 Texas Instruments Incorporated Transistor design and layout for performance improvement with strain
US7247912B2 (en) * 2004-01-05 2007-07-24 International Business Machines Corporation Structures and methods for making strained MOSFETs
US7381609B2 (en) * 2004-01-16 2008-06-03 International Business Machines Corporation Method and structure for controlling stress in a transistor channel
US7202132B2 (en) * 2004-01-16 2007-04-10 International Business Machines Corporation Protecting silicon germanium sidewall with silicon for strained silicon/silicon germanium MOSFETs
US7118999B2 (en) * 2004-01-16 2006-10-10 International Business Machines Corporation Method and apparatus to increase strain effect in a transistor channel
KR100641365B1 (ko) * 2005-09-12 2006-11-01 삼성전자주식회사 최적화된 채널 면 방위를 갖는 모스 트랜지스터들, 이를구비하는 반도체 소자들 및 그 제조방법들
US7205210B2 (en) 2004-02-17 2007-04-17 Freescale Semiconductor, Inc. Semiconductor structure having strained semiconductor and method therefor
US7923782B2 (en) 2004-02-27 2011-04-12 International Business Machines Corporation Hybrid SOI/bulk semiconductor transistors
US7205206B2 (en) 2004-03-03 2007-04-17 International Business Machines Corporation Method of fabricating mobility enhanced CMOS devices
US7001844B2 (en) * 2004-04-30 2006-02-21 International Business Machines Corporation Material for contact etch layer to enhance device performance
US7208803B2 (en) * 2004-05-05 2007-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a raised source/drain and a semiconductor device employing the same
US7223994B2 (en) * 2004-06-03 2007-05-29 International Business Machines Corporation Strained Si on multiple materials for bulk or SOI substrates
US7037794B2 (en) 2004-06-09 2006-05-02 International Business Machines Corporation Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain
TWI463526B (zh) * 2004-06-24 2014-12-01 Ibm 改良具應力矽之ｃｍｏｓ元件的方法及以該方法製備而成的元件
US7288443B2 (en) * 2004-06-29 2007-10-30 International Business Machines Corporation Structures and methods for manufacturing p-type MOSFET with graded embedded silicon-germanium source-drain and/or extension
US6991998B2 (en) 2004-07-02 2006-01-31 International Business Machines Corporation Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
US7384829B2 (en) * 2004-07-23 2008-06-10 International Business Machines Corporation Patterned strained semiconductor substrate and device
US7241647B2 (en) 2004-08-17 2007-07-10 Freescale Semiconductor, Inc. Graded semiconductor layer
JP5017771B2 (ja) * 2004-08-20 2012-09-05 日本電気株式会社 相補型電界効果型トランジスタ、および電界効果型トランジスタの製造方法
US7288448B2 (en) 2004-08-24 2007-10-30 Orlowski Marius K Method and apparatus for mobility enhancement in a semiconductor device
US7166897B2 (en) 2004-08-24 2007-01-23 Freescale Semiconductor, Inc. Method and apparatus for performance enhancement in an asymmetrical semiconductor device
US7161199B2 (en) 2004-08-24 2007-01-09 Freescale Semiconductor, Inc. Transistor structure with stress modification and capacitive reduction feature in a width direction and method thereof
US7268399B2 (en) * 2004-08-31 2007-09-11 Texas Instruments Incorporated Enhanced PMOS via transverse stress
US7018901B1 (en) 2004-09-29 2006-03-28 Freescale Semiconductor, Inc. Method for forming a semiconductor device having a strained channel and a heterojunction source/drain
US7067868B2 (en) 2004-09-29 2006-06-27 Freescale Semiconductor, Inc. Double gate device having a heterojunction source/drain and strained channel
US7160769B2 (en) 2004-10-20 2007-01-09 Freescale Semiconductor, Inc. Channel orientation to enhance transistor performance
US7226833B2 (en) 2004-10-29 2007-06-05 Freescale Semiconductor, Inc. Semiconductor device structure and method therefor
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
JP2006165335A (ja) * 2004-12-08 2006-06-22 Toshiba Corp 半導体装置
US7348635B2 (en) * 2004-12-10 2008-03-25 International Business Machines Corporation Device having enhanced stress state and related methods
US7173312B2 (en) * 2004-12-15 2007-02-06 International Business Machines Corporation Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification
US7405436B2 (en) 2005-01-05 2008-07-29 International Business Machines Corporation Stressed field effect transistors on hybrid orientation substrate
US7274084B2 (en) * 2005-01-12 2007-09-25 International Business Machines Corporation Enhanced PFET using shear stress
US20060160317A1 (en) * 2005-01-18 2006-07-20 International Business Machines Corporation Structure and method to enhance stress in a channel of cmos devices using a thin gate
US7220626B2 (en) 2005-01-28 2007-05-22 International Business Machines Corporation Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels
US7256081B2 (en) * 2005-02-01 2007-08-14 International Business Machines Corporation Structure and method to induce strain in a semiconductor device channel with stressed film under the gate
US7224033B2 (en) 2005-02-15 2007-05-29 International Business Machines Corporation Structure and method for manufacturing strained FINFET
US7282402B2 (en) 2005-03-30 2007-10-16 Freescale Semiconductor, Inc. Method of making a dual strained channel semiconductor device
US7545004B2 (en) * 2005-04-12 2009-06-09 International Business Machines Corporation Method and structure for forming strained devices
JP2006351694A (ja) * 2005-06-14 2006-12-28 Fujitsu Ltd 半導体装置およびその製造方法
US7649230B2 (en) * 2005-06-17 2010-01-19 The Regents Of The University Of California Complementary field-effect transistors having enhanced performance with a single capping layer
US7323389B2 (en) 2005-07-27 2008-01-29 Freescale Semiconductor, Inc. Method of forming a FINFET structure
US7544577B2 (en) * 2005-08-26 2009-06-09 International Business Machines Corporation Mobility enhancement in SiGe heterojunction bipolar transistors
US7202513B1 (en) * 2005-09-29 2007-04-10 International Business Machines Corporation Stress engineering using dual pad nitride with selective SOI device architecture
US7655511B2 (en) 2005-11-03 2010-02-02 International Business Machines Corporation Gate electrode stress control for finFET performance enhancement
US7785950B2 (en) * 2005-11-10 2010-08-31 International Business Machines Corporation Dual stress memory technique method and related structure
US7709317B2 (en) 2005-11-14 2010-05-04 International Business Machines Corporation Method to increase strain enhancement with spacerless FET and dual liner process
US7348638B2 (en) * 2005-11-14 2008-03-25 International Business Machines Corporation Rotational shear stress for charge carrier mobility modification
US7564081B2 (en) 2005-11-30 2009-07-21 International Business Machines Corporation finFET structure with multiply stressed gate electrode
US7863197B2 (en) 2006-01-09 2011-01-04 International Business Machines Corporation Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification
US7776695B2 (en) * 2006-01-09 2010-08-17 International Business Machines Corporation Semiconductor device structure having low and high performance devices of same conductive type on same substrate
US7635620B2 (en) 2006-01-10 2009-12-22 International Business Machines Corporation Semiconductor device structure having enhanced performance FET device
US20070158743A1 (en) * 2006-01-11 2007-07-12 International Business Machines Corporation Thin silicon single diffusion field effect transistor for enhanced drive performance with stress film liners
US7691698B2 (en) 2006-02-21 2010-04-06 International Business Machines Corporation Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain
US7573104B2 (en) * 2006-03-06 2009-08-11 International Business Machines Corporation CMOS device on hybrid orientation substrate comprising equal mobility for perpendicular devices of each type
DE102006019835B4 (de) * 2006-04-28 2011-05-12 Advanced Micro Devices, Inc., Sunnyvale Transistor mit einem Kanal mit Zugverformung, der entlang einer kristallographischen Orientierung mit erhöhter Ladungsträgerbeweglichkeit orientiert ist
US7521307B2 (en) * 2006-04-28 2009-04-21 International Business Machines Corporation CMOS structures and methods using self-aligned dual stressed layers
WO2007130240A1 (en) * 2006-04-28 2007-11-15 Advanced Micro Devices , Inc. A transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility
US7608489B2 (en) * 2006-04-28 2009-10-27 International Business Machines Corporation High performance stress-enhance MOSFET and method of manufacture
US7615418B2 (en) * 2006-04-28 2009-11-10 International Business Machines Corporation High performance stress-enhance MOSFET and method of manufacture
US8853746B2 (en) 2006-06-29 2014-10-07 International Business Machines Corporation CMOS devices with stressed channel regions, and methods for fabricating the same
US7790540B2 (en) 2006-08-25 2010-09-07 International Business Machines Corporation Structure and method to use low k stress liner to reduce parasitic capacitance
US7462522B2 (en) * 2006-08-30 2008-12-09 International Business Machines Corporation Method and structure for improving device performance variation in dual stress liner technology
US8754446B2 (en) * 2006-08-30 2014-06-17 International Business Machines Corporation Semiconductor structure having undercut-gate-oxide gate stack enclosed by protective barrier material
JP2008103607A (ja) * 2006-10-20 2008-05-01 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US7897493B2 (en) * 2006-12-08 2011-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Inducement of strain in a semiconductor layer
JP5010310B2 (ja) * 2007-02-28 2012-08-29 株式会社東芝 半導体装置の製造方法および半導体装置
US7795605B2 (en) * 2007-06-29 2010-09-14 International Business Machines Corporation Phase change material based temperature sensor
US7816198B2 (en) * 2007-07-10 2010-10-19 Infineon Technologies Ag Semiconductor device and method for manufacturing the same
US7615435B2 (en) * 2007-07-31 2009-11-10 International Business Machines Corporation Semiconductor device and method of manufacture
US7525162B2 (en) * 2007-09-06 2009-04-28 International Business Machines Corporation Orientation-optimized PFETS in CMOS devices employing dual stress liners
JP2009076731A (ja) * 2007-09-21 2009-04-09 Renesas Technology Corp 半導体装置およびその製造方法
US8115254B2 (en) 2007-09-25 2012-02-14 International Business Machines Corporation Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same
US8492846B2 (en) 2007-11-15 2013-07-23 International Business Machines Corporation Stress-generating shallow trench isolation structure having dual composition
US8062951B2 (en) * 2007-12-10 2011-11-22 International Business Machines Corporation Method to increase effective MOSFET width
US8122394B2 (en) * 2008-09-17 2012-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Performance-aware logic operations for generating masks
US20090261346A1 (en) * 2008-04-16 2009-10-22 Ding-Yuan Chen Integrating CMOS and Optical Devices on a Same Chip
US9723122B2 (en) 2009-10-01 2017-08-01 Mc10, Inc. Protective cases with integrated electronics
JP2011103340A (ja) * 2009-11-10 2011-05-26 Elpida Memory Inc 半導体装置、半導体チップ及び半導体装置の製造方法
US8269283B2 (en) 2009-12-21 2012-09-18 Intel Corporation Methods and apparatus to reduce layout based strain variations in non-planar transistor structures
US8598006B2 (en) * 2010-03-16 2013-12-03 International Business Machines Corporation Strain preserving ion implantation methods
CN102569086B (zh) * 2010-12-29 2014-10-29 中国科学院微电子研究所 半导体器件及其形成方法
US8772127B2 (en) * 2010-12-29 2014-07-08 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device and method for manufacturing the same
JP2014523633A (ja) 2011-05-27 2014-09-11 エムシー１０ インコーポレイテッド 電子的、光学的、且つ／又は機械的装置及びシステム並びにこれらの装置及びシステムを製造する方法
US9006798B2 (en) * 2013-05-03 2015-04-14 Infineon Technologies Ag Semiconductor device including trench transistor cell array and manufacturing method
FR3028351B1 (fr) * 2014-11-12 2018-01-19 Stmicroelectronics Sa Cellule integree multi-orientations, en particulier cellule d'entree/sortie d'un circuit integre
CN109449121B (zh) * 2018-10-26 2022-04-19 中国科学院微电子研究所 半导体器件及其制造方法及包括该器件的电子设备
US20210074716A1 (en) * 2019-09-09 2021-03-11 Samsung Electronics Co., Ltd. Three-dimensional semiconductor devices
KR20210030533A (ko) * 2019-09-09 2021-03-18 삼성전자주식회사 3차원 반도체 장치
US11430747B2 (en) * 2020-12-31 2022-08-30 Texas Instruments Incorporated Strain-induced shift mitigation in semiconductor packages
DE102021206134A1 (de) * 2021-06-16 2022-12-22 Robert Bosch Gesellschaft mit beschränkter Haftung Stress- und/oder Dehnungsmesszelle für ein Stress- und/oder Dehnungsmesssystem

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5171703A (en) * 1991-08-23 1992-12-15 Intel Corporation Device and substrate orientation for defect reduction and transistor length and width increase
CN1129358A (zh) * 1994-09-26 1996-08-21 摩托罗拉公司 迁移率提高了的mosfet器件及其制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE606275A (zh) 1960-07-18
FR1522471A (fr) 1967-03-15 1968-04-26 Csf Dispositif de mesure de contrainte
US3965453A (en) * 1974-12-27 1976-06-22 Bell Telephone Laboratories, Incorporated Piezoresistor effects in semiconductor resistors
JPH01162362A (ja) 1987-12-18 1989-06-26 Fujitsu Ltd 半導体装置の製造方法
US5633202A (en) 1994-09-30 1997-05-27 Intel Corporation High tensile nitride layer
JPH11233769A (ja) * 1998-02-12 1999-08-27 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
US5981325A (en) * 1999-04-26 1999-11-09 United Semiconductor Corp. Method for manufacturing CMOS

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5171703A (en) * 1991-08-23 1992-12-15 Intel Corporation Device and substrate orientation for defect reduction and transistor length and width increase
CN1129358A (zh) * 1994-09-26 1996-08-21 摩托罗拉公司 迁移率提高了的mosfet器件及其制造方法

Also Published As

Publication number Publication date
US20020063292A1 (en) 2002-05-30
WO2002045156A3 (en) 2003-01-23
AU2002219862A1 (en) 2002-06-11
US7312485B2 (en) 2007-12-25
TW523818B (en) 2003-03-11
WO2002045156A2 (en) 2002-06-06
EP1340253A2 (en) 2003-09-03
CN1478297A (zh) 2004-02-25

Similar Documents

Publication Publication Date Title
CN1319152C (zh) 利用特定晶体管取向的cmos制造方法
US7888710B2 (en) CMOS fabrication process utilizing special transistor orientation
US6974733B2 (en) Double-gate transistor with enhanced carrier mobility
US7354815B2 (en) Method for fabricating semiconductor devices using strained silicon bearing material
CN101233605B (zh) 用于制造受应力的mos器件的方法
US6982433B2 (en) Gate-induced strain for MOS performance improvement
Liow et al. Strained n-channel FinFETs with 25 nm gate length and silicon-carbon source/drain regions for performance enhancement
KR940004804A (ko) 반도체 집적 회로 장치 및 그 제조 방법
JPH10321733A (ja) 集積ｃｍｏｓ回路装置及びその製造方法
US7534676B2 (en) Method of forming enhanced device via transverse stress
JP2007531294A (ja) 歪みシリコンオンインシュレータ構造を製造する方法およびそれによって形成された歪みシリコンオンインシュレータ構造
JP2008523622A (ja) Ｆｅｒｍｉ−ＦＥＴのひずみシリコンとゲート技術
KR20090038653A (ko) Ｃｍｏｓ 소자 및 그 제조방법
CN102844870A (zh) 匹配器件中的纳米线电路
US7235436B1 (en) Method for doping structures in FinFET devices
CN111668220A (zh) 一种垂直沟道sram集成电路结构
Toh et al. Strain and materials engineering for the I-MOS transistor with an elevated impact-ionization region
CN105742284A (zh) 半导体器件制备方法以及半导体器件
US20060040430A1 (en) System and method for integrating low schottky barrier metal source/drain
Le et al. High-performance poly-Si vertical nanowire thin-film transistor and the inverter demonstration
Thompson et al. Strained Si and the future direction of CMOS
CN102738161B (zh) 一种双多晶双应变混合晶面Si基BiCMOS集成器件及制备方法
CN102723342B (zh) 一种混合晶面垂直沟道应变BiCMOS集成器件及制备方法
JPH0521800A (ja) Ｓｏｉｍｏｓｆｅｔ
WO2023065549A1 (zh) 半导体器件及其制备方法与应用

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070530

Termination date: 20171106