CN1327263A - 半导体器件及其制造方法、层叠型半导体器件和电路基板 - Google Patents
半导体器件及其制造方法、层叠型半导体器件和电路基板 Download PDFInfo
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- CN1327263A CN1327263A CN01122151A CN01122151A CN1327263A CN 1327263 A CN1327263 A CN 1327263A CN 01122151 A CN01122151 A CN 01122151A CN 01122151 A CN01122151 A CN 01122151A CN 1327263 A CN1327263 A CN 1327263A
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Abstract
半导体器件的制造方法包括在第1个面有多个电极2的半导体元件6上形成通孔4的第1工序,以及为了与电极2进行电连接、从通孔4内壁表面到第1个面及与第1个面相向的第2个面上形成导电层8的第2工序,在第2工序中,在第1个面和第2个面配备连接区14,并且在多个电极2之中,至少两个电极2的间距与第1个面及第2个面之中至少任何一个面处的连接区14的间距不同,以此形成上述导电层8。
Description
本发明涉及半导体器件及其制造方法、层叠型半导体器件、电路基板以及电子设备。
近年来开发了将多片半导体芯片层叠起来的半导体器件。其中的多数是将连线和引线键合到半导体芯片的电极上以期实现电连接,但由于布设连线等,小型化是有限度的。
另外,还进行了如下的开发:在半导体芯片上形成通孔,将熔融后的焊料填充到通孔内以期实现电连接。然而,如将焊料填充到细的通孔内就要产生空隙,难以确保电连接的可靠性。
本发明就是解决这些问题的,其目的在于,提供一种半导体器件及其制造方法、层叠型半导体器件、电路基板以及电子设备,能够容易地谋求使层叠的半导体元件相互之间的电连接具有高可靠性,并且能够谋求实现小型化。
(1)涉及本发明的半导体器件的制造方法包括:在第1个面上有多个电极的半导体元件上形成通孔的第1工序,以及
形成与上述电极进行电连接、从上述通孔内壁表面达到上述第1个面上以及与上述第1个面相向的第2个面上的导电层的第2工序。
在上述第2工序中,在上述第1个面及上述第2个面配备连接区,并且在多个电极之中至少两个上述电极的间距与上述第1个面及上述第2个面之中至少任何一个面处的上述连接区的间距不同,以此形成上述导电层。
按照本发明,藉助于在通孔内形成导电层,谋求半导体元件中一方的面与另一方的面的电连接。因此,由于不向通孔内的导电层填充熔融材料,就不会产生空隙等问题,能够确保电连接的高可靠性。
还有,因导电层按指定的形状迂回布线,故能够改变多个连接区的间距。因此,例如在使多个半导体元件层叠起来的情况下,能够提高半导体元件相互之间的连接自由度。
(2)在该半导体器件的制造方法中,
在上述第1工序中,可以预先形成其直径比上述通孔小的小孔,再将上述小孔扩大,形成上述通孔。
因此,可以很容易形成通孔。
(3)在该半导体器件的制造方法中,
可以在形成上述小孔的位置处形成一个凹坑。
由于可借助于该凹坑确认形成通孔的位置,因此该通孔可以在正确的位置处形成。
(4)在该半导体器件的制造方法中,
上述小孔用激光光束形成,可采用湿法刻蚀使上述小孔扩大。
因此,可以很容易形成通孔。再有,由激光光束形成的小孔的内壁表面尽管粗糙,但由于采取湿法刻蚀使之扩大,可以形成光滑内壁表面的通孔。
(5)在该半导体器件的制造方法中,
可以在上述电极处,形成与上述通孔连通的孔。
(6)在该半导体器件的制造方法中,
上述通孔在上述半导体元件的端部一侧形成,
上述连接区可设置在比上述半导体元件的上述通孔更靠近中心一侧。
因此,借助于在半导体元件的中心一侧形成连接区,可以在广大区域内期求改变连接区的间距。
(7)在该半导体器件的制造方法中,
在上述第2工序前,还包括在上述第1个面及上述第2个面中至少任何一个面处形成应力减缓层的工序,
可以在上述第2工序中形成到达上述应力减缓层上的上述导电层。
因此,施加到导电层上的应力可在应力减缓层得到减缓。
(8)在该半导体器件的制造方法中,
通过上述应力减缓层形成多个突起部,
可以在上述第2工序中,形成到达各个上述突起部的上述导电层。
因此,可将该突起部作为凸点使用。
(9)在该半导体器件的制造方法,
通过上述应力减缓层形成多个凹陷部,
可以在上述第2工序中,形成到达各个上述凹陷部的上述导电层。
(10)在该半导体器件的制造方法中,
上述应力减缓层可以用树脂形成。
(11)在该半导体器件的制造方法中,
上述连接区可以在上述应力减缓层上形成。
因此,施加到连接区的应力可以在应力减缓层得到减缓。
(12)在该半导体器件的制造方法中,
相邻上述连接区的间距可以比相邻的上述电极的间距宽。
因此,例如在使各半导体元件之间层叠在一起时,在连接区之间可以很容易实现两者的电连接。
(13)在该半导体器件的制造方法中,
还包括在上述连接区上设置外部端子的工序。
(14)在该半导体器件的制造方法中,
在设置上述外部端子的工序中,可以在上述连接区上形成厚层焊锡后,用湿回法形成焊球。
(15)在该半导体器件的制造方法中,
可以在上述连接区上用电镀法或印刷法敷设上述焊锡。
(16)在该半导体器件的制造方法中,
在上述第2工序后,还可以包括至少在上述连接区以外的区域形成保护膜的工序。
(17)在该半导体器件的制造方法中,
在上述第1工序后,在上述第2工序前,还包括在包含上述通孔内壁表面的区域形成绝缘膜的工序。
也可以在上述第2工序中,在上述绝缘膜上形成上述导电层。
因此,在除了电极的部分中,可以防止半导体元件和导电层之间发生短路。
(18)在该半导体器件的制造方法中,
可以在包含上述通孔的内壁表面的区域,涂敷树脂以形成上述绝缘膜。
因此,可不用特殊装置而在短时间并且以低成本形成绝缘膜。
(19)在该半导体器件的制造方法中,
在形成上述绝缘膜的工序中,在上述通孔内埋入敷设树脂,可以在上述第2工序中形成上述导电层以使上述通孔内的上述树脂贯通。
因此,可不用特殊装置而在短时间并且以低成本形成绝缘膜。
(20)在该半导体器件的制造方法中,
上述半导体元件可以是半导体芯片。
(21)在该半导体器件的制造方法中,
上述半导体元件可以是半导体晶片的一部分。
(22)进而包括使得用上述方法制成的半导体器件层叠起来,在上下的半导体器件之间通过上述导电层实现电连接的工序。
三维安装适用于该半导体器件的制造方法。
(23)在该半导体器件的制造方法中,
进而包括将上述半导体晶片切割为单片的工序。
(24)涉及本发明的半导体器件包括:
具有通孔、并且在第1个面有多个电极的半导体元件;
与上述电极进行电连接,并且从上述通孔的内壁表面到上述第1个面以及与上述第1个面相向的第2个面上形成的导电层;以及
配备在上述导电层上、在上述第1个面及上述第2个面中的至少任何一个面按照与多个上述电极之中至少两个上述电极的间距不同的间距形成的多个连接区。
按照本发明,借助于在通孔内形成导电层谋求在半导体元件的一方的面与另一方的面之间实现电连接。因此,由于导电层不是在通孔内填充熔融材料而形成的,因此不产生空隙等问题,可确保电连接的高可靠性。
再有,通过导电层按指定的形状迂回布线,可改变多个连接区的间距。因此,例如在将多个半导体元件层叠在一起的情况下,可提高半导体元件相互之间的连接自由度。
(25)在该半导体器件中,
上述通孔在上述半导体元件的端部一侧形成,
上述连接区可以设置在比上述半导体元件的上述通孔更靠近中心一侧。
因此,通过在半导体元件的中心一侧形成连接区,可以在广大区域内谋求改变连接区的间距。
(26)在该半导体器件中,
进而包括在上述第1个面及上述第2个面中至少任何一个面上所形成的应力减缓层,
可以形成能到达上述应力减缓层上的上述导电层。
因此,施加到导电层的应力可以通过应力减缓层得到减缓。
(27)在该半导体器件中,
通过上述应力减缓层形成多个突起部,
可以形成能到达各个上述突起部的上述导电层。
因此,可将该突起部作为凸点使用。
(28)在该半导体器件中,
通过上述应力减缓层形成多个凹陷部,
可以形成能到达各个上述凹陷部的上述导电层。
(29)在该半导体器件中,
上述应力减缓层可用树脂形成。
(30)在该半导体器件中,
上述连接区可以在上述应力减缓层上形成。
(31)在该半导体器件中,
相邻上述连接区的间距可以比相邻的上述电极的间距宽。
因此,例如在使各半导体元件之间层叠在一起时,在连接区之间
可以很容易实现两者的电连接。
(32)在该半导体器件中,
进而包括在上述连接区设置的外部端子。
(33)在该半导体器件中,
可在除上述连接区以外的区域形成保护膜。
(34)在该半导体器件中,
在包含上述通孔内壁表面的区域形成绝缘膜,
上述导电层可以在上述绝缘膜上形成。
因此,在电极以外的部分中,可以防止半导体元件与导电层之间发生短路。
(35)在该半导体器件中,
上述半导体元件可以是半导体芯片。
(36)在该半导体器件中,
上述半导体元件可以是半导体晶片的一部分。
(37)涉及本发明的层叠型半导体器件是将多个半导体器件层叠起来的,至少最下层的半导体器件是上述半导体器件。
(38)在该层叠型半导体器件中,
可将多个上述半导体器件层叠起来,上下的半导体器件可通过上述导电层实现电连接。
因此,仅仅通过上下层叠就使上下半导体器件相互之间的电连接成为可能,从而可提供有层叠结构的小型半导体器件。
(39)在该层叠型半导体器件中,
使多个上述半导体器件层叠起来,上下的半导体器件通过上述导电层进行电连接,
在层叠起来的一对上述半导体器件上,上述应力减缓层的上述突起部之间可以相向配置。
因此,可将突起部作为凸点使用。再有,通过作为应力减缓层的突起部可使施加于上下半导体芯片之间的应力得到减缓。
(40)在该层叠型半导体器件中,
可将上述半导体器件层叠起来,上下的半导体器件可通过上述导电层实现电连接,
在层叠起来的一对上述半导体器件上,可使一方的半导体元件上的上述突起部楔入另一方半导体元件上的上述凹陷部。
因此,能够确实谋求在连接区之间实现电连接。即,可增大连接区之间的接触面积。
(41)在该层叠型半导体器件中,
最下层的半导体器件可与将上述半导体元件上的上述第1个面层叠起来的另一半导体器件相向配置。
因此,与形成半导体元件上电极的面相反的面由于例如与电路基板相对,因此可抑制半导体器件在安装中或安装后的损伤。
(42)安装有上述半导体器件或上述层叠型半导体器件的电路基板。
(43)具有上述半导体器件或上述层叠型半导体器件的电子设备。
图1是与应用本发明的第1实施例有关的半导体器件的重要部分的放大截面图。
图2是与应用本发明的第1实施例有关的半导体器件的平面图。
图3A~图3C是与应用本发明的第1实施例有关的半导体器件的制造方法的工序图。
图4A~图4C是与应用本发明的第1实施例有关的半导体器件的制造方法的工序图。
图5A~图5C是与应用本发明的第1实施例有关的半导体器件的制造方法的工序图。
图6A~图6C是与应用本发明的第1实施例有关的半导体器件的制造方法的工序图。
图7A~图7C是与应用本发明的第1实施例有关的半导体器件的制造方法的工序图。
图8A和图8B是与应用本发明的第1实施例有关的半导体器件的制造方法的工序图。
图9A~图9C是与应用本发明的第1实施例有关的半导体器件的制造方法的工序图。
图10A~图10C是与应用本发明的第1实施例有关的半导体器件的制造方法的工序图。
图11是与应用本发明的第2实施例有关的半导体器件的示意图。
图12是与应用本发明的第2实施例的变形例有关的半导体器件的示意图。
图13是与应用本发明的第3实施例有关的半导体器件的示意图。
图14是与应用本发明的第4实施例有关的半导体器件的示意图。
图15是与应用本发明的第4实施例的第2例有关的半导体器件的示意图。
图16是与应用本发明的第4实施例的第3例有关的半导体器件的示意图。
图17是安装了与应用本发明的实施例有关的半导体器件的电路基板的示意图。
图18是有与应用本发明的实施例有关的半导体器件的电子设备的示意图。
图19是有与应用本发明的实施例有关的半导体器件的电子设备的示意图。
图1是涉及本发明第1实施例的半导体器件中重要部分的放大截面图。图2是涉及本发明第1实施例的半导体器件的平面图。详细地说,图2是与半导体芯片6的电极2相反面的平面图,一部分导电层8(包括连接区14及布线18)以及阻焊层26均予省略。在下面所示的说明中,我们举半导体芯片为例加以说明,然而本实施例也可适用于半导体晶片。
涉及本实施例的半导体器件1,可按所谓CSP(Chip Scale/SizePackage,芯片尺度/尺寸封装)进行分类。半导体器件1包括有电极2并且形成通孔4的半导体芯片6(半导体元件)以及在包含通孔4内侧(内壁表面)的区域所形成的导电层8。然而,所形成的导电层8可到达半导体芯片6的面上,并且在半导体芯片6的面上有一部分形成布线18。
半导体芯片6的外形通常多为长方体(包含立方体),但本实施例中对此并无限定,例如球形体亦可。半导体芯片6在图中没有示出的由晶体管和存储器等构成的集成电路赖以形成的表面上具有绝缘膜(层间膜)16。绝缘膜16多为半导体芯片6的基本材料硅的氧化膜。
在绝缘膜16上形成电极(焊盘)2,电极2与图中没有示出部分的集成电路进行电连接。电极2多以集成电路布线图形中所使用的金属形成,具体地说,以铝、铝合金或铜之类的金属形成。电极2沿着半导体芯片6的面上至少1个边(多数情况下为2个边或4个边)排列。电极2多在半导体芯片6中形成集成电路一侧的面(有源面)上形成。电极2多在集成电路形成区域(有源区)的外侧形成,但也可在其内侧形成。另外,电极2有在半导体芯片6的面边缘区排列的情形,以及在中心区排列的情形。
如图1所示,通孔4系从半导体芯片6中形成电极2的面(第1个面)贯通半导体芯片6而到达与之相对的面(第2个面)。所形成的通孔4的数目可与电极2的数目相等,也可比电极2的数目多或者少。通孔4最好在半导体芯片6的集成电路形成区域的外侧形成。亦即,通孔4可在半导体芯片6的边缘区形成。再有,如图2所示,如从半导体芯片6的平面看,通孔4可在与电极2重叠的位置上形成。通孔4的形状不加限定,可根据其形成方法自由地形成。例如,如图1所示,通孔4可形成为其中间部分尺寸比开口端部宽。或者,通孔4也可形成为与开口端部同样尺寸并且具有垂直内壁表面。
半导体芯片6通过导电层8谋求有源面(图1中上侧的面)与非有源面(图1中下侧的面)之间的电连接。亦即,所形成的导电层8是从通孔4的内壁表面到达有源面(第1个面)上以及与有源面相对的面(第2个面)上。在电极2上也可介入绝缘膜10形成与通孔4连通的孔12。导电层8与电极2的至少一部分层叠而形成的。在通孔4的内侧,在导电层8下面形成绝缘膜10,阻断与半导体芯片6内部所形成的集成电路的电连接。
如图1及图2所示,所形成的导电层8有一部分在半导体芯片6的面上构成布线18。换言之,导电层8的一部分(布线18)是在半导体芯片6的面上从通孔4延伸的区域形成的。例如,如图2所示,在半导体芯片6的边缘区形成通孔4的场合,布线18比半导体芯片6上的通孔4更接近于在延伸到中心一侧的区域上形成。布线18在半导体芯片6的面上在通孔4的开口端部,与以包围该通孔4的方式所形成的导电层8的一部分连接并从该处延伸而形成。亦即,如图2所示,在半导体芯片6的面上,形成在平面上包围通孔4的导电层8的一部分和从该处延伸出来作为布线18而形成的导电层8的另一部分。通过从通孔4出发按照指定的形状迂回曲折形成布线18(导电层),可改变其间距。亦即,与电极2的电连接区(在图2为外部端子24)的间距比电极2相互之间的间距要宽。另外,借助于这种间距变换,在作为指定面的区域可提供半导体芯片6的电连接区。因此,其优点是与其它部件(半导体芯片或晶片,或电路基板等)的连接自由度可极大地增加。
在图1和图2所示的例子中,布线18(导电层8)可在与半导体芯片6的电极2所形成的面相反的面上形成。或者,如下所述,布线18可在半导体芯片6的电极2所形成的面上形成,也可在其两方的面上形成。
在半导体芯片6上,形成与电极2电导通的连接区14。连接区14可作为导电层8的一部分形成。连接区14可形成为在半导体芯片6的面上在通孔4的开口端部包围通孔4。另外,连接区14可作为布线18的一部分形成。在连接区14形成为布线18一部分时,通过布线18按指定的形状迂回走线,能够使相邻连接区14的间距比相邻电极2的间距拓宽。此时,如图2所示,在半导体芯片6的面上,连接区14多以二维扩展的方格形地改变间距。连接区14最好作为比布线18的宽度宽的大面积表面形成。连接区14在其表面上可作镀金之类的镀覆处理。
还有,导电层8形成为使得在连接区14之间的间距与多个电极2之中至少两个电极2之间的间距不同。
半导体芯片6的面上可形成应力减缓层。应力减缓层有减缓应力的功能。应力减缓层可用树脂形成,或用其它材料形成。应力减缓层在半导体芯片6的一面或两面形成。详细地讲,应力减缓层在半导体芯片6的电极2所形成的面上,在与之相反的面上或在这两方的面上形成。另外,例如通孔4在半导体芯片6的边缘区形成时,应力减缓层在半导体芯片6的面可比通孔4更近于中心区形成。应力减缓层的厚度以及平面面积在考虑到半导体器件的可靠性后可自由决定。
导电层8形成到应力减缓层上。详细地讲,在导电层8之中,构成布线18的部分中至少有一部分在应力减缓层上形成。另外,连接区14最好在应力减缓层上形成。亦即,至少布线18(导电层8)的连接区14在应力减缓层上形成。还有,应力减缓层可使用聚酰亚胺树脂,但对其材料并不加以限定。
如图1所示,应力减缓层还可形成为多个突起部20。此时,以到达各突起部20上的方式形成布线18(导电层8)。亦即,在各突起部20上可形成连接区14。因此,在半导体芯片6的面上,例如可形成以树脂为核的多个凸点。亦即,借助于作为突起部20所形成的应力减缓层以及在其表面上所形成的连接区14,可形成与金属凸点有大致相同功能的树脂凸点。此外,该树脂凸点借助于成为核的应力减缓层,在与其它构件(其它的半导体芯片或晶片,或电路基板等)的连接点处可使集中的应力得到减缓。还有,对突起部20的形状并不加以限定,但可呈棱锥形或圆锥形形成。
或者,如下所述,应力减缓层可形成为多个凹陷部。此时,以到达各凹陷部上的方式形成布线18(导电层8)。凹陷部例如可与两个以上的突起部并排形成,也可在两排突起部之间的区域形成。在各凹陷部可形成连接区。详细地讲,连接区14可在凹陷部内侧形成。通过形成凹陷部,可使具有诸如突起形状的凸点(包括树脂凸点)之类楔入凹陷部的内侧,可增大电连接区之间的接触面积。再有,如能增大连接区之间的接触面积,则凹陷部的形状不受限制。如图1和图2所示,在连接区14上可设置外部端子24。外部端子24例如可以是焊球,也可使焊料之类呈球状(突起状)设置。连接区14以在其上形成外部端子24构成基座。借助于外部端子24,可使半导体芯片6良好地结合到其它构件(其他半导体芯片或晶片,或电路基板等)上。
另外,未必需要焊球等外部端子24,也可将半导体器件安装在基板(中介物)上构成半导体组件。还可不形成焊球等,可利用在安装母板时涂敷在母板面上的焊锡膏,依靠其熔融时的表面张力以求实现电连接。
另外,在连接区14以外的区域形成阻焊层26。阻焊层26可作为防氧化膜,还可作为最终形成半导体器件时的保护膜,更可作为以提高防潮性为目的的保护膜。
下面,根据图3A~图10C的工序图来说明制造上述半导体器件1的方法。
如图3A所示,在半导体芯片6上在表面形成绝缘膜16,在绝缘膜16上形成电极2的下层部分2a。而且,在下层部分2a的两端,绝缘膜28、29层叠在下层部分2a之上,电极2的上层部分2b以到达绝缘膜29上的方式形成。还有,可形成钝化膜30,避开电极2的中心区而覆盖在电极2的两端。钝化膜30可用诸如SiO2、SiN或聚酰亚胺树脂之类的材料形成。
如图3B所示,在半导体芯片6的有源面,也就是电极2所形成的面上形成了也覆盖住电极2的抗蚀剂32。作为形成抗蚀剂32的方法可采用转涂法、浸渍法、喷涂法等方法。抗蚀剂32覆盖住在下述刻蚀工序中不被刻蚀的部分,它可以是光致抗蚀剂、电子束抗蚀剂、X射线抗蚀剂中的任何一种,可以是正型或负型中的任何一种。本实施例中使用的抗蚀剂32是正型的光致抗蚀剂。抗蚀剂32由于在涂覆后不附着于其它部件上,因此经过前烘,使溶剂挥发掉。
其次,如图3C所示,对抗蚀剂进行构图。详细地讲,在抗蚀剂32上要配置图中没有示出的掩模,照射能量。能量因抗蚀剂32的性质而异,是光、电子束、X射线中的任何一种。在本实施例中使用光致抗蚀剂进行曝光。掩模的形状由构图的形状决定,视抗蚀剂32是正型还是负型,掩模应反转其形状。
曝光后对抗蚀剂32显影并后烘。在经过构图后的抗蚀剂32上,形成使电极2的中心区暴露出来的开口部34。
如图4A所示,通过抗蚀剂32的开口部34对暴露出来的电极2的中心区进行刻蚀。刻蚀最好采用干法刻蚀。干法刻蚀可以是反应性离子刻蚀(RIE)。另外,刻蚀也可用湿法刻蚀。
就这样,如图4B所示,在电极2的中心区(除边缘区以外的部分),形成孔36。孔36在上述图1和图2中所述通孔4的位置上形成。详细地讲,孔36以与通孔4的开口端部大致相同或比它大的尺寸形成,与通孔4连通。
然后,在抗蚀剂32被剥离后,如图4C所示,在半导体芯片6的电极2所形成的一侧(有源面一侧)和与之相反的一侧(非有源面一侧)分别形成绝缘膜38、40。绝缘膜38、40可以是氧化硅膜或氮化硅膜,可用化学汽相淀积法(CVD法)形成。有源面一侧的绝缘膜38覆盖住电极2和钝化膜30。由于孔36是在电极2处形成的,因此绝缘膜38也覆盖住孔36的内部(内壁表面及暴露出来的绝缘膜16)。
接着,如图5A和图5B所示,在半导体芯片6的有源面一侧和非有源面一侧形成抗蚀剂42、44后,对这些抗蚀剂42、44进行构图,在形成上述图1和图2中所示通孔4的位置形成开口部46、48。开口部46在电极2的孔36的内侧形成,使得在孔36与开口部46之间存在绝缘膜38。因此,开口部46、48使绝缘膜38、40的一部分暴露出来。再有,抗蚀剂42、44的形成及其构图方法符合对上述抗蚀剂32所说明的内容。形成抗蚀剂42、44中的一方(例如抗蚀剂42)(在例如半导体芯片6的有源面一侧),经前烘之后,形成另一方(例如抗蚀剂44),对该抗蚀剂也要进行前烘。
如图5C所示,在绝缘膜16、38上,在电极2的孔36的内侧形成孔50,在绝缘膜40上形成孔52。
如图6A所示,将抗蚀剂42、44剥离。然后,如图6B所示,对半导体芯片6的孔50、52上暴露出来的部分进行刻蚀。该被刻蚀部分是没有形成集成电路的部分,由硅形成。通过如此刻蚀,就在半导体芯片6的表面形成在视觉上容易识别的凹坑54、56。凹坑54、56的形状并不特别加以限定,可以是作成锥形的形状,也可以有与表面垂直的内壁面。刻蚀以应用湿法刻蚀比较简单,而应用干法刻蚀亦可。按照刻蚀的种类来决定凹坑54、56的形状。
如图6C所示,在半导体芯片6上形成小孔58(例如直径约为20μm的小孔)。小孔58比起在上述图1和图2中所述的通孔4,其直径要小,并且在通孔4的中心处形成。为了形成小孔58,可使用激光器(例如YAG激光器或CO2激光器等)。激光光束能通过凹坑54。56识别位置并照射。激光光束可只从半导体芯片6的一方的面照射以形成小孔58,也可从半导体芯片6的两面(轮流或同时)照射激光光束。假如从两个面照射激光光束,则对半导体芯片6的影响较少。
如图7A所示,在半导体芯片6上形成通孔4。通孔4是使上述小孔58扩大后形成的。例如,应用湿法刻蚀,可对小孔58的内表面进行刻蚀。刻蚀液可用诸如将氢氟酸与氯化铵混合的水溶液(缓冲氢氟酸)。
通孔4可以形成为具有开口端部和比开口端部直径为大的中间部分(例如约为40~50μm的直径)的形状。使通孔4中间部分的直径尽可能增大,以易于进行下述的CVD和无电解电镀。中间部分就其全体而言,是以大致相同的直径形成的。亦即,通孔4中间部分的内壁表面在通过通孔4的中心轴的截面可描成一直线。或者,中间部分可以随着接近于半导体芯片6厚度方向的中点而以大的直径形成。此类形状是把小孔58湿法刻蚀扩大后得到的。借助于此类形状,可以抑制因形成通孔4而造成的半导体芯片6强度的降低。通孔4有一连接开口端部和中间部分的锥形部分。锥形部分也是把小孔58湿法刻蚀扩大后形成的。或者,可以把通孔4形成为直线状使得在轴向的全体部分开口处的截面成为大致相同的直径。
接着,如图7B所示,至少在通孔4的内壁表面形成绝缘膜10。为形成绝缘膜10,可应用CVD法。绝缘膜10也可在通孔4内壁表面以外的区域形成。例如,绝缘膜38、40上也可形成绝缘膜10。其中,在后面的工序中为形成导电层8,依靠绝缘膜10使得不堵塞通孔4的出口。
绝缘膜10可用树脂形成。此时,可向包括通孔4内壁表面的区域涂布树脂。涂布树脂的手段可使用转涂法、喷涂法或使二者组合起来的方法。转涂法通过调节滴下的树脂的粘度可在通孔4的内壁表面形成均匀的膜层。还有,喷涂法利用空气喷射或静电,可在通孔4上涂覆树脂。再有,通过涂布后的树脂在树脂中的溶剂挥发后而干燥,可以很容易使之涂覆在通孔4的内壁表面上。
或者,通过在通孔4内填注树脂,也可在通孔4的内壁表面形成绝缘膜10。可使用配料器之类将树脂注入通孔4。然后,形成贯穿通孔4内侧树脂的孔,此孔孔径比通孔4的孔径要小。亦即,一旦以树脂填注通孔4后,再使通孔4开一出口。贯穿树脂的孔可使用激光光束等形成。
借助于这些工序,仅靠涂布树脂即可形成绝缘膜10。亦即,不必使用特殊装置即可在短时间内以低成本形成绝缘膜。
接着,如图7C和图8A所示,在半导体芯片6的有源面一侧,在形成抗蚀剂64堵塞住半导体芯片6的通孔4一个面的出口后,对抗蚀剂64构图,形成开口部68。再有,在形成抗蚀剂64时,在非有源面一侧也能形成抗蚀剂66。然后对抗蚀剂64、66进行前烘。抗蚀剂64、66的形成及其构图方法,能够适用于对上述抗蚀剂32所作说明的内容。开口部68在电极2至少一部分的上方形成,但在通孔4的上方,仍保留抗蚀剂64的一部分。例如,开口部68在纳入电极2范围内形状的外缘和至少覆盖通孔4的开口端部的形状的内缘之间形成环状。再有,此处所谓的环状可以是方环状,也可以是圆环状。开口部68使绝缘膜10的一部分暴露出来。
接着,如图8B所示,以构图后的抗蚀剂64作为掩模,对绝缘膜10、38进行刻蚀,使电极2的一部分暴露出来。此处暴露出来的电极2的一部分由于是要进行电连接的部分,最好要大一些。此后,将抗蚀剂64、66剥离。
如图9A所示,在半导体芯片6的面上形成应力减缓层70。在图示的例子中,在与形成半导体芯片6的电极2的面相对的面上,形成应力减缓层70。应力减缓层70可通过涂布(例如用「转涂法」)感光性聚酰亚胺树脂形成。应力减缓层70可用覆盖在半导体芯片6的整个面上的方式形成。所形成的应力减缓层70最好在1~100μm的厚度范围,而以10μm左右的厚度更佳。再有,由于使用转涂法,浪费掉的聚酰亚胺树脂很多,故可使用由泵带状地喷出聚酰亚胺树脂的装置。这样的装置例如有FAS公司制造的FAS超精密喷出型涂敷系统(可参考美国专利第4696885号)。
如图9B所示,可使应力减缓层70在多个突起部20上形成。例如,可应用光刻技术使感光性树脂形成突起部20。亦即,对应力减缓层70进行曝光、显影和烘烤处理,只保留作为下述布线的基座的部分,即突起部20而去除掉其它部分。
或者,应力减缓层70使用非感光性树脂更佳。例如,在整个覆盖半导体芯片6的面上的应力减缓层70形成后,可通过刻蚀形成突起部20。或者,可用丝网印刷或喷墨方式直接形成突起部20。应力减缓层70的材料除聚酰亚胺树脂外,也可采用诸如硅改性聚酰亚胺树脂、环氧树脂和硅改性环氧树脂等。应力减缓层70固化时的杨氏模量较低(小于1×1010Pa),宜用作实现应力减缓功能的材料。
接着,在半导体芯片6上形成导电层8。例如,如图9C所示,在半导体芯片6的面上的突起部20上,包括通孔4的内壁表面敷设催化剂78。亦即,可用无电解电镀法(例如自催化镀法)形成导电层8。
首先,避开敷设催化剂78的指定区域,在半导体芯片6的有源面一侧和非有源面一侧形成抗蚀剂(图中没有示出)。例如可使半导体芯片6的有源面一侧和非有源面一侧的抗蚀剂形成图形,可形成与通孔4连通的开口部以及与该开口部相连的布线图形。在抗蚀剂所在的有源面一侧的开口部,使电极2暴露出来。在有源面一侧的抗蚀剂由于形成了有很大台阶的区域,因此最好使用预先作成膜状的薄层(干膜)。还有,抗蚀剂在构图后要进行前烘。
接着,从通孔4在电极2暴露部分上从抗蚀剂的暴露区域中,提供要涂敷供无电解电镀用的催化剂。此处,可用钯作催化剂。作为催化剂的形成方法,例如可将半导体芯片6浸渍在含钯和锡的混合溶液中,然后通过盐酸之类的酸进行处理,即可仅敷设钯。或者,通过将半导体芯片6浸渍在氯化锡溶液中藉以吸附锡离子(还原剂),然后将半导体芯片6浸渍在氯化钯溶液中,藉锡离子(还原剂)使钯离子还原,析出钯核(催化剂)。
还有,在将半导体芯片6浸渍在指定溶液中进行无电解电镀的场合,将抗蚀剂覆盖在除指定区域的整个面上,亦即最好直至半导体芯片6的侧面均形成抗蚀剂。藉此可防止处于溶液中的半导体芯片6的电极之间的电位变化。亦即可对无电解电镀法的金属析出等作均匀化处理。还有,出于同样的理由,在将半导体芯片6浸渍在溶液的场所最好要避光。
或者,催化剂可采取喷墨方式直接敷设。喷墨方式是已经用于喷墨打印机的实用化技术,采用这种技术可以做到高速并且不浪费墨水,比较经济。喷墨头例如是在喷墨打印机中实用化了的部件,采用压电元件的压电喷墨型,或采用电热转换体作为能量发生器的喷墨型,喷涂面积和喷涂图形可任意设定。因此,不必进行抗蚀剂构图工序和抗蚀剂剥离工序。此外,在整个面上形成金属层的场合,有可能无须刻蚀工序而形成导电层8。
接着,剥离掉半导体芯片6的有源面一侧和非有源面一侧的抗蚀剂。通过剥离抗蚀剂,可仅在要形成导电层8的区域敷设催化剂。抗蚀剂剥离时可照射紫外线,也可浸渍在弱碱性溶液中以剥离抗蚀剂。藉此可容易地并且可靠地剥离掉抗蚀剂。
再有,与上述在敷设抗蚀剂后再敷设催化剂78的例子不同,例如可在将催化剂78敷设到半导体芯片6的整个面后,除了在要形成导电层8的区域敷设抗蚀剂,结果在形成导电层8的区域使催化剂78暴露出来。在这种场合,在形成导电层8的工序结束后剥离掉抗蚀剂。
接着,如图10A所示,在催化剂78暴露的区域,通过无电解电镀形成导电层。导电层8之中,从半导体芯片6的面上从通孔4的开口端部延伸的区域上所形成的部分,构成布线18。另外,催化剂78敷设在通孔4的内壁表面(在图9C的例子中为绝缘膜10的表面)和半导体芯片6的有源面一侧和非有源面一侧。因此,在半导体芯片6的有源面一侧和非有源面一侧经过通孔4连续形成导电层8。还有,导电层8可层叠在电极2上。
导电层8的材料可采用Ni、Au、Ni+Au、Cu、Ni+Cu、Ni+Au+Cu中的任何一种。例如,使用铜镀液,以催化剂78的钯为核以还原溶液中的铜离子,使铜(导电层8)析出。还有,作为形成导电层8的导电材料,可采用多组不同种类的金属(例如Ni+Cu、Ni+Au+Cu),藉此,可形成多层导电层8。
为了进行无电解电镀,可采用弱碱性的铜镀液。作为弱碱性(PH值在9附近)的铜镀液,例如可采用将PB-570MU、PB-570A、PB-570B、PB570-C、PB-570S混合而成的PB-570(制造商名称:荏原ェ-ジ-ラ亻ト株式会社)。因此,由于铜镀液呈弱碱性,所以例如即便电极2为铝,也可减少对铝电极的损伤。
或者,假如在电极2的表面形成图中没有示出的导电层以保护电极2,则也可以使用强碱性溶液。导电层8可以是单层,也可以是多层。例如,能以镍和金的双层形成导电层8。作为用镍形成导电层8的方法,可预先在电极2上作镀锌处理,将铝的表面置换成锌,然后将其浸渍在无电解镍镀液中,经过锌和镍的置换反应,淀积一层镍。或者,可将铝浸渍在仅在铝上作有选择吸附的钯溶液中,然后浸渍在无电解镍镀液中,以钯为核,使之析出镍膜。导电层8可以仅在镍上形成,进而将其浸渍在无电解金镀液中,在镍的表面可进而形成金膜。借助于形成金膜,可使与导电层8的电连接变得更加可靠。
上述例子完全是采用湿法(镀)的导电层8的形成方法,然而作为其它的形成方法,可采用现行的干法(溅射等),或采用干法和湿法的组合方法。再有,导电层8也可用电镀形成。
此外,可形成与电极2进行电导通的电连接区14。如图所示,导电层8(布线18)的一部分可作为连接区14。此时,最好使导电层8增厚(例如约5μm以上),以形成连接区14。
借助于以上的工序,形成导电层8,导电层8的一部分位于非有源面上,形成布线18。布线18的末端覆盖住用聚酰亚胺之类的树脂所形成的突起部20的表面,该部分成为供形成焊球之用的连接区14。
还有,如图所示,最好在半导体芯片6上形成阻焊层26。例如,以整个覆盖在半导体芯片6的面上的方式形成感光性阻焊层26。然后,对阻焊层26进行曝光、显影和烘烤处理,如图10B所示,在阻焊层26之中去除掉覆盖连接区14部分的区域。阻焊层26最好至少要覆盖在布线18(导电层8的一部分)上。就这样,保留下来的阻焊层26可作为防氧化膜,也可作为最终形成半导体器件时的保护膜,还可作为以提高防潮性为目的的保护膜。
如图10C所示,可在连接区14上设置外部端子24。在图示的例子中,连接区14被设置在突起部20(应力减缓层70)上,而外部端子又在连接区14上形成。外部端子24可以是焊球。外部端子24的形成首先在连接区14上以厚层形式形成焊球状焊锡。该焊锡的厚度由与其后焊球形成时所需的球直径相对应的焊锡量来决定。焊锡层可通过电镀或印刷等方法形成。然后,采用“湿回法”作成半球以上的球状,形成焊球。此处,所谓“湿回法”是在外部端子24的形成位置形成焊锡材料后使之回流形成略呈半球状的凸点。
再有,可采用阻焊层26作为掩模,更可不设置掩模而形成外部端子24。藉此可简化工序。
通过以上的做法得到图1和图2所示的半导体器件1。然后根据如此形成的半导体器件1,可借助于突起区20以及借助于电路基板和半导体芯片6之间的热膨胀系数之差来减缓应力。然后,由于是将非有源面对着电路基板安装半导体芯片6,不会损伤到安装时处于相反一侧的有源面。因此,不用说半导体芯片6,即便安装了如此半导体芯片6的电路基板其可靠性也得到提高。
在上述半导体器件的制造方法中,以半导体芯片6为例加以说明,而若该半导体芯片6换成半导体晶片也是同样的。此时,在晶片工序内即可完成差不多全部工序。换言之,形成与安装好的基板相连接的外部端子的工序可在晶片工序内进行,而不必进行往常的封装工序,亦即处理每个半导体芯片,对每个半导体芯片逐一进行内引线键合工序和外部端子形成工序等。
按照本实施例,借助于在通孔4内形成导电层8,谋求对一个半导体元件(半导体芯片或半导体晶片)的面与另一半导体元件的面进行电连接。据此,由于不像往常那样向通孔4内填充熔融材料形成固态导体,也就没有产生空隙等问题,即可确保电连接的高可靠性。
再有,借助于形成导电层8使得在半导体元件的面上形成布线的手段,可改变连接区14的间距。亦即,它具有扩大与其它构件的连接自由度的优点。另外,在半导体元件上形成应力减缓层70(突起部20),其上又形成连接区14(导电层8)以及外部端子24,借助于应力减缓层70(突起部20)可使加到外部端子24上的应力得到减缓。还有,在本实施例中,就半导体元件的状态而言,由于直至半导体封装形态均可制造,也可没有预先设置外部端子并已构图的薄片之类的基板。
(第2实施例)
图11是与第2实施例有关的半导体器件的示意图。图12是与第2实施例的变例有关的半导体器件的示意图。在以下所示的实施例中,尽可能应用其它实施例中所述的内容。
本实施例中所述的半导体器件,可称之为三维安装型(叠层型)的CSP(芯片尺度/尺寸封装)。如图11所示,半导体器件100包括有电极2并且形成通孔4的多个半导体芯片6,以及在各半导体芯片6上形成的导电层8。
各个半导体芯片6呈层叠配置,层叠起来的一对半导体芯片6藉导电层8进行电连接。半导体器件100至少有一个是借助于上述实施例中所述工序制成的半导体器件1。在图示的例子中,半导体器件1被配置在半导体器件100的最下层。亦即,在最下层所配置的半导体芯片6的导电层8是从通孔4的开口端部起作为半导体芯片6面上的布线18而形成的。然后,在最下层半导体芯片6上形成的连接区14作间距变换,藉以在电路基板上简单地进行位置调整。
另外,在最下层的半导体芯片6上,形成突起部20,在其上方经过连接区14(布线18),形成外部端子24。据此,借助于突起部(应力减缓层70)可减缓因半导体器件100与电路基板的热膨胀系数不同而造成的应力。或者,不采用多个突起部20,而是在半导体芯片6的面上集中在形成多个外部端子24的区域中,保留应力减缓层70,借助于该应力减缓层70,即可减缓施加于半导体器件100之类上的应力。据此,由于可增加在半导体芯片6的面上所形成的应力减缓层70(例如树脂)的形成区域,因此可以有效地减缓施加到半导体器件100之类上的应力。
最下层的半导体芯片6的形成电极2的面可与其它半导体芯片6相对配置。在经过这样做后,将半导体器件100安装到电路基板的场合,可使与半导体芯片6的形成电极2的面相对的面(非有源面)朝向电路基板一侧。亦即,可以不损伤到安装时相反一侧的有源面,半导体器件100固不待言,即便安装有这样的半导体器件100的电路基板其可靠性也可得到提高。
层叠起来的一对半导体芯片6,借助于通孔4的开口端部所形成的各连接区14实现相互之间的电连接。还有,从最下层起第2层以上的半导体芯片6中形成电极2的面的方向,可以与最下层的半导体芯片6为同一方向,也可向相反方向配置。
在图11所示的例子中,从下面起第2至第4层半导体芯片6每一个都有同样的构成,较短地形成各个非有源面一侧的连接区14,使得成为仅是与其相连接的对方一侧半导体芯片的有源面一侧的电连接区14重合的长度。又,从下面起第2和第3层半导体芯片6与最下层的半导体芯片6同向,即有源面朝上层叠而成。还有,最上层的半导体芯片6,系有源面朝下层叠上去的。另外,该半导体器件100的上面。亦即最上层半导体芯片6的非有源面以阻焊层26覆盖,该半导体器件100的下面,亦即最下层半导体芯片6的非有源面上除外部端子24以外的部分以同样的阻焊层26覆盖而得到保护。
而且,使从下面起第2层半导体芯片6的非有源面一侧的连接区14重叠到最下层半导体芯片6的有源面一侧的电连接区14上。使从下面起第3层半导体芯片6的非有源面一侧的连接区14重叠到第2层半导体芯片6的有源面一侧的电连接区14上。使从下面起第4层半导体芯片6的有源面一侧的电连接区14重叠到第3层半导体芯片6的有源面一侧的电连接区14上。连接区14之间的相互键合可通过施加超声波振动或施加超声波振动同时加热来进行。一旦进行键合,就可通过振动和加热导致构成连接区14(导电层8)的材料相互扩散而形成金属键合。
或者,在图12所示的变例中,全部半导体芯片6(4层半导体芯片6)其有源面均朝上,即在朝向电路基板相反一侧的状态下层叠起来。还有,在最下层的半导体芯片6的非有源面一侧的表面绝缘膜上,可通过上述工序形成突起部20,包含电连接区14和布线18的导电层8、外部端子24以及阻焊层26。
而且,使从下面起第2层半导体芯片6的非有源面一侧的电连接区14重叠到最下层半导体芯片6的有源面一侧的连接区14上。使从下面起第3层半导体芯片6的非有源面一侧的电连接区14重叠到第2层半导体芯片6的有源面一侧的连接区14上。使从下面起第4层半导体芯片6的非有源面一侧的电连接区14重叠到第3层半导体芯片6的有源面一侧的连接区14上。而且,连接区14相互的键合可以是金属键合。
或者,全部半导体芯片6(4层半导体芯片6)其有源面均朝下,即可在朝向电路基板一侧的状态下层叠起来,各半导体芯片6的朝向不受上述情况限制。
另外,此处各半导体芯片6之间的电键合,以通过金属键合进行的情况为例进行了说明,然而这种电键合也可借助于焊锡之类的焊料、导电性粘结剂或氟化处理等进行。此外,导电性粘结剂可以是液态或胶状粘结剂,也可以是片状的粘结片。
粘结剂中的导电性物质由诸如焊料、焊锡之类的颗粒构成,这些颗粒散布在粘结材料之中。通过这样做使各半导体芯片相互键合时,上述颗粒起键合用焊料的作用,能使可键合性进一步得到显著提高。
还有,粘结剂可以是散布有导电颗粒的各向异性导电粘结剂(ACA),例如各向异性导电膜(ACF)或各向异性导电膏(ACP)。各向异性导电粘结剂是将导电颗粒(填料)散布于粘结剂中,有时也添加分散剂。作为各向异性导电粘结剂的粘结剂,多使用热固化性粘结剂。在这种场合,在各连接区14之间介入导电颗粒,以期实现两者之间的电连接。
在上述层叠型半导体器件中,以半导体芯片为例加以说明,然而该半导体芯片换成半导体晶片后也同样适用。亦即,把进行了与各层半导体芯片的制造工序相同的工序所得到的多片半导体晶片层叠起来,将各连接区进行电键合,然后进行切割,即可制成半导体器件100。
按照本实施例,作为具有层叠结构的小型半导体器件,能够提供可以很容易安装在电路基板上的半导体器件。
基于本实施例的半导体器件的制造方法包括将采用上述方法制成的各半导体器件层叠起来,将上下的半导体器件藉导电层8进行电连接的工序。
(第3实施例)
图13是基于第3实施例的半导体器件的示意图。半导体器件300包括有电极2并且形成通孔4的多个半导体芯片6,以及在各半导体芯片6上形成的布线18的导电层8。
按照本实施例,不仅在最下层,即便在其它半导体芯片6上,连接区14(布线18)也可作间距变换。详细地讲,层叠起来的一对半导体芯片6,其导电层8进而在从通孔4的开口端部延伸的区域形成并构成布线18,布线18按指定的形状迂回走线,以期实现连接区14的间距变换。据此,层叠起来的一对半导体芯片6相互之间很容易进行电连接。亦即,相邻连接区14的间距比相邻电极2的间距要宽,从而在多片半导体芯片6层叠时不致使各电极2之间短路。因此,可提高半导体器件制造时的成品率,并且可提供可靠性高、有层叠结构的半导体器件。
在层叠起来的一对半导体芯片6上的连接区14之间,最好藉形成凸点的方式,以期实现两者的电连接。例如,如图所示,连接区14之间可介入金属凸点80进行键合。金属凸点80可以是金凸点(包括镀金的凸点)或镍凸点、焊锡等焊料或使它们组合而成。其形成方法可列举镀覆(电镀或无电解电镀)处理、溅射、金属箔刻蚀或焊锡的回流等。另外,在半导体芯片6上,除连接区14外,最好特别在布线18(导电层8)上形成阻焊层26。再有,最上层的半导体芯片6最好在其上整体覆盖一层阻焊层26。
还有,也可与图示的例子不同,即在层叠起来的一对半导体芯片6之间形成应力减缓层。亦即,连接区14可在应力减缓层上形成。在这种场合,应力减缓层可在形成多个连接区14的区域经二维扩展而成。在本实施例中,尽管没有突起部,在大体为一个平面的应力减缓层70上形成连接区14,但仍可藉金属凸点80以期实现半导体芯片6之间的电连接。
(第4实施例)
图14~图16是基于第4实施例的半导体器件的示意图。在本实施例中,在层叠起来的一对半导体芯片6之间形成突起部20。
(第1个例子)
如图14所示,半导体芯片400包括有电极2并且形成通孔4的多个半导体芯片6,和包含在各半导体芯片6上所形成的布线18的导电层8,以及半导体芯片6的面上所形成的多个突起部20。然后,使层叠起来的一对半导体芯片6的突起部20之间相向配置。
半导体芯片6可在两面均形成突起部20。然后,在突起部20上形成连接区14。据此,在层叠起来的一对半导体芯片6之间,尤其是集中于两者连接点的应力可通过树脂之类(突起部20)得到减缓。因此,可提高半导体芯片6之间的连接可靠性。
再有,借助于将树脂形成为突起部20,能够以树脂为核形成凸点。亦即,可使用突起部20取代上述金属凸点80,不再形成凸点而能够在连接区14之间实现电连接。或者,即便还在连接区14上形成金属凸点也毫无关系。
还有,如图所示,从下面起第2层以上的半导体芯片6与最下层的半导体芯片6有同一形态。亦即,在全部半导体芯片6上,其连接区14均可在突起部20上形成。据此,由于可使以同一工序形成的半导体芯片6层叠起来,因此可以简化直至制造层叠结构的半导体器件的工序。
或者,也可与图示的例子不同,即在最下层的半导体芯片6,对着电路基板这一面而设置的应力减缓层可在二维扩展的区域形成。此时,应力减缓层(例如树脂)可在半导体芯片6的几乎整个面上形成。据此,半导体器件与电路基板之间因膨胀系数不同而造成的应力可得到有效的减缓。
另外,连接区14之间的电连接可采取金属键合、焊锡键合、导电性粘结剂等。
(第2个例子)
图15是基于本实施例第2个例子的半导体器件示意图。半导体芯片500包括:具有电极2并且形成通孔4的多个半导体芯片6、包含在各半导体芯片6上所形成的布线18的导电层8、以及在半导体芯片6的面上所形成的多个突起部20。
半导体芯片6在任何一片的面上均可形成突起部20。然后,层叠起来的一对半导体芯片6在一片半导体芯片6上形成突起部20的面,同与另一半导体芯片6上形成突起部20的面相反的面呈相向配置。在层叠起来的一对半导体芯片6之间,若在任何半导体芯片6上均形成突起部20,即能以此为凸点使两个连接区14之间实现电连接。
也可与图示的例子不同,即在与半导体芯片6上的形成突起部20的面相反的面上可形成大体为一个平面的应力减缓层。在这种场合,连接区14可在应力减缓层上形成,据此,由于在层叠起来的一对半导体芯片6之间由于在较大的区域内可夹有应力减缓层(例如树脂),施加于两片半导体芯片6之间连接区上的应力可以更有效地得到减缓。
(第3个例子)
图16是基于本实施例第3个例子的半导体器件示意图。半导体芯片600包括:具有电极2并且形成通孔4的多个半导体芯片6、包含在各半导体芯片6上所形成的布线18的导电层8、任何半导体芯片6的面上所形成的多个突起部20、以及任何半导体芯片6的面上所形成的多个凹陷部22。然后,在层叠起来的一对半导体芯片6之间,将一个半导体芯片6的突起部20楔入另一半导体芯片6的凹陷部22,以此实现两连接区14之间的电连接。
例如,如图所示,各半导体芯片6可在一片芯片的面上形成突起部20,在另一片的面上形成凹陷部22。然后,可使各半导体芯片6上形成突起部20的面与形成凹陷部22的面相向配置。突起部20至少一部分要楔入凹陷部22。据此,由于可使两连接区14之间的接触面积增大,各半导体芯片6可实现可靠的电连接。还有,由于突起部20嵌入凹陷部22,各半导体芯片6之间的对位变得十分容易。
凹陷部22的形状最好是易于容纳突起部20的形状。还有,如图所示,凹陷部22可与两个以上的突起部20并排,并可在它们之间形成。或者,在半导体芯片6的面上以大致呈一平面的方式形成应力减缓层,并在指定位置形成凹坑,藉此可形成多个凹陷部22,对凹陷部22的形态不加限定。还有,本实施例的效果如同以往所描述的那样。
图17示出安装了与本发明有关的半导体器件1的电路基板1000。在电路基板1000上通常采用诸如玻璃环氧树脂基板之类的有机系列基板。在电路基板1000上可形成由诸如铜之类组成的布线图形以得到所要的电路,通过把这些布线图形与成为半导体器件1的连接区的外部端子24机械地连接,以便实现它们的电导通。
另外,作为使用本发明中半导体器件1的电子设备,在图18示出了笔记本型个人计算机2000,在图19示出了移动电话机3000。
再有,如将上述实施例中的「半导体芯片」换成「电子元件」,也可以制造电子部件。使用这类电子元件制成的电子部件有诸如光元件、电阻器、电容器、线圈、振荡器、滤波器、温度传感器、热敏电阻、变阻器、电位器或熔断器等。
Claims (43)
1.一种半导体器件的制造方法,其特征在于包括:
在第1个面上有多个电极的半导体元件上形成通孔的第1工序;以及
形成与上述电极进行电连接、从上述通孔内壁表面达到上述第1个面上以及与上述第1个面相向的第2个面上的导电层的第2工序,
在上述第2工序中,在上述第1个面及上述第2个面配备连接区,并且在多个上述电极之中至少两个上述电极的间距与上述第1个面及上述第2个面之中至少任何一个面处的上述连接区的间距不同,以此形成上述导电层。
2.如权利要求1中所述的半导体器件的制造方法,其特征在于:
在上述第1工序中,预先形成其直径比上述通孔小的小孔,再将上述小孔扩大,形成上述通孔。
3.如权利要求2中所述的半导体器件的制造方法,其特征在于:
在形成上述小孔的位置处形成一个凹坑。
4.如权利要求2中所述的半导体器件的制造方法,其特征在于:
上述小孔用激光光束形成,采用湿法刻蚀使上述小孔扩大。
5.如权利要求1中所述的半导体器件的制造方法,其特征在于:
在上述电极处形成与上述通孔连通的孔。
6.如权利要求1中所述的半导体器件的制造方法,其特征在于:
上述通孔在上述半导体元件的端部一侧形成,
上述连接区可设置在比上述半导体元件的上述通孔更靠近中心一侧。
7.如权利要求1中所述的半导体器件的制造方法,其特征在于:
在上述第2工序前,还包括在上述第1个面及上述第2个面中至少任何一个面处形成应力减缓层的工序,
可以在上述第2工序中形成能达到上述应力减缓层上的上述导电层。
8.如权利要求7中所述的半导体器件的制造方法,其特征在于:
通过上述应力减缓层形成多个突起部,
在上述第2工序中,形成能到达各个上述突起部的上述导电层。
9.如权利要求7中所述的半导体器件的制造方法,其特征在于:
通过上述应力减缓层形成多个凹陷部,
可以在上述第2工序中形成到达各个上述凹陷部的上述导电层。
10.如权利要求7中所述的半导体器件的制造方法,其特征在于:
上述应力减缓层可以用树脂形成。
11.如权利要求7中所述的半导体器件的制造方法,其特征在于:
上述连接区可在以上述应力减缓层上形成。
12.如权利要求1至11中任何一项所述的半导体器件的制造方法,其特征在于:
相邻上述连接区的间距可以比相邻的上述电极的间距宽。
13.如权利要求1至11中任何一项所述的半导体器件的制造方法,其特征在于:
还包括在上述连接区上设置外部端子的工序。
14.如权利要求13中所述的半导体器件的制造方法,其特征在于:
在设置上述外部端子的工序中,在上述连接区上形成厚层焊锡后,用湿回法形成焊球。
15.如权利要求13中所述的半导体器件的制造方法,其特征在于:
在上述连接区上用电镀法或印刷法敷设焊锡。
16.如权利要求1至11中任何一项所述的半导体器件的制造方法,其特征在于:
在上述第2工序后,还包括至少在上述连接区以外的区域形成保护膜的工序。
17.如权利要求1至11中任何一项所述的半导体器件的制造方法,其特征在于:
在上述第1工序后,在上述第2工序前,还包括在包含上述通孔内壁表面的区域形成绝缘膜的工序,在上述第2工序中,在上述绝缘膜上形成上述导电层。
18.如权利要求17中所述的半导体器件的制造方法,其特征在于:
可以在包含上述通孔的内壁表面的区域,涂敷树脂以形成上述绝缘膜。
19.如权利要求17中所述的半导体器件的制造方法,其特征在于:
在形成上述绝缘膜的工序中,在上述通孔内埋入敷设树脂,可以在上述第2工序中形成上述导电层以使上述通孔内的上述树脂贯通。
20.如权利要求1中所述的半导体器件的制造方法,其特征在于:
上述半导体元件是半导体芯片。
21.如权利要求1中所述的半导体器件的制造方法,其特征在于:
上述半导体元件是半导体晶片的一部分。
22.如权利要求1至11、20、21中任何一项所述的半导体器件的制造方法,其特征在于:
还包括使得用制成的半导体器件层叠起来,在上下的半导体器件之间藉上述导电层实现电连接的工序。
23.如引用权利要求21的权利要求22所述的半导体器件的制造方法,其特征在于:
还包括将上述半导体晶片切割为单片的工序。
24.一种半导体器件,其特征在于包括:
具有通孔、并且在第1个面有多个电极的半导体元件;
与上述电极进行电连接、从上述通孔的内壁表面到上述第1个面及与上述第1个面相向的第2个面上形成的导电层;以及
配备在上述导电层上、在上述第1个面及上述第2个面中的至少任何一个面按照与多个上述电极之中至少两个上述电极的间距不同的间距形成的多个连接区。
25.如权利要求24中所述的半导体器件,其特征在于:
上述通孔在上述半导体元件的端部一侧形成,
上述连接区设置在比上述半导体元件的上述通孔更靠近于中心一侧。
26.如权利要求24中所述的半导体器件,其特征在于:
还包括在上述第1个面及上述第2个面中至少任何一个面上所形成的应力减缓层,
形成能到达上述应力减缓层上的的上述导电层。
27.如权利要求26中所述的半导体器件,其特征在于:
通过上述应力减缓层形成多个突起部,
形成能到达各个上述突起部的上述导电层。
28.如权利要求26中所述的半导体器件,其特征在于:
通过上述应力减缓层形成多个凹陷部,
形成能到达各个上述凹陷部的上述导电层。
29.如权利要求26中所述的半导体器件,其特征在于:
上述应力减缓层用树脂形成。
30.如权利要求26中所述的半导体器件,其特征在于:
上述连接区在上述应力减缓层上形成。
31.如权利要求24至30中任何一项所述的半导体器件,其特征在于:
相邻上述连接区的间距比相邻的上述电极的间距宽。
32.如权利要求24至30中任何一项所述的半导体器件,其特征在于:
进而包括在上述连接区上设置的外部端子。
33.如权利要求24至30中任何一项所述的半导体器件,其特征在于:
在除上述连接区以外的区域形成保护膜。
34.如权利要求24至30中任何一项所述的半导体器件,其特征在于:
在包含上述通孔内壁表面的区域形成绝缘膜,
上述导电层在上述绝缘膜上形成。
35.如权利要求24至30中任何一项所述的半导体器件,其特征在于:
上述半导体元件是半导体芯片。
36.如权利要求24至30中任何一项所述的半导体器件,其特征在于:
上述半导体元件是半导体晶片的一部分。
37.一种层叠型半导体器件,由多片半导体器件层叠而成,其特征在于:
至少最下层的半导体器件是权利要求24至30中任何一项所述的半导体器件。
38.一种层叠型半导体器件,其特征在于:
由权利要求24至30中任何一项所述的多个半导体器件层叠而成,上下的半导体器件可通过上述导电层实现电连接。
39.一种层叠型半导体器件,其特征在于:
由权利要求27所述的多个半导体器件层叠而成,上下的半导体器件藉上述导电层进行电连接,
在层叠起来的一对上述半导体器件上,上述应力减缓层的上述突起部之间相向配置。
40.一种层叠型半导体器件,其特征在于:
将权利要求27中所述的半导体器件与权利要求28中所述的半导体器件层叠起来,上下的半导体器件通过上述导电层实现电连接,
在层叠起来的一对上述半导体器件上,一方的半导体元件上的上述突起部楔入另一方半导体元件上的上述凹陷部。
41.如权利要求37中所述的半导体器件,其特征在于:
最下层的半导体器件与将上述半导体元件上的上述第1个面层叠起来的另一半导体器件相向配置。
42.一种电路基板,其特征在于:
其上安装有权利要求24至30、39中任何一项所述的半导体器件或层叠型半导体器件。
43.一种电子设备,其特征在于:
其中具有权利要求24至30、39中任何一项所述的半导体器件或层叠型半导体器件。
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US20040155355A1 (en) | 2004-08-12 |
US6962865B2 (en) | 2005-11-08 |
JP2002208655A (ja) | 2002-07-26 |
TW492120B (en) | 2002-06-21 |
US6720661B2 (en) | 2004-04-13 |
KR100447830B1 (ko) | 2004-09-08 |
US20040155354A1 (en) | 2004-08-12 |
KR20010110170A (ko) | 2001-12-12 |
US20020030245A1 (en) | 2002-03-14 |
CN1275312C (zh) | 2006-09-13 |
US7102219B2 (en) | 2006-09-05 |
JP3879816B2 (ja) | 2007-02-14 |
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