CN1327476C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN1327476C
CN1327476C CNB028166116A CN02816611A CN1327476C CN 1327476 C CN1327476 C CN 1327476C CN B028166116 A CNB028166116 A CN B028166116A CN 02816611 A CN02816611 A CN 02816611A CN 1327476 C CN1327476 C CN 1327476C
Authority
CN
China
Prior art keywords
epoxy resin
interconnection
semiconductor device
conductive
tube core
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB028166116A
Other languages
English (en)
Other versions
CN1547758A (zh
Inventor
马丁·斯坦丁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies North America Corp
Original Assignee
International Rectifier Corp USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Rectifier Corp USA filed Critical International Rectifier Corp USA
Publication of CN1547758A publication Critical patent/CN1547758A/zh
Application granted granted Critical
Publication of CN1327476C publication Critical patent/CN1327476C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/90—Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83905—Combinations of bonding methods provided for in at least two different groups from H01L2224/838 - H01L2224/83904
    • H01L2224/83907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01056—Barium [Ba]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

一种芯片尺寸封装及其制造方法，该方法包括：在半导体晶片的主表面上淀积钝化层，所述半导体晶片包括由划线彼此隔离的多个相同半导体管芯，每个管芯具有在其主表面上的主电接触；在所述钝化层中形成多个窗口，每个窗口设置在各个管芯的所述主电接触上并露出所述主电接触；在每个所述窗口中淀积含有导电颗粒的导电环氧树脂，从而在每个所述主电接触上形成互连；在每个所述互连周围形成一层热环氧树脂；和沿着所述划线切割所述晶片，从而形成多个半导体器件。

Description

半导体器件及其制造方法
技术领域
本申请涉及一种半导体器件，特别涉及芯片尺寸半导体器件及其制造方法。
背景技术
本申请基于并要求在2002年8月24日申请的、题为“晶片级下填(underfill)和互连工艺”的美国临时申请No.60/314818的优先权，这里结合该申请的主题和公开内容供参考。
半导体器件如功率开关是电子器件的常用部件。这种器件经常被封装，以便它们可以实际上安装到电子电路中。由于希望有更小的电子器件，因此要求更小尺寸的电子封装。由此研制了芯片尺寸封装，这种封装的尺寸是半导体器件的尺寸或近似尺寸。
还公知一种半导体器件封装，其中所有电极位于公共管芯表面上，并可以连接到如印刷电路板之类的支撑表面上的相应导电焊盘或迹线上。
半导体封装在电路板上的适当放置和固定是制造电子电路的重要步骤。目前，这种器件首先被向下焊接到电路板上，并且在分立的步骤中，在器件周边周围施加液体环氧树脂，这些液体环氧树脂由于毛细作用而被引入器件底部和电路板顶部之间的空间中，形成下填，从而提高器件温度循环能力。通常，这种工艺要求在施加下填材料之前首先在自动化步骤中焊接该器件。因此，如果在焊接工艺期间该器件没有完全放好，则存在下填材料将不准确设置的机会，并且可能意外地溢出到电路板的其它区域。这当然是不希望的，并且可能要求用这种方式设计的电路板容纳由于半导体封装的位置放错产生的溢出物。例如，电路板上趋于用于半导体封装的区域可以扩大以容纳下填材料的溢出物。这种解决方案当然需要扩大电路板，这与对更小电子器件的期望是相违背的。
希望提供一种半导体封装，能够精确地放在电路板上，并在其上固定，而没有上述常规公知器件的缺点。
发明内容
制备根据本发明的半导体器件，它包括电路板固定和下填所需要的材料，以至于用户只需提供热漂移以完成固定工艺，由此避免由现有技术封装和固定方法所遇到的问题。
根据本发明，可以以晶片级制成的新固定系统采用用于互连的银承载环氧树脂和设置在银承载互连之间的用于下填的热环氧树脂。
本发明的优选实施例是倒装片式半导体器件，在分割(singulation)之前在晶片级处理该器件。
具体而言，首先用合适的光敏环氧树脂钝化涂层涂覆具有多个相同管芯的晶片。然后处理这个层以在每一个管芯的接触上打开窗口。然后互连将设置在每个管芯的每个接触上，并通过各个窗口与每个管芯的每个接触相连。
根据本发明的方案，互连由具有一定有益特性的银承载环氧树脂构成。具体而言，银承载环氧树脂具有作为基体材料的树脂，它是半固态的，并且在室温下的触感将是粘稠的。银承载环氧树脂还可以包括在室温下和在较高温度下提供互连结构整体性的填料。
为了允许银承载环氧树脂设置在各个管芯的内容物上，可以使用溶剂还原。这些溶剂在蒸发时会离开具有粘稠外部表面的互连。
然后，热环氧树脂向下穿过晶片表面放置。将要构成下填层的热环氧树脂在室温下是固态的(直到比用于互连的温度稍高的温度保持固态)，并且用溶剂还原。热环氧树脂层可以通过重复淀积和蒸发到略小于互连高度的厚度的工艺来形成。
一旦形成了热环氧树脂层，例如通过锯开法分割管芯，由此形成多个芯片级尺寸的半导体器件。
为了实现本发明的目的，根据本发明的一个方面，在焊料回流工艺如通常用于SMT(表面贴装)组件的焊料回流工艺期间，首先对根据本发明的半导体器件进行回流处理，然后固化热环氧树脂，形成下填结构。具体地说，当首先将该器件放在电路板上时，该器件的粘稠互连足以保持该器件在电路板上的适当位置。随着温度升高，互连树脂开始变为可移动的，但是填料将防止这些互连在这个阶段塌陷。随着温度进一步升高，热环氧树脂变得可移动，并且没有结构化的填料，将变得不太粘稠。因此，热环氧树脂容易流动并通过毛细作用向半导体器件中心牵引。根据本发明的一个方面，提供了一种制造半导体器件的方法，可包括：在半导体晶片的主表面上淀积钝化层，所述半导体晶片包括由划线彼此隔离的多个相同半导体管芯，每个管芯具有在其主表面上的主电接触；在所述钝化层中形成多个窗口，每个窗口设置在各个管芯的所述主电接触上并露出所述主电接触；在每个所述窗口中淀积含有导电颗粒的导电环氧树脂，从而在每个所述主电接触上形成互连；在每个所述互连周围形成一层热环氧树脂；和沿着所述划线切割所述晶片，从而形成多个半导体器件。
根据本发明的另一个方面，提供了一种半导体器件，可包括：具有主表面的半导体管芯；在所述半导体管芯的所述主表面上的电接触；在所述电接触上的互连，所述互连由含有导电颗粒的粘稠环氧树脂和溶剂构成；和设置在所述主表面上和包围所述互连的热环氧树脂层。
根据本发明的另一个方面，还提供了一种将半导体管芯固定到导电焊盘的方法，其中所述半导体管芯在其主表面上具有主电接触，该方法可包括：a)在所述主电接触上设置互连，所述互连包括含有导电颗粒的粘稠环氧树脂；b)用热环氧树脂层包围所述互连；c)将所述互连粘接到所述导电焊盘上；d)将所述互连加热到回流温度，从而在所述互连和所述导电焊盘之间形成连接；和e)进一步将所述热环氧树脂加热到固化温度，所述固化温度高于所述回流温度。
在本发明的优选实施例中，一旦温度超过约110℃，则环氧树脂开始固化。然而，如果需要的话，这个固化温度可以升高。在根据本发明的半导体器件中使用的该环氧树脂和热环氧树脂的硬化系统被选择为能够在焊料回流循环内完全固化。
附图说明
图1表示具有形成在半导体晶片顶表面上的多个相同半导体管芯的半导体晶片的顶部平面图。
图2表示由图1所示的晶片的典型部分的顶部平面图。
图3表示具有钝化层的由图2所示的晶片的典型部分，其中在晶片中的管芯的电接触上有窗口。
图4表示在箭头4-4的方向和4-4之间观看到的图3所示部分的一部分。
图5表示具有在其窗口中形成的银承载环氧树脂互连的由图3所示的晶片的典型部分。
图6表示在箭头5-5的方向和5-5之间观看到的图5所示的部分的一部分。
图7表示具有在每个管芯的互连周围设置的热环氧树脂层的由图5所示的晶片的典型部分。
图8表示在箭头8-8的方向和8-8之间观看到的图7所示部分的一部分。
图9是在加热之前设置在电路板上的根据本发明的半导体器件的侧视图。
图10表示在适当的加热步骤之后连接到电路板上的根据本发明的半导体器件的侧视图。
具体实施方式
图1表示单片硅的晶片100，它包括形成在其中的多个相同的管芯10。形成在晶片100中的管芯10可以是功率开关器件如MOSFET或IGBT或功率二极管。
图2表示晶片100的典型部分105，它包括多个相邻设置的管芯10。每个管芯10与其相邻的管芯10通过交叉划线110隔开。根据该优选实施例，管芯10是MOSFET，它包括只在其主表面之一上的所有它的主电接触11、12、13、14。具体而言，每个管芯10包括只在其一个主表面上的源极接触11、12、漏极接触13和栅极接触14。其它种类的管芯也可以被处理成根据本发明的半导体器件。
下面参照图3和4，钝化层30设置在晶片100的整个表面上，其典型部分105由图3示出。钝化层30由光敏环氧树脂构成。
接着，使用可包括成像步骤以及之后的固化步骤的光刻法，处理钝化层30，以便分别在每个管芯的源极接触11、12、漏极接触13和栅极接触14上提供窗口31、32、33、34。每个窗口31-34从钝化层30的顶部延伸到各个接触的顶表面，由此露出各个接触。
下面参照图5和6，在每个管芯的窗口31、32、33、34内部淀积银承载环氧树脂，在其中形成分别电连接到每个管芯10的电接触11-14的互连40、41、42、43。银承载环氧树脂可以用任何希望的方式淀积，如通过丝网印刷或通过分散法。根据该优选实施例的银承载环氧树脂包括60％到85％重量银的银颗粒，银颗粒的尺寸为3到40微米。而且，在该优选实施例中，在互连40、41、42、43中使用的银环氧树脂将含有合适的溶剂，如Dowanol PMA(丙二醇)或相似的化学材料。溶剂的选择将取决于其速度和挥发性。就是说，实现慢得足以处理该材料和快得足以导致较短烘干时间之间的平衡。而且，还应该指出，溶剂含量将确定由互连40、41、42、43所经受的收缩性。此外，该优选实施例中的溶剂的蒸发温度将保持低于环氧树脂的固化温度。优选地，溶剂速度为约1小时。明显地，当溶剂蒸发时，并且环氧树脂仍然未固化时，互连40、41、42、43的表面将是稍微粘稠的。
在该优选实施例中，除了银颗粒之外，银承载环氧树脂将含有适量的填料，如微粉化玻璃、云母或硫酸钡。填料将防止在环氧树脂为半液体如当加热互连时形成互连40、41、42、43的环氧树脂塌陷。
下面参照图7和8，在晶片100的顶表面上淀积热环氧树脂层50，其典型部分105由图7示出。然后蒸发热环氧树脂50中的溶剂，得到未固化的固态热环氧树脂层50。如图8示意示出的，热环氧树脂层50在烘干后包围每个管芯10的互连40、41、42、43并延伸到低于互连40、41、42、43高度的高度。热环氧树脂层50可以在一个步骤中淀积，然后进行烘干步骤，或者在多个淀积步骤中淀积，每个淀积步骤之后是烘干步骤。可用在导电互连和热环氧树脂中的环氧树脂包括环氧酚醛(novalac)或双苯基A和双苯基F的混合物。
然后通过例如沿着线110锯开而将晶片100分割成单独的半导体器件。然后可以如在胶带和卷轴中封装如此制造的半导体器件，并运送给用户，其中每个器件的互连40、41、42、43由粘稠的和未固化的银承载环氧树脂形成，并且每个器件包括包围其互连40、41、42、43的一层干燥和未固化的热环氧树脂50。
参见图9和10，互连40、41、42、43的粘稠或粘性表面保持管芯在电路板60上的位置上。之后，使用传统焊料回流工艺对电路板(它还可承载将要向下焊接的其它元件)进行回流。
互连40、41、42、43在约80℃下变得稍微软一些，并且允许与电路板60上的导电焊盘(未示出)形成接点。同时，热环氧树脂层50变得非常有流动性(达到了稠油的稠度)并流动从而在管芯10和电路板60的顶表面之间形成接点。热环氧树脂层50的粘性继续减小，直到温度超过约150℃为止。此时，外部环氧树脂50中的催化剂开始固化反应。通过使用公知的固化引发剂和阻滞剂控制催化剂以停止低温固化。当电路板60从回流炉的端部引出时，环氧树脂系统固化，并且该器件具有连接到电路板60的导电焊盘的银互连。如图10中最佳示出的，除了互连40、41、42、43被下填的位置之外，热环氧树脂50已经流出并在管芯10表面和电路板60之间形成键合部。
虽然前面已经针对本发明的特殊实施例介绍了本发明，但是各种修改和改变以及其它用途对于本领域普通技术人员来说是显而易见的。因此，优选本发明不限于这里公开的具体例子。

Claims (22)

1.一种制造半导体器件的方法，包括：
在半导体晶片的主表面上淀积钝化层，所述半导体晶片包括由划线彼此隔离的多个相同半导体管芯，每个管芯具有在其主表面上的主电接触；
在所述钝化层中形成多个窗口，每个窗口设置在各个管芯的所述主电接触上并露出所述主电接触；
在每个所述窗口中淀积含有导电颗粒的导电环氧树脂，从而在每个所述主电接触上形成互连；
在每个所述互连周围形成一层热环氧树脂；和
沿着所述划线切割所述晶片，从而形成多个半导体器件。
2.根据权利要求1的制造半导体器件的方法，其中所述一层热环氧树脂形成为其最大高度低于所述互连最大高度。
3.根据权利要求1的制造半导体器件的方法，其中所述一层热环氧树脂是通过热环氧树脂的多个淀积步骤并在每个步骤之后进行蒸发步骤而形成的。
4.根据权利要求1的制造半导体器件的方法，其中所述钝化层包括光敏环氧树脂。
5.根据权利要求1的制造半导体器件的方法，其中所述窗口是通过光刻成像步骤并在之后进行固化步骤而形成的。
6.根据权利要求1的制造半导体器件的方法，其中所述导电颗粒包括银。
7.根据权利要求1的制造半导体器件的方法，其中所述导电环氧树脂包括60％到85％重量的银颗粒，所述颗粒的粒度为3到40微米。
8.根据权利要求1的制造半导体器件的方法，其中所述导电环氧树脂包括溶剂。
9.根据权利要求1的制造半导体器件的方法，其中所述导电环氧树脂是通过丝网印刷和分散法之一淀积的。
10.根据权利要求1的制造半导体器件的方法，其中每个相应管芯的所有主电接触都只设置在其一个主表面上，并且在形成所述一层热环氧树脂之前，在每个相应管芯的所有主电接触上形成互连。
11.一种半导体器件，包括：
具有主表面的半导体管芯；
在所述半导体管芯的所述主表面上的电接触；在所述电接触上的互连，所述互连由含有导电颗粒的粘稠环氧树脂和溶剂构成；和
设置在所述主表面上和包围所述互连的热环氧树脂层。
12.根据权利要求11的半导体器件，其中所述一层热环氧树脂层的最大高度低于所述互连的最大高度。
13.根据权利要求11的半导体器件，其中所述导电颗粒包括银。
14.根据权利要求11的半导体器件，其中所述导电环氧树脂包括60％到85％重量的银颗粒，所述颗粒的粒度为3到40微米。
15.根据权利要求11的半导体器件，其中所述管芯的所有主电接触都设置在所述主表面上，并且互连形成在所述管芯的所有主电接触上。
16.一种将半导体管芯固定到导电焊盘的方法，其中所述半导体管芯在其主表面上具有主电接触，该方法包括：
在所述主电接触上设置互连，所述互连包括含有导电颗粒的粘稠环氧树脂；
用热环氧树脂层包围所述互连；
将所述互连粘接到所述导电焊盘上；
将所述互连进行第一加热到回流温度，从而在所述互连和所述导电焊盘之间形成连接；和
进一步将所述热环氧树脂加热到固化温度，所述固化温度高于所述回流温度。
17.根据权利要求16的方法，其中所述导电焊盘位于功率电路板上。
18.根据权利要求16的方法，其中所述热环氧树脂包括引发剂和阻滞剂，以便确保所述固化温度将不低于所述回流温度。
19.根据权利要求16的方法，其中所述回流温度约为80，所述固化温度约为150℃。
20.根据权利要求16的方法，其中在所述第一加热后，使所述热环氧树脂变为液体，并且所述管芯与所述导电焊盘隔开，以便通过毛细作用允许所述热环氧树脂流到所述管芯的中心部分。
21.根据权利要求16的方法，其中所述粘稠环氧树脂包括填料。
22.根据权利要求16的方法，其中所述导电颗粒包括60％到85％重量的所述粘稠环氧树脂，并包括粒度为3到40微米的银颗粒。
CNB028166116A 2001-08-24 2002-08-21 半导体器件及其制造方法 Expired - Lifetime CN1327476C (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US31481801P 2001-08-24 2001-08-24
US60/314,818 2001-08-24
US10/225,399 US6582990B2 (en) 2001-08-24 2002-08-20 Wafer level underfill and interconnect process
US10/225,399 2002-08-20
PCT/US2002/027065 WO2003019628A1 (en) 2001-08-24 2002-08-21 Wafer level underfill and interconnect process

Publications (2)

Publication Number Publication Date
CN1547758A CN1547758A (zh) 2004-11-17
CN1327476C true CN1327476C (zh) 2007-07-18

Family

ID=26919563

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB028166116A Expired - Lifetime CN1327476C (zh) 2001-08-24 2002-08-21 半导体器件及其制造方法

Country Status (5)

Country Link
US (2) US6582990B2 (zh)
EP (1) EP1428246A4 (zh)
CN (1) CN1327476C (zh)
TW (1) TW569331B (zh)
WO (1) WO2003019628A1 (zh)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4166627B2 (ja) * 2003-05-30 2008-10-15 株式会社デンソー 半導体装置
US7352558B2 (en) 2003-07-09 2008-04-01 Maxwell Technologies, Inc. Dry particle based capacitor and methods of making same
US7791860B2 (en) 2003-07-09 2010-09-07 Maxwell Technologies, Inc. Particle based electrodes and methods of making same
KR100520080B1 (ko) * 2003-07-18 2005-10-12 삼성전자주식회사 반도체칩 표면실장방법
US7920371B2 (en) 2003-09-12 2011-04-05 Maxwell Technologies, Inc. Electrical energy storage devices with separator between electrodes and methods for fabricating the devices
JP4536366B2 (ja) * 2003-12-22 2010-09-01 株式会社豊田中央研究所 半導体装置とその設計支援用プログラム
US7090946B2 (en) 2004-02-19 2006-08-15 Maxwell Technologies, Inc. Composite electrode and method for fabricating same
US7440258B2 (en) 2005-03-14 2008-10-21 Maxwell Technologies, Inc. Thermal interconnects for coupling energy storage devices
US20070054559A1 (en) * 2005-09-02 2007-03-08 Maxwell Technologies, Inc. Thermal interconnects for coupling energy storage devices
US7429521B2 (en) * 2006-03-30 2008-09-30 Intel Corporation Capillary underfill of stacked wafers
US7768075B2 (en) 2006-04-06 2010-08-03 Fairchild Semiconductor Corporation Semiconductor die packages using thin dies and metal substrates
US7541681B2 (en) * 2006-05-04 2009-06-02 Infineon Technologies Ag Interconnection structure, electronic component and method of manufacturing the same
US7757392B2 (en) 2006-05-17 2010-07-20 Infineon Technologies Ag Method of producing an electronic component
US7476978B2 (en) * 2006-05-17 2009-01-13 Infineon Technologies, Ag Electronic component having a semiconductor power device
US7626262B2 (en) * 2006-06-14 2009-12-01 Infineon Technologies Ag Electrically conductive connection, electronic component and method for their production
DE102006044690B4 (de) * 2006-09-22 2010-07-29 Infineon Technologies Ag Elektronisches Bauteil und Verfahren zum Herstellen
DE102006047761A1 (de) * 2006-10-06 2008-04-10 Infineon Technologies Ag Halbleiterbauteil und Verfahren zu dessen Herstellung
DE102007007142B4 (de) * 2007-02-09 2008-11-13 Infineon Technologies Ag Nutzen, Halbleiterbauteil sowie Verfahren zu deren Herstellung
US7759777B2 (en) * 2007-04-16 2010-07-20 Infineon Technologies Ag Semiconductor module
FR2915573B1 (fr) * 2007-04-25 2010-04-02 Fr De Detecteurs Infrarouges S Procede pour la realisation d'une matrice de detection de rayonnements electromagnetiques et notamment de rayonnements infrarouges
US7879652B2 (en) * 2007-07-26 2011-02-01 Infineon Technologies Ag Semiconductor module
US7701065B2 (en) * 2007-10-26 2010-04-20 Infineon Technologies Ag Device including a semiconductor chip having a plurality of electrodes
US7799614B2 (en) 2007-12-21 2010-09-21 Infineon Technologies Ag Method of fabricating a power electronic device
US7968378B2 (en) * 2008-02-06 2011-06-28 Infineon Technologies Ag Electronic device
US8637341B2 (en) * 2008-03-12 2014-01-28 Infineon Technologies Ag Semiconductor module
US7759163B2 (en) * 2008-04-18 2010-07-20 Infineon Technologies Ag Semiconductor module
US8710665B2 (en) 2008-10-06 2014-04-29 Infineon Technologies Ag Electronic component, a semiconductor wafer and a method for producing an electronic component
US9093448B2 (en) 2008-11-25 2015-07-28 Lord Corporation Methods for protecting a die surface with photocurable materials
JP5318222B2 (ja) * 2008-11-25 2013-10-16 ロード コーポレイション 光硬化性材料でダイ表面を保護する方法
US8906747B2 (en) * 2012-05-23 2014-12-09 Freescale Semiconductor, Inc. Cavity-type semiconductor package and method of packaging same
TW201543720A (zh) * 2014-05-06 2015-11-16 Genesis Photonics Inc 封裝結構及其製備方法
KR101976175B1 (ko) * 2017-09-20 2019-05-08 엘지전자 주식회사 화합물 태양전지 모듈 및 그 제조 방법

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5492863A (en) * 1994-10-19 1996-02-20 Motorola, Inc. Method for forming conductive bumps on a semiconductor device
US5661042A (en) * 1995-08-28 1997-08-26 Motorola, Inc. Process for electrically connecting electrical devices using a conductive anisotropic material
US5940729A (en) * 1996-04-17 1999-08-17 International Business Machines Corp. Method of planarizing a curved substrate and resulting structure
US5976953A (en) * 1993-09-30 1999-11-02 Kopin Corporation Three dimensional processor using transferred thin film circuits
US6168972B1 (en) * 1998-12-22 2001-01-02 Fujitsu Limited Flip chip pre-assembly underfill process
US6245595B1 (en) * 1999-07-22 2001-06-12 National Semiconductor Corporation Techniques for wafer level molding of underfill encapsulant

Family Cites Families (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3403438A (en) 1964-12-02 1968-10-01 Corning Glass Works Process for joining transistor chip to printed circuit
DE1514453A1 (de) 1965-04-26 1969-08-14 Siemens Ag Verfahren zum Herstellen von Halbleiterschaltungen
US3871014A (en) 1969-08-14 1975-03-11 Ibm Flip chip module with non-uniform solder wettable areas on the substrate
US3972062A (en) 1973-10-04 1976-07-27 Motorola, Inc. Mounting assemblies for a plurality of transistor integrated circuit chips
GB1487945A (en) 1974-11-20 1977-10-05 Ibm Semiconductor integrated circuit devices
US4604644A (en) 1985-01-28 1986-08-05 International Business Machines Corporation Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making
US5270253A (en) * 1986-01-27 1993-12-14 Mitsubishi Denki Kabushiki Kaisha Method of producing semiconductor device
EP0259727A3 (de) * 1986-09-11 1989-02-08 Siemens Aktiengesellschaft Verfahren zur Herstellung wärmebeständiger strukturierter Schichten auf Epoxidharzbasis
EP0360971A3 (en) 1988-08-31 1991-07-17 Mitsui Mining & Smelting Co., Ltd. Mounting substrate and its production method, and printed wiring board having connector function and its connection method
US5634267A (en) 1991-06-04 1997-06-03 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
JP2660934B2 (ja) 1989-10-30 1997-10-08 三井金属鉱業株式会社 接続機能を有するテープキャリヤ
US5656862A (en) 1990-03-14 1997-08-12 International Business Machines Corporation Solder interconnection structure
US5136365A (en) 1990-09-27 1992-08-04 Motorola, Inc. Anisotropic conductive adhesive and encapsulant material
JP2984068B2 (ja) 1991-01-31 1999-11-29 株式会社日立製作所 半導体装置の製造方法
US5559444A (en) 1991-06-04 1996-09-24 Micron Technology, Inc. Method and apparatus for testing unpackaged semiconductor dice
JPH05129516A (ja) 1991-11-01 1993-05-25 Hitachi Ltd 半導体装置
CA2089435C (en) 1992-02-14 1997-12-09 Kenzi Kobayashi Semiconductor device
JP2833326B2 (ja) * 1992-03-03 1998-12-09 松下電器産業株式会社 電子部品実装接続体およびその製造方法
FR2690278A1 (fr) 1992-04-15 1993-10-22 Picogiga Sa Composant photovoltaïque multispectral à empilement de cellules, et procédé de réalisation.
JPH0637143A (ja) * 1992-07-15 1994-02-10 Toshiba Corp 半導体装置および半導体装置の製造方法
US5394490A (en) 1992-08-11 1995-02-28 Hitachi, Ltd. Semiconductor device having an optical waveguide interposed in the space between electrode members
US5313366A (en) 1992-08-12 1994-05-17 International Business Machines Corporation Direct chip attach module (DCAM)
KR100280762B1 (ko) * 1992-11-03 2001-03-02 비센트 비.인그라시아 노출 후부를 갖는 열적 강화된 반도체 장치 및 그 제조방법
JPH06244231A (ja) 1993-02-01 1994-09-02 Motorola Inc 気密半導体デバイスおよびその製造方法
US5371404A (en) 1993-02-04 1994-12-06 Motorola, Inc. Thermally conductive integrated circuit package with radio frequency shielding
JP2795788B2 (ja) * 1993-02-18 1998-09-10 シャープ株式会社 半導体チップの実装方法
US5703405A (en) 1993-03-15 1997-12-30 Motorola, Inc. Integrated circuit chip formed from processing two opposing surfaces of a wafer
US5510758A (en) * 1993-04-07 1996-04-23 Matsushita Electric Industrial Co., Ltd. Multilayer microstrip wiring board with a semiconductor device mounted thereon via bumps
US5667884A (en) * 1993-04-12 1997-09-16 Bolger; Justin C. Area bonding conductive adhesive preforms
JP3258764B2 (ja) * 1993-06-01 2002-02-18 三菱電機株式会社 樹脂封止型半導体装置の製造方法ならびに外部引出用電極およびその製造方法
US5484648A (en) 1993-08-11 1996-01-16 Shin-Etsu Polymer Co., Ltd. Heat-sealable connector and method for the preparation thereof
US5397921A (en) 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array
JPH0794554A (ja) * 1993-09-24 1995-04-07 Toshiba Corp 半導体装置の実装方法
US5734201A (en) 1993-11-09 1998-03-31 Motorola, Inc. Low profile semiconductor device with like-sized chip and mounting substrate
US5367435A (en) 1993-11-16 1994-11-22 International Business Machines Corporation Electronic package structure and method of making same
US5454160A (en) * 1993-12-03 1995-10-03 Ncr Corporation Apparatus and method for stacking integrated circuit devices
JPH07193184A (ja) * 1993-12-27 1995-07-28 Fujitsu Ltd マルチチップモジュールの製造方法及びマルチチップモジュール
US5578869A (en) * 1994-03-29 1996-11-26 Olin Corporation Components for housing an integrated circuit device
US5474620A (en) 1994-05-16 1995-12-12 United Solar Systems Corporation Cut resistant laminate for the light incident surface of a photovoltaic module
JP3377867B2 (ja) * 1994-08-12 2003-02-17 京セラ株式会社 半導体素子収納用パッケージ
JP2546192B2 (ja) 1994-09-30 1996-10-23 日本電気株式会社 フィルムキャリア半導体装置
US5532512A (en) * 1994-10-03 1996-07-02 General Electric Company Direct stacked and flip chip power semiconductor device structures
US5579573A (en) * 1994-10-11 1996-12-03 Ford Motor Company Method for fabricating an undercoated chip electrically interconnected to a substrate
JP3138159B2 (ja) 1994-11-22 2001-02-26 シャープ株式会社 半導体装置、半導体装置実装体、及び半導体装置の交換方法
US5604445A (en) 1994-12-21 1997-02-18 International Business Machines Corporation Apparatus, and corresponding method, for stress testing semiconductor chips
US5847022A (en) * 1995-03-27 1998-12-08 Dainippon Ink And Chemicals, Inc. Radiation curable resin composition and method therefor
JPH08335653A (ja) 1995-04-07 1996-12-17 Nitto Denko Corp 半導体装置およびその製法並びに上記半導体装置の製造に用いる半導体装置用テープキャリア
US5655703A (en) 1995-05-25 1997-08-12 International Business Machines Corporation Solder hierarchy for chip attachment to substrates
US5674780A (en) * 1995-07-24 1997-10-07 Motorola, Inc. Method of forming an electrically conductive polymer bump over an aluminum electrode
US5674785A (en) 1995-11-27 1997-10-07 Micron Technology, Inc. Method of producing a single piece package for semiconductor die
US5766982A (en) * 1996-03-07 1998-06-16 Micron Technology, Inc. Method and apparatus for underfill of bumped or raised die
US5726502A (en) 1996-04-26 1998-03-10 Motorola, Inc. Bumped semiconductor device with alignment features and method for making the same
US5925930A (en) * 1996-05-21 1999-07-20 Micron Technology, Inc. IC contacts with palladium layer and flexible conductive epoxy bumps
US5709336A (en) * 1996-05-31 1998-01-20 International Business Machines Corporation Method of forming a solderless electrical connection with a wirebond chip
US5813870A (en) * 1996-07-12 1998-09-29 International Business Machines Corporation Selectively filled adhesives for semiconductor chip interconnection and encapsulation
US5789278A (en) * 1996-07-30 1998-08-04 Micron Technology, Inc. Method for fabricating chip modules
US5759737A (en) 1996-09-06 1998-06-02 International Business Machines Corporation Method of making a component carrier
US5801452A (en) 1996-10-25 1998-09-01 Micron Technology, Inc. Multi chip module including semiconductor wafer or dice, interconnect substrate, and alignment member
JP3438859B2 (ja) * 1996-11-21 2003-08-18 ティーディーケイ株式会社 積層型電子部品とその製造方法
US5798050A (en) * 1997-01-10 1998-08-25 International Business Machines Corporation Process for fabrication of a selectively filled flexible adhesive device for solderless connection of electronic modules to a substrate
US5931371A (en) * 1997-01-16 1999-08-03 Ford Motor Company Standoff controlled interconnection
US5814401A (en) * 1997-02-04 1998-09-29 Motorola, Inc. Selectively filled adhesive film containing a fluxing agent
US6016060A (en) 1997-03-25 2000-01-18 Micron Technology, Inc. Method, apparatus and system for testing bumped semiconductor components
US5931685A (en) * 1997-06-02 1999-08-03 Micron Technology, Inc. Interconnect for making temporary electrical connections with bumped semiconductor components
US6040702A (en) 1997-07-03 2000-03-21 Micron Technology, Inc. Carrier and system for testing bumped semiconductor components
US6107122A (en) 1997-08-04 2000-08-22 Micron Technology, Inc. Direct die contact (DDC) semiconductor package
US5977642A (en) 1997-08-25 1999-11-02 International Business Machines Corporation Dendrite interconnect for planarization and method for producing same
US6097087A (en) 1997-10-31 2000-08-01 Micron Technology, Inc. Semiconductor package including flex circuit, interconnects and dense array external contacts
US5861678A (en) * 1997-12-23 1999-01-19 Micron Technology, Inc. Method and system for attaching semiconductor dice to substrates
US6259036B1 (en) 1998-04-13 2001-07-10 Micron Technology, Inc. Method for fabricating electronic assemblies using semi-cured conductive elastomeric bumps
US5990566A (en) 1998-05-20 1999-11-23 Micron Technology, Inc. High density semiconductor package
US6133634A (en) 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
US6189208B1 (en) * 1998-09-11 2001-02-20 Polymer Flip Chip Corp. Flip chip mounting technique
US6194788B1 (en) 1999-03-10 2001-02-27 Alpha Metals, Inc. Flip chip with integrated flux and underfill
US6395124B1 (en) * 1999-07-30 2002-05-28 3M Innovative Properties Company Method of producing a laminated structure
US6744124B1 (en) * 1999-12-10 2004-06-01 Siliconix Incorporated Semiconductor die package including cup-shaped leadframe
US6949822B2 (en) * 2000-03-17 2005-09-27 International Rectifier Corporation Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance
US6391687B1 (en) 2000-10-31 2002-05-21 Fairchild Semiconductor Corporation Column ball grid array package
US6455941B1 (en) * 2001-01-03 2002-09-24 Advanced Semiconductor Engineering, Inc. Chip scale package

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5976953A (en) * 1993-09-30 1999-11-02 Kopin Corporation Three dimensional processor using transferred thin film circuits
US5492863A (en) * 1994-10-19 1996-02-20 Motorola, Inc. Method for forming conductive bumps on a semiconductor device
US5661042A (en) * 1995-08-28 1997-08-26 Motorola, Inc. Process for electrically connecting electrical devices using a conductive anisotropic material
US5940729A (en) * 1996-04-17 1999-08-17 International Business Machines Corp. Method of planarizing a curved substrate and resulting structure
US6168972B1 (en) * 1998-12-22 2001-01-02 Fujitsu Limited Flip chip pre-assembly underfill process
US6245595B1 (en) * 1999-07-22 2001-06-12 National Semiconductor Corporation Techniques for wafer level molding of underfill encapsulant

Also Published As

Publication number Publication date
US6967412B2 (en) 2005-11-22
TW569331B (en) 2004-01-01
US6582990B2 (en) 2003-06-24
US20030207490A1 (en) 2003-11-06
WO2003019628A1 (en) 2003-03-06
EP1428246A4 (en) 2009-08-26
CN1547758A (zh) 2004-11-17
US20030038342A1 (en) 2003-02-27
EP1428246A1 (en) 2004-06-16

Similar Documents

Publication Publication Date Title
CN1327476C (zh) 半导体器件及其制造方法
US6897142B2 (en) Formation of solder balls having resin member as reinforcement
JP3233535B2 (ja) 半導体装置及びその製造方法
US6900079B2 (en) Method for fabricating a chip scale package using wafer level processing
US6576495B1 (en) Microelectronic assembly with pre-disposed fill material and associated method of manufacture
US6454159B1 (en) Method for forming electrical connecting structure
KR100475324B1 (ko) 용융제를함유하는선택적충전형접착막
CN103050462B (zh) 半导体器件封装件及方法
KR20090080623A (ko) 포스트 범프 및 그 형성방법
CN105575924A (zh) 功率模块
US6083819A (en) Method and assembly for providing improved underchip encapsulation
TWI722307B (zh) 具有多層囊封物之半導體裝置及相關系統、裝置及方法
US7169641B2 (en) Semiconductor package with selective underfill and fabrication method therfor
KR20040030659A (ko) 칩 리드 프레임
JP2007066960A (ja) 半導体パッケージ及び回路基板並びに半導体パッケージの製造方法
TWI736072B (zh) 封裝結構與其形成方法
KR20100137183A (ko) 반도체 패키지의 제조 방법 및 이에 의해 제조된 반도체 패키지
JP2000340712A (ja) ポリマ補強カラム・グリッド・アレイ
CN108198794A (zh) 一种芯片封装体及其制备方法
CN103681455B (zh) 管芯底部填充结构和方法
JP2008277594A (ja) 半導体装置、およびその製造方法、並びにその製造方法に用いるリードフレーム
JP2000349230A (ja) 半導体モジュールおよびその製造方法
TW457655B (en) Method of packaging an integrated circuit device
Gilleo Advances in packaging and assembly polymers
JPH06310567A (ja) 半導体装置の実装方法およびその実装構造

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: California, USA

Patentee after: Infineon Technologies Americas Corp.

Address before: California, USA

Patentee before: INTERNATIONAL RECTIFIER Corp.

CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20070718