CN1331492A - 对聚合材料具有增强的附着力的半导体器件保护层及其制造方法 - Google Patents
对聚合材料具有增强的附着力的半导体器件保护层及其制造方法 Download PDFInfo
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Abstract
一种带有低应力的薄膜保护层的集成电路器件,其保护层对用于封装半导体器件的聚合材料和在钝化膜层内都具有增强的附着力,该保护层包括通过PECVD工艺顺序淀积的下列材料:二氧化硅薄膜;氮化硅、氧氮化硅或碳化硅层;以及非常薄的最上面的氧化硅层。
Description
本发明总体上讲是涉及一种半导体器件,更具体地讲是涉及集成电路上的保护层。
通常,集成电路(IC)是在被称作芯片的半导体利底上制造的,并且最普通的衬底是由硅做成的。硅片通常被装配到一个外壳中,外壳用来有效地扩大芯片的输入/输出接点之间的距离或节距,使它适合于附着到印刷电路板上,并且保护IC不受机械的或环境的损坏。不幸的是,用于提供这种保护的外壳有时会带来器件的故障。比如一些容纳超大规模集成电路(VLSI)芯片的表面安装外壳,其中在芯片和模塑料之间的界面上的不良的附着力导致分层。由于被塑料吸附的湿气在分层的界面上蒸汽压力迅速升高,以及外壳焊接到印刷电路板时迅速受热,造成了器件的故障,这些故障表现为外壳破裂、焊线破损以及伴随的其它与应力有关的故障。
与较为典型的在外围将输入和输出(I/O)端子安装到密封在模制塑料外壳中的一个引线框架上的情况相比,近来,半导体工业引入了减小的组件尺寸,比如那些具有区域阵列形式的组件。这些区域阵列组件是芯片尺寸组件(ChipScale Package—CSP)、线接合的或倒装芯片球栅阵列(BGA)组件和直接安装芯片(DCA)组件,芯片尺寸组件(CSP)的一个例子显示在图1中,在直接安装芯片组件中,硅片是不用中间的组件而直接安装到印刷电路板上的。通常这些区域阵列组件具有焊料块或焊料球11,该焊料块或焊料球通过软熔焊料从芯片的输入/输出(I/O)接点连接到基片或印刷电路(PC)板上,从而实现电气和机械连接。因为硅片10和基片或PC板12的材料具有不同的热膨胀系数(CTE),这样,在刚性的、低CTE的芯片与更具顺从性的、高CTE的PC板之间的焊料连接处就引入了应力。由热膨胀失配而引起的应力发生在焊料软熔过程中和/或当供给到IC的电源循环地通断时。这种应力经常会导致一个或更多的焊料接点发生机械故障,并且又引起该产品的电气故障。
为了减少焊料疲劳故障并且将由于热而产生的应力分配到一个大的面积中,引入了液体形式的聚合物填料或“未充满(undefill)”密封剂15,密封剂包围焊料球11并且填充芯片或CSP 10和PC板之间的空腔。该“未充满”密封剂靠近芯片的边缘分散并且在芯片下面、通过毛细管作用围绕着焊料球流动。通过设定紫外线照射的时间、温度或其组合,该“未充满”密封剂凝固成为硬的状态。
该“未充满”方法具有许多缺点,包括但不限于下列缺点:产生于器件下面的气泡或空隙16会导致局部应力集中,引起未充满密封剂对一个或多个表面的不良附着,并且这是一个繁琐和费时的方法。这种未充满的粘性化合物最普通的是带有无机填料的环氧树脂,它被顺序地和慢慢地引入,以防止由于对芯片上的保护层、基片的表面和/或焊料块的不良浸润而在芯片下面形成空隙。
对材料表面之间的附着和不良浸润的后果已经进行了长期研究;已认识到的主要因素是清洁度、表面张力和外形以及粘合物的化学性质。
许多半导体芯片制造商选择的芯片的钝化或保护层(PO)是氮化硅,这主要是因为它显示出对流动的离子和污染物的进入具有很好的阻止作用。然而,氮化硅不能提供用于附着和浸润的活性部位,并且会遭受可能引起破裂和分层的应力水平。应力会因淀积技术不同而变化,并且一致的努力方向是控制应力的大小并提供压缩力,以避免芯片性能和可靠性变劣。
由于用氮化硅保护层的这些缺陷,芯片制造商经常被迫在保护层的上面采用一层构图的聚酰亚胺薄膜。图2a和2b显示出在芯片20上的聚酰亚胺薄膜22。采用聚酰亚胺薄膜22是为了提高对半导体封装时使用的聚合物的附着力,这种聚合物比如在图2b中的常规带引线塑料模制外壳中的模制化合物26,或者提高对其它类型外壳中的未充满或灌注化合物的附着力。聚酰亚胺22被施加在氮化硅或其它薄膜PO(21)上并进行构图。
图2a提供了在保护层21上带有构图的聚酰亚胺薄膜22的芯片20的表面布局的更详细视图。对于附着力,如果聚酰亚胺薄膜厚到足以留下一个光滑、平坦的表面的话,它就可能具有副作用。薄的氮化硅保护层21是沿着芯片电路24的轮廓(来覆盖的),但较厚的聚酰亚胺22会使该轮廓软化,造成一个更平的表面;这样一种平滑的表面不太适合最佳的附着。
此外,聚酰亚胺薄膜的弹性模数高于典型的无机薄膜,具有较高的热膨胀的较厚薄膜确实会在晶片上产生应力,该应力能导致卷绕和/或分层。有机薄膜,比如聚酰亚胺既没有希望的高温稳定性也没有无机薄膜的较高导热性。
聚酰亚胺前体(precursors)是以液体的形式施加到晶片表面上的,该晶片预先已经制备有一种附着力促进剂,或着具有这样一种包含在聚酰亚胺组成成分中的化合物。聚酰亚胺随后必须进行光学构图。聚酰亚胺组成成分可以包含一种允许直接构图的感光剂,如果不含有该感光剂的话,就需要一个单独的光致抗蚀剂(加工)步骤。下一步,该薄膜通过热处理过程被固化或交联。聚酰亚胺不仅是一种昂贵的化合物,而且其处理也费时、费钱,并且可能不利地影响在晶片上形成良好芯片。
相应地,工业上需要一种可靠的芯片保护层,该保护层容易被诸如模制和未充满化合物之类的聚合物浸润,并且对聚合物具有良好附着力,需要一种在芯片电路上只产生很小应力的保护层,以及需要一种在晶片加工方面具有低成本的保护层。
本发明的一个目的就是提供一种可靠且低成本的芯片保护层,该保护层具有良好的层间附着力,并且对集成电路芯片装配所用的聚合材料具有良好的浸润和附着力。
本发明的一个目的是提供一种具有增强的附着力的保护层的制造方法,并且该制造方法利用现有的晶片制造设备和材料。
本发明的另一个目的是提供一种热稳定的芯片保护层,它对芯片上的有源电路和金属化层只产生很小的和可控制的应力。
本发明的一个目的是要提供一种芯片保护层,它具有优异的扩散阻挡特性。
本发明还有一个目的是提供一种无机芯片保护层,它与聚合物涂层相比具有提高的热传导性。
本发明的目的是通过在集成电路器件上设置一个保护层来实现的,该保护层包括下列顺序的材料:一层在有源电路和金属化层上面的氧化硅薄膜,其厚度范围为5000到10000埃;一个氮化硅、氧氮化硅或碳化硅层,其厚度范围是1000到5000埃;以及一个氧化硅的顶部粘合层,其厚度范围是500到5000埃。这个复合(保护)层是在硅晶片上用等离子体增强化学汽相淀积方法通过改变反应器中的气体成分和工艺参数来制造的,但不需要额外的手工操作。在所淀积的保护层中,通过光学构图和蚀刻形成用于输入/输出端子的开孔。
二氧化硅的第一和第三层用来控制由氮化物所带来的应力,以提供优异的介电特性,并允许在保护层的各层之间和对组装半导体器件时所用聚合物都有良好的附着力。氮化硅、碳化硅或氧氮化硅的第二层是阻挡层,用来阻挡移动离子或污染物的进入。
从参照附图对本发明的一个优选实施例所做的详细说明,本发明的上述和其它目的、特征和优点将会变得更加清楚。
图1是带有未充满密封剂的芯片尺寸组件(已有技术)。
图2a显示出在保护层上面具有聚酰亚胺粘合层的芯片表面(已有技术)。
图2b是一个带引线的塑料外壳,它容纳一个带有聚酰亚胺涂层的半导体器件(已有技术)。
图3显示出本发明的连续的保护层。
图4显示出本发明的具有增强的附着力的保护层的工艺流程。
图5是在PO和未充满材料之间具有增强的附着力的倒装芯片组装图。
图6本发明的模制成型的半导体器件。
附图详细说明
图3显示出一个半导体芯片30的一部分的剖面图,该芯片具有一个本发明的保护层结构31。许多新的特征提供了可靠的和高性能的器件,该器件在保护层的多层电介质之间以及对封装芯片所用的聚合材料都具有良好的附着力。在图3中,包括金属互连线34和埋置结构35的器件电路被一个钝化或保护层(PO)31所覆盖,该保护层31包括连续形成的下列薄膜层:二氧化硅薄膜311;硅化合物的第二电介质层312,硅化合物最好是氮化硅或者氧氮化硅或碳化硅;以及非常薄的最后或最顶层的二氧化硅层313。这些层被构图形成有外部接触或其它器件要求所需的开孔(未显示)。
电介质材料层通常用来提供导电层之间的电绝缘,并且用来保护集成电路的下面结构不被污染。此外,即使当其中任一层被损坏时,例如,由于形成了小裂缝,连续层的设置也能确保对器件的保护。因此,重要的是不允许存在其与覆盖层之间的附着力小于正常附着力的区域。
第一层311是厚度在5000到10000埃范围的二氧化硅。术语二氧化硅指的是一种不严格化学计量的二氧化硅,即,Si[x]O[2-x]。该层用来减轻氮化硅或该保护层结构31的第二层的应力,并且给器件电路提供优异的电介质钝化。二氧化硅作为第一层311和第三层313提供了对中间或阻挡层312的附着力。另外,第一二氧化硅层在电路或芯片的金属化层上几乎不产生张应力,并且用于减弱从氮化硅层到下面电路的应力。
在一个优选实施例中,一个氮化硅或阻挡层312提供了优异的保护来防止移动离子、湿气或其它污染物的进入,该层与氧化层311、313组合相当于现有技术的较厚的氮化物保护层。在本发明中,1000到5000埃的厚度对阻挡或第二层来说就足够了。
在第二实施例中,该保护层的第二层312是氧氮化硅,而在第三实施例中,第二层是碳化硅。在需要选择的透光性的特定器件类型中,优选氧氮化物。众所周知,碳化硅具有非常高的热导率,它作为一个PO层用来在芯片的表面上扩散由电路所产生的局部热量,并且提供一种途径将热量从电路传递到外部。已经研发出用于形成具有优良的阻挡特性的碳化硅薄膜的技术,并且应力可通过淀积参数很容易地控制。
选择作为第二或阻挡层的硅化合物不仅仅是指按照化学计量的成分,而是指主要包含所述化合物的混合物以及业内所理解的混合物。
对于保护层与聚合材料的附着力而言,第三个或最顶部的氧化层是关键的。只需要500到5000埃范围的非常薄的氧化物薄膜,就可以提供用于附着到下面的氮化物的活性部位,并且提供一个暴露的表面,该表面具有低的表面张力和用于浸润和附着到聚合物以及硅的氧化物上的活性部位,聚合物例如用于未充满化合物和塑料模制化合物中的环氧树脂。硅的氧化物,例如Si-Ox、Si-OH,以及各种形式的硅烷反应产物是本领域的普通技术人员熟知的,它们可作为比如用于未充满化合物或塑料模制化合物中的环氧树脂之类的聚合物的附着力促进剂。(美国专利5795821和美国专利5418189)。
如前面所指出的,材料之间的浸润和附着的控制因素是清洁度、表面张力和外形以及粘合物的化学性质。
从图3中可注意到,具有增强附着力的保护层31的薄膜是沿着下面的电路结构的外形(分布的),从而提供了一个具有不规则构形的暴露表面。早已知道:与光滑、平坦的表面不同,通过粗糙或有纹理的表面可增强附着力。
附着力增强的保护层的一个显著优点在于与工业上使用的公知晶片加工技术和自动化技术的兼容性。图4a到4d显示出制造如图3中所示的保护层31的步骤。在图4a中,一个硅晶片40被设置在一个等离子体增强的化学汽相淀积(反应)室中,硅晶片40具有构图的集成电路44并且包括最上面的金属互连层45。使用由箭头401所指示的标准PETEOS(等离子体增强的四乙基原硅酸盐)工艺,淀积厚度在5000到10000埃范围的一个氧化物薄膜411。在图4b的更详细的示意图中,气体源被改变为包括硅烷和氮和/或氨,以便使用由箭头402所指示的PECVD工艺来淀积1000到5000埃厚的一个氮化硅薄膜412。去除氮气源,并且在图4c中使用标准的PETEOS工艺401来增加一个最后的氧化物薄膜413。将晶片从反应室中取出,施加光致抗蚀剂403并且进行光学构图,从而暴露结合区48和/或器件所需的其它开孔。该图形优选使用气体干蚀刻工艺404来蚀刻,以从结合区和器件上的其它开孔处去除保护层。或者,使用缓冲氢氟酸的湿蚀刻来蚀刻PO。
对于第二个实施例的制造方法,一种具有二氧化硅、氧氮化硅和二氧化硅组成的保护层的器件与上述(第一个实施例的制造方法)的不同在于:在淀积第二层的过程中,与氮气、硅烷和氨一起引入了氧气。氧氮化硅的工艺是公知的并在工业上普遍应用,特别是对于E—PROM器件。该保护层的第一和第三层的工艺与上述(第一个实施例的制造方法)相同。
包括二氧化硅、碳化硅和二氧化硅组成的一个层的第三个实施例的保护层的制造,与第一个实施例的不同在于:对于碳化硅的第二层,硅烷/甲烷、三甲基硅烷、四甲基硅烷或其它有机硅烷气体是原料气体,同时以Ar或He作为载运气体。同样,第一和第三层是使用PETEOS工艺形成的二氧化硅。
每一淀积和构图工艺都是半导体工业中公知的,并且设备也是广泛使用的。这种组合的连续工艺形成了一种独特的PO结构,该结构对IC组件装配中所用的聚合物具有增强的附着力,在薄膜层之间具有良好附着力,并且在电路上具有最小应力,从而提供结实的、缺陷少的芯片钝化。
通过在单个反应室中按顺序淀积多层薄膜,连续的保护层的等离子增强化学汽相淀积(PECVD)去除了多余的晶片手工操作。通过在加工室内的气氛控制,使用等离子增强化学汽相淀积的工艺在层之间提供了清洁、无污染的表面,因此有利于多层之间的附着。另外,通过不用手工操作的连续淀积以及通过单个光学构图步骤来蚀刻开孔,PECVD优化了工艺循环时间。
本发明完全无机化的保护层不仅提供了对封装聚合物具有增强附着力的器件性能优点,而且还具有超过了450℃的很高温度稳定性,并且与现有的增强表面附着力PO技术相比提高了导热性。特别是,具有碳化硅的第二或阻挡层的本实施例提供了良好的热传导性,并且可适用于大功率电路。
图5显示出本发明的倒装芯片的装配。一个集成电路器件50具有二氧化硅511、氮化硅512和二氧化硅513的连续淀积的保护层,该器件50使用焊料球51附着到一个衬底52上。一种聚合的未充满化合物55完全浸润到保护层的氧化物表面513上,在未充满(化合物)中防止了由于不良附着而产生的空隙。
图6以带引线的塑料模制外壳的剖面图显示出另一实施例,其中,本发明的多层保护层61对模制化合物65具有增强的附着力。该附着力在芯片69的角部尤其有益,因为在此处塑料的分层会引起芯片金属结构的切断和/或接合线的疲劳。
尽管已结合几个优选实施例说明了本发明,但并非要将本发明的范围限制于所说明的具体形式,相反,而是要涵盖包括在所附权利要求限定的本发明的精神和范围内的多种替换、更改和等同物。
Claims (17)
1.一种具有增强附着力的保护层的集成电路,所述保护层包括下列薄膜层:
二氧化硅的第一层,
硅化合物的第二层,该硅化合物选自由氮化硅、碳化硅或氧氮化硅组成的一组化合物,
以及第三层,它包含一个非常薄的二氧化硅薄膜。
2.根据权利要求1的集成电路,其中,所述第一层的厚度范围是5000到10000埃。
3.根据权利要求1的集成电路,其中,所述第二层的厚度范围是1000到5000埃。
4.根据权利要求1的集成电路,其中,所述第三层的厚度范围是500到5000埃。
5.根据权利要求1的集成电路,其中,所述的层是通过等离子体增强化学汽相淀积方法来淀积的。
6.根据权利要求1的集成电路,其中,所述第三层对聚合材料具有很强的附着力。
7.根据权利要求1的集成电路,其中,所述保护层的热稳定温度高于450℃。
8.根据权利要求1的集成电路,其中,所述保护层是一个阻挡层,用来阻挡湿气、移动离子和其它污染物的进入。
9.根据权利要求1的集成电路,其中,所述第一和第三氧化物层对所述第二电介质层具有很强的附着力。
10.一种钝化膜,包括下列薄膜层:
二氧化硅的第一层,
硅化合物的第二层,该硅化合物选自由氮化硅、碳化硅或氧氮化硅组成的一组化合物。
11.一种倒装芯片半导体器件,它具有一个保护层,保护层对聚合材料具有增强的附着力,该器件包括下列层:
集成电路,它具有带有有源电路和互连线的第一表面,
淀积在所述第一表面上面并构图的保护层,它包括:一个二氧化硅层;包含硅化合物的第二电介质层,该硅化合物选自由氮化硅、碳化硅或氧氮化硅组成的一组化合物;以及一个薄的二氧化硅层,
未充满聚合物,以及
带有焊料球接点的衬底。
12.根据权利要求11的半导体器件,其中,所述器件是BGA组件。
13.根据权利要求11的半导体器件,其中,所述器件是CSP。
14.一种带引线的表面安装半导体器件,它具有一个保护层,保护层对聚合材料有增强的附着力,该器件包括:
集成电路,具有带有有源电路和互连线的第一表面以及安装到一个引线框架的第二表面,
淀积在所述第一表面上面并构图的保护层,所述保护层包括:一个二氧化硅层;包含硅化合物的第二电介质层,该硅化合物选自由氮化硅、碳化硅或氧氮化硅组成的一组化合物;以及薄的二氧化硅的第三层,
接合线,用于将芯片上的结合区连接到该引线框架,以及
包括环氧聚合物的模制化合物,用于封装具有增强附着力的保护层的所述集成电路芯片、接合线和引线框架的内部引线。
15.一种制造具有保护层的半导体器件的方法,所述保护层对用于封装的聚合材料和在所述保护层的各层之间都具有增强的附着力,这种方法包括下列步骤:
将一个或多个包括制备的集成电路的半导体晶片设置到一个等离子体淀积反应器中,
在使用PETEOS(等离子体增强四乙基原硅酸盐)工艺淀积二氧化硅层之前先抽空该(反应)室,
将所供气体改变为包括硅烷、氮气和氨,使用PEVCD(等离子体增强化学汽相淀积)工艺来淀积氮化硅层,
改变所供气体,以使用PETEOS工艺来淀积薄的二氧化硅层,
施加光致抗蚀剂,对结合区和/或其它开孔进行光学构图,并且使用干蚀刻工艺来蚀刻保护层中的开孔。
16.一种制造具有保护层的半导体器件的方法,所述保护层对用于封装的聚合材料和在所述保护层的各层之间都具有增强的附着力,这种方法包括下列步骤:
将一个或多个具有制备的集成电路的半导体晶片设置到一个等离子体淀积反应器中,
在使用PETEOS(等离子体增强四乙基原硅酸盐)工艺淀积二氧化硅层之前先抽空该(反应)室,
将所供气体改变为包括硅烷、氮气、氧气和氨,使用PEVCD(等离子体增强化学汽相淀积)工艺来淀积氧氮化硅层,
改变所供气体,以使用PETEOS工艺来淀积薄的二氧化硅层,
施加光致抗蚀剂,对结合区和/或其它开孔进行光学构图,并且使用干蚀刻工艺来蚀刻保护层中的开孔。
17.一种制造具有保护层的半导体器件的方法,所述保护层对用于封装的聚合材料和在所述保护层的各层之间都具有增强的附着力,这种方法包括下列步骤:
在使用PETEOS(等离子体增强四乙基原硅酸盐)工艺淀积二氧化硅层之前先抽空该(反应)室,
将所供气体改变为包括硅烷/甲烷或诸如三甲基硅烷或四甲基硅烷之类的有机硅烷,使用PEVCD(等离子体增强化学汽相淀积)工艺来淀积碳化硅层,
改变所供气体,以使用PETEOS工艺来淀积薄的二氧化硅层,
施加光致抗蚀剂,对结合区和/或其它开孔进行光学构图,并且使用干蚀刻工艺来蚀刻保护层中的开孔。
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-
2001
- 2001-06-02 US US09/873,058 patent/US6580170B2/en not_active Expired - Lifetime
- 2001-06-13 CN CN01123308A patent/CN1331492A/zh active Pending
- 2001-06-21 KR KR1020010035383A patent/KR20020002446A/ko not_active Application Discontinuation
- 2001-06-22 TW TW090115185A patent/TW502377B/zh not_active IP Right Cessation
- 2001-06-22 JP JP2001189162A patent/JP2002075981A/ja not_active Abandoned
- 2001-06-22 EP EP01202417A patent/EP1168437A3/en not_active Withdrawn
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2003
- 2003-04-29 US US10/426,451 patent/US6787397B2/en not_active Expired - Lifetime
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CN100442459C (zh) * | 2005-11-24 | 2008-12-10 | 上海华虹Nec电子有限公司 | 自对准硅化物阻挡层的制作工艺方法 |
CN104616669A (zh) * | 2006-04-10 | 2015-05-13 | 希捷科技有限公司 | 用于保护外涂层的粘合层 |
CN110997975A (zh) * | 2017-07-14 | 2020-04-10 | 英飞康有限责任公司 | 从部件的表面受控地除去保护层的方法 |
CN110212071A (zh) * | 2019-05-22 | 2019-09-06 | 华灿光电(浙江)有限公司 | 发光二极管芯片及其制作方法 |
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KR20020002446A (ko) | 2002-01-09 |
US20020011656A1 (en) | 2002-01-31 |
US6787397B2 (en) | 2004-09-07 |
EP1168437A2 (en) | 2002-01-02 |
EP1168437A3 (en) | 2006-03-22 |
US20030205812A1 (en) | 2003-11-06 |
US6580170B2 (en) | 2003-06-17 |
JP2002075981A (ja) | 2002-03-15 |
TW502377B (en) | 2002-09-11 |
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