CN1332440C - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN1332440C
CN1332440C CNB2004100880277A CN200410088027A CN1332440C CN 1332440 C CN1332440 C CN 1332440C CN B2004100880277 A CNB2004100880277 A CN B2004100880277A CN 200410088027 A CN200410088027 A CN 200410088027A CN 1332440 C CN1332440 C CN 1332440C
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China
Prior art keywords
substrate
electrode
impedance matching
semiconductor device
semiconductor element
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Expired - Fee Related
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CNB2004100880277A
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CN1705102A (zh
Inventor
十和人
久保田义浩
浅田宪治
细山田澄和
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Socionext Inc
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Fujitsu Ltd
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    • H01L2924/3025—Electromagnetic shielding

Abstract

在一种半导体器件中，在减少接合线长度的同时，当将高密度半导体元件安装于低成本的衬底上时，接合线能够彼此平行地应用于高速信号线路的电极。在衬底(2)上安装阻抗匹配衬底(6)，其具有与半导体元件(4)的电路阻抗匹配的布线。多条第一金属线(12)连接于半导体元件(2)的第一电极(4a)与衬底的电极(2a)之间。多条第二金属线(14)连接于半导体元件(2)的第二电极(4b)与阻抗匹配衬底(6)的第一电极(6a)之间。多条第三金属线(16)连接于阻抗匹配衬底(6)的第二电极(6b)与衬底(2)的电极(2a)之间。第二金属线(14)彼此平行地延伸，并且第三金属线(16)也彼此平行地延伸。

Description

半导体器件
技术领域
本发明涉及半导体器件，特别地涉及这样的一种半导体器件，在该半导体器件中，半导体元件通过接合线(wire-bonding)安装于衬底上。
背景技术
近年来，高密度的半导体元件已得到发展，这使得半导体元件上形成的电极端子的节距减少。另外，输入和输出信号的处理速度已有所提高，这在许多情况下能够提供用于输入和输出高频信号的电极端子。
与用于输出和输入高频信号的电极端子相连的高频信号线路需要与外围电路和布线获得阻抗匹配。一般地，差模对(differential pair)由两个高频线路形成，并且该差模对位于屏蔽线路比如接地线路、电源线路等之间。
一般地，在半导体器件中，半导体元件的电极沿着半导体元件的外围(每边)来排列，并且半导体元件通过接合线安装于衬底上并且电连接于衬底。这样构造的半导体器件能够利用先前确立的技术来制造，因而能够以相对低的成本来制造。
例如，日本公开专利申请号6-6151公开一种具有上述结构的半导体器件。
如果如同半导体元件制造技术的高密度技术被用来制造其上安装有半导体元件的衬底，则会增加衬底的制造成本。为此，一般地，衬底是利用一种制造与半导体元件相比而言的低密度结构的技术来制造的。这样的衬底被称作低成本的衬底。
在低成本的衬底上形成高密度布线是困难的，这会增加衬底的面积(大小)。然而，由于半导体器件的成本能够通过利用低成本的衬底得以减少，所以低成本的衬底被广泛地使用。由于半导体元件的高密度，半导体元件的电极节距已变得比低成本衬底的端子节距要小得多。
因此，在排列于半导体元件外围部分的电极被线接合于衬底的端子情况下，该线的接合是在衬底的端子上进行的，同时逐步增大了相邻接合线之间的间隔。
另外，使得衬底的端子远离半导体元件，这导致每条接合线的长度增加。
如果这样的高密度半导体元件安装在低成本的衬底上，则接合线彼此不平行，而是逐渐地展开。特别是在高速信号线路由差模对构成的情况下，接合线的长度会增加，这导致无法提供适当的阻抗(例如100Ω)的情况。
此外，由于接合线被拉长，所以出现的问题是利用在低成本衬底中形成的布线难以获得接合线的阻抗匹配。尽管通过利用精细结构在衬底中形成布线，也能够在衬底内获得阻抗匹配，但是仅在一部分的低成本衬底中形成精细结构是不可取的。
发明内容
本发明的总的目的是提供一种改进并且有用的半导体器件，上述问题在该半导体器件中被消除。
本发明的更具体目的是提供一种半导体器件，在该半导体器件中，在减少接合线的长度的同时，当将高密度的半导体元件安装到低成本的衬底上时，接合线能够彼此平行地被应用于高速信号线路的电极。
为了实现上述目的，按照本发明提供一种半导体器件，包括：基础衬底；安装于基础衬底上的半导体元件；阻抗匹配衬底，具有与半导体元件的电路阻抗匹配的布线；多条第一金属线，连接于半导体元件的第一电极与基础衬底的电极之间；多条第二金属线，连接于半导体元件的第二电极与阻抗匹配衬底的第一电极之间；以及多条第三金属线，连接于阻抗匹配衬底的第二电极与基础衬底的电极之间，其中第二金属线彼此平行地延伸，并且第三金属线也彼此平行地延伸。
在按照本发明的半导体器件中，阻抗匹配衬底的第二电极的节距可大于阻抗匹配衬底的第一电极的节距。阻抗匹配衬底的第一电极的节距可等于半导体元件的第二电极的节距。从半导体元件的第一电极延伸到基础衬底的电极的相邻第一金属线之间的距离可朝着基础衬底的电极逐渐地增加。阻抗匹配衬底的厚度可小于半导体元件的厚度。阻抗匹配衬底的厚度等于半导体元件的厚度的一半。
此外，在按照本发明的半导体器件中，阻抗匹配衬底在设置阻抗匹配衬底的第二电极的位置具有槽口，并且第三金属线可通过延伸经过槽口的内表面所包围的区域而连接于基础衬底的电极。阻抗匹配衬底可由导电材料形成，并且槽口的内表面可由该导电材料的露出表面来限定。可通过导电材料来电镀槽口的内表面。
此外，在按照本发明的半导体器件中，凸起电极可形成于阻抗匹配衬底的第一电极上，并且第二金属线可接合于凸起电极。第二金属线的第一端(side)可接合于半导体元件的第二电极，并且第二金属线的第二端可接合于凸起电极。
此外，在按照本发明的半导体器件中，多条第一金属线的一部分可通过在阻抗匹配衬底上方延伸而连接于基础衬底的电极。
此外，在按照本发明的半导体器件中，设定为电源电势或接地电势的屏蔽布线或屏蔽平面被设置于阻抗匹配衬底的阻抗匹配布线的相对两侧上。阻抗匹配衬底可由导电材料形成，并且屏蔽布线或屏蔽平面可形成为阻抗匹配衬底的一部分。
此外，在按照本发明的半导体器件中，阻抗匹配衬底可具有三角形状，并且该三角形状的一边设置为邻近于和平行于半导体元件的一边。
按照上述发明，需要阻抗匹配的布线路径被形成于阻抗匹配衬底上，以获得具有高精确性的阻抗匹配，同时具有相对低精确性的阻抗匹配被应用于其他布线路径。因此，当安装具有精细节距的半导体元件时，使用具有相对粗糙衬底结构的衬底，并且仅对于需要阻抗匹配的高速线路使用阻抗匹配衬底，由此无需使整个衬底具有精细的结构。因此，即使在安装具有精细电极节距的半导体元件时，仍可使用相对廉价的衬底，这可降低半导体器件的制造成本。
从结合附图阅读如下具体的描述中，本发明的其他目的、特征和优点将变得更为明显。
附图说明
图1是按照本发明第一实施例的BGA型半导体器件的透明侧视图；
图2是图1中所示半导体器件的透明平面图；
图3是图1中所示半导体器件内部的平面图，其表示应用接合线的方法；
图4是阻抗匹配衬底和半导体衬底的透视图；
图5是阻抗匹配衬底和半导体衬底的透视图；
图6是一部分半导体器件的侧视图，其中在半导体元件与阻抗匹配衬底之间应用接合线；
图7是阻抗匹配衬底的平面图，该阻抗匹配衬底设有形成差模对的信号线路；
图8是设有槽口的阻抗匹配衬底的平面图；
图9是图1中所示半导体器件的透明平面图；
图10是图9中所示半导体器件内部的平面图，其表示应用接合线的方法；
图11是图10中所示阻抗匹配衬底变化的平面图；
图12是半导体器件内部的平面图，其中，两个图10中所示的阻抗匹配衬底设置于一个半导体元件。
具体实施方式
现在将图1至3，给出按照本发明第一实施例的半导体器件的描述。图1是按照本发明第一实施例的球栅(ball-grid)阵列(BGA)型半导体器件的内部透明侧视图。图2是图1中所示半导体器件的透明平面图。图3是表示图1中所示半导体器件的接合线结构的平面图。
按照本发明第一实施例的半导体器件包括：衬底2；安装于衬底2上的半导体元件4；以及安装于衬底2上的阻抗匹配衬底6。半导体元件4和阻抗匹配衬底6被线接合于衬底2的电极2a(参见图3)，并且它们被衬底2上的密封树脂8完全地封装。设置于衬底2背部的是起外部连接端子作用的焊球10。
电极(第一电极)4a沿着半导体元件4的四个边排列，并且电极4a的节距是精细的节距。另一方面，衬底2是低成本的衬底，并且电极的节距大于半导体元件4的电极节距。因此，将半导体元件4的电极4a连接于衬底2的电极2a的接合线(第一金属线)12中相邻线之间的距离从半导体4这侧到衬底2这侧逐渐地增加，如图2所示。
除具有通过接合线12而连接于衬底2的电极2a的电极(第一电极)4a之外，半导体器件4还具有例如对应于高速信号线路的电极(第二电极)4b。电极4b经过接合线(第二金属线)14，连接于阻抗匹配衬底6上所形成的电极6b。特别地，高速信号线路的阻抗需要相对于半导体元件4的内部布线到衬底2的布线之间的路径来调整。当按照接合线12的连接而获得高速线路时，由于接合线12很长，难以获得适当的阻抗(例如100Ω)。因此，在本实施例中，在阻抗匹配衬底6中预先形成布线，以获得预定阻抗(参见图4)。
阻抗匹配衬底6被设置于靠近电极4b对应于半导体元件4的高速线路14的部分。也就是说，一般具有四边形状的阻抗匹配衬底6的一边被放置为靠近半导体元件4的一边(设置高速信号线路的电极的边)。与半导体元件4的高速信号线路相对应的电极4b经过接合线14而连接于阻抗匹配衬底6的电极(第一电极)6a。
通过接合线14而连接的阻抗匹配衬底6的电极6a的节距被设定为等于半导体元件4的电极4b的节距，以便使接合线14彼此平行地延伸。而且，由于阻抗匹配衬底6被放置为靠近半导体元件4，所以接合线14能够比接合线12短得多，这能够最小化接合线12的阻抗。
阻抗匹配衬底6的电极6a(沿着正对半导体元件4的一边而排列)经过阻抗匹配衬底6上所形成的布线而连接于电极(第二电极)6b(沿着阻抗匹配衬底6的其他三边而设置)。沿着阻抗匹配衬底6的其他三边而设置的电极6b以与衬底的电极2a的节距相等的电极节距来排列。因此，阻抗匹配衬底6的电极6b通过彼此平行的接合线(第三金属线)16而连接于衬底2的电极2a。
现在将参照图4，给出阻抗匹配衬底6的描述。图4是阻抗匹配衬底6和半导体元件4的透视图，其中示出衬底上所形成的线6c。
阻抗匹配衬底6可以是由比如有机衬底、玻璃衬底或金属衬底等材料制成的任何衬底，只要该衬底比半导体元件4薄，并且其上可形成布线。在本实施例中，将给出利用铜衬底的情况的描述。当利用由导电材料形成的衬底比如铜衬底时，该衬底除布线之外的部分可处于电源电势或接地电势。而且，当将铜衬底设定于接地电势时，没有必要特别地提供用于接合线的电极作为接地线路，并且接合线可直接地接合到衬底上。此外，形成于阻抗匹配衬底6上的电极可形成为一部分的图案布线(pattern wiring)，并且无需将这些电极从该图案布线分离。
当通过铜衬底形成阻抗匹配衬底6时，首先，将稍微大于图案线6c的绝缘层6d形成于铜衬底上，然后，将图案线6c形成于绝缘层6d上。每条图案线6c的一端(对应于电极6a)位于正对半导体元件4的一边附近，并且相对端(对应于电极6b)位于其他三边附近。
每条图案线6c形成有预定长度和宽度，以具有期望阻抗(例如100Ω)。可使得图案线的阻抗小于接合线的阻抗，并且能够以更高的精确性设定图案线的阻抗为期望值。因此，半导体元件4的电极4b可经过具有比接合线12更高精确性的阻抗而与衬底2的电极2b连接。应当注意，接合线14和接合线16都比接合线12充分地短，这对阻抗影响更小。
而且，阻抗匹配衬底6中未设置图案线的表面部分被设定为电源电势或接地电势，以起到屏蔽布线或屏蔽平面的作用。
而且，如图1所示，阻抗匹配衬底6的厚度优选地等于或小于半导体元件4的厚度。这是因为如果阻抗匹配衬底6的厚度大于半导体元件4的厚度，则接合线14和接合线16的长度总和变得过大。而且，更优选地，阻抗匹配衬底6的厚度是半导体元件4的厚度的一半。在这种情况下，接合线14和接合线16所接合到的接合表面之间的高度差(半导体元件的表面与阻抗匹配衬底6的表面之间的高度差，以及阻抗匹配衬底6的表面与衬底2的表面之间的高度差)变得彼此相等，这提供了这样的优点，该接合可通过相同的线接合装置来进行。
现在将参照图5，给出阻抗匹配衬底6的变化的描述。图5中所示阻抗匹配衬底6A在设置电极6b的部分设有槽口6Aa。槽口6Aa所露出的衬底2的表面设有电极2a(图中未示出)，并且电极6b连接于电极2a。因此，接合线16在槽口6Aa的内侧上延伸。
阻抗匹配衬底6A是铜衬底，并且每个槽口6Aa的内侧在三个方向上被铜表面围绕，这是接合线16被每个槽口6Aa的内表面屏蔽的状态。因此，可通过将噪声易于进入到的接合线16屏蔽来获得降噪效果。当阻抗匹配衬底6A由相似于铜衬底的导电材料之外的材料形成时，可通过在槽口内表面电镀导电材料比如铜电镀来获得相同的屏蔽效果。
现在将给出从半导体元件4的电极4b到阻抗匹配衬底6或6A的电极6a的接合线优选实施例的描述。
接合线14连接于半导体元件4的电极4b与阻抗匹配衬底6或6A的电极6a之间。一般地，作为接合方法，半导体元件4的电极4b被设定为接合的主侧，位于比电极4a更低位置处的阻抗匹配衬底6或6A的电极6a被设定为接合的辅侧。如图6所示，在接合的主侧上，形成于线末端处的球部被接合。由于球的大小可变得小于半导体元件的电极4b的节距，所以主侧上的接合部分对于接合线不会造成影响。
然而，在接合的辅侧上，该线在被按压于电极6a的同时被撕开。因此，存在这样的可能，变形的线在左右方向上展开，并且延伸到相邻电极6a。也就是说，由于被称作鱼尾(fish tail)的部分形成于接合的辅侧上，所以电极6a的间隔必须考虑到鱼尾而有所增加。在本实施例中，阻抗匹配衬底6或6A的电极6a的节距可变得等于半导体元件4的电极4b的节距，以使得接合线14彼此平行，并且无需减少电极6a的间隔。因此，优选地在每个电极6a上形成凸起电极18，如图6所示，从而该鱼尾不会从凸起电极18的顶表面突出。凸起电极18例如可利用柱头螺栓块、电镀块等形成。
现在将给出阻抗匹配衬底6所连接的信号线路是差模对的情况的描述。图7是阻抗匹配衬底6B的平面图，该衬底设有起差模对作用的信号线。尽管阻抗匹配衬底6B具有与阻抗匹配衬底6相同的基本结构，但是其每两条图案线6c形成为配成一对，并且配对的两条图案线6c形成有相同的宽度和长度。一对图案线6c对应于信号线，并且连接于图案线6c的接合线14和16分配有符号S。另一方面，符号G分配给用作接地布线的接合线14和16。
如图7所示，连接于一对图案线6c的一对接合线14和16(即分配有符号S的线)被插置于起到接地线作用的接合线14和16之间，以被该接合线14和16屏蔽。应当注意，铜衬底用于本实施例中，因而没有为起到接地线作用的接合线14和16设置电极，并且起到接地线作用的接合线14和16被直接地接合于铜衬底。因此，该铜衬底本身被设定为接地电势。
应当注意，在图7中，各上、下对的图案线中的缠绕图案线6c设有缠绕部分，使得缠绕图案线6c的长度等于该对的另一图案线6c的长度。
图5中所示槽口可设置于图7中所示阻抗匹配衬底6C。图8是表示设有槽口6Ca的阻抗匹配衬底6C的平面图。槽口6Ca提供与图5中所示阻抗匹配衬底6A的槽口6Aa相同的效果。而且，用于信号布线的接合线16(即分配有符号S的线)被插置于槽口6Ca的内表面之间，并且无需提供用于接地布线的接合线。
将参照图9和10，给出本发明第二实施例的描述。图9是按照本发明第二实施例的半导体器件的透明平面图。图10是表示图9中所示半导体器件中接合结构的平面图。应当注意，在图9和10中，与图1至图3中所示部分相同的部分分配有相同的标号，并且将省略其描述。
按照本发明第二实施例的半导体器件的结构与按照上述第一实施例的半导体器件相同，不同之处在于阻抗匹配衬底6D具有三角形状。也就是说，如图9所示，按照第二实施例的半导体器件具有三角形状，其一边位于靠近半导体元件4的一边。在这种情况下，如图10所示，与半导体元件的电极4b相连接的电极6a沿着正对阻抗匹配衬底6D的半导体元件4的一边来设置，并且与衬底2的电极2a相连接的电极6b沿着阻抗匹配衬底6D的其他两边来设置。
通过使阻抗匹配衬底成为三角形状，从阻抗匹配衬底6D延伸的接合线16能够在与半导体元件4分离的方向上伸展。因此，阻抗匹配衬底6D中的布线路径能够成为平滑路径，并且在从阻抗匹配衬底6D延伸之后、与衬底2中布线的连接能够变得平滑。
应当注意，由于阻抗匹配衬底6D比半导体元件4更薄，如图10所示，所以将半导体元件4的电极4a连接到衬底2的电极2a的接合线12能够伸展以穿过阻抗匹配衬底6D上方。由此，设置接合线的自由程度有所增加，衬底2的电极2a位置的自由程度也能够有所增加。
图11是图10中所示阻抗衬底6D的变化的平面图。图11中所示阻抗匹配衬底6E具有这样的形状，其中的三角形的角被截去。当阻抗匹配衬底变成如图10所示的三角形时，三角形角的部分无法设置布线，它们是没有用的部分。为此，三角形的角被截去，与阻抗匹配衬底6E相似，以最小化阻抗匹配衬底。
如上所述，该阻抗匹配衬底不限于三角形状或四边形状，而可以是多边形或角被截去的多边形状。而且，除具有直边的形状之外，还可使用具有弓形侧边的形状。
图12是两个图10中所示阻抗匹配衬底6D相对于一个半导体元件4来设置的实例中所示的平面图。当半导体元件具有需要阻抗匹配的许多信号线路时，会出现单个阻抗匹配衬底不够使用的情况。按照本发明的阻抗匹配衬底不限于相对于单个半导体元件的一个衬底，并且多个阻抗匹配衬底可相对于单个半导体元件来设置。
本发明不限于具体公开的实施例，并且不背离本发明的范围，可做出各种变化和改型。

Claims (15)

1.一种半导体器件，包括：
基础衬底；以及
安装于该基础衬底上的半导体元件；
其特征在于：
阻抗匹配衬底安装于该基础衬底上，该阻抗匹配衬底具有与该半导体元件的电路阻抗匹配的布线；
多条第一金属线连接于所述半导体元件的第一电极与所述基础衬底的电极之间；
多条第二金属线连接于所述半导体元件的第二电极与所述阻抗匹配衬底的第一电极之间；
多条第三金属线连接于所述阻抗匹配衬底的第二电极与所述基础衬底的电极之间；以及
所述第二金属线彼此平行地延伸，并且所述第三金属线也彼此平行地延伸。
2.如权利要求1所述的半导体器件，其中所述阻抗匹配衬底的第二电极的节距大于所述阻抗匹配衬底的第一电极的节距。
3.如权利要求1所述的半导体器件，其中所述阻抗匹配衬底的第一电极的节距等于所述半导体元件的第二电极的节距。
4.如权利要求1所述的半导体器件，其中从所述半导体元件的第一电极延伸到所述基础衬底的电极的所述第一金属线的相邻金属线之间的距离朝着所述基础衬底的电极逐渐地增加。
5.如权利要求1所述的半导体器件，其中所述阻抗匹配衬底的厚度小于所述半导体元件的厚度。
6.如权利要求5所述的半导体器件，其中所述阻抗匹配衬底的厚度等于所述半导体元件的厚度的一半。
7.如权利要求1所述的半导体器件，其中所述阻抗匹配衬底在设置所述阻抗匹配衬底的第二电极的位置处具有槽口，并且所述第三金属线延伸穿过所述槽口的内表面所包围的区域而连接于所述基础衬底的电极。
8.如权利要求7所述的半导体器件，其中所述阻抗匹配衬底由导电材料形成，并且所述槽口的内表面由该导电材料的露出表面来限定。
9.如权利要求7所述的半导体器件，其中通过导电材料来电镀所述槽口的内表面。
10.如权利要求1所述的半导体器件，其中凸起电极形成于所述阻抗匹配衬底的第一电极上，并且所述第二金属线接合于所述凸起电极。
11.如权利要求10所述的半导体器件，其中所述第二金属线的第一端接合于所述半导体元件的第二电极，并且所述第二金属线的第二端接合于所述凸起电极。
12.如权利要求1所述的半导体器件，其中所述多条第一金属线的一部分通过在所述阻抗匹配衬底上方延伸而连接于所述基础衬底的所述电极。
13.如权利要求1所述的半导体器件，其中设定为电源电势或接地电势的屏蔽布线或屏蔽平面被设置于所述阻抗匹配衬底的阻抗匹配布线的相对两侧上。
14.如权利要求13所述的半导体器件，其中所述阻抗匹配衬底由导电材料形成，并且所述屏蔽布线或所述屏蔽平面形成为所述阻抗匹配衬底的一部分。
15.如权利要求1所述的半导体器件，其中所述阻抗匹配衬底具有三角形状，并且该三角形状的一边被设置为邻近于和平行于所述半导体元件的一边。
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