CN1339159A - 垂直叠式现场可编程非易失存储器和制造方法 - Google Patents

垂直叠式现场可编程非易失存储器和制造方法 Download PDF

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CN1339159A
CN1339159A CN99815543A CN99815543A CN1339159A CN 1339159 A CN1339159 A CN 1339159A CN 99815543 A CN99815543 A CN 99815543A CN 99815543 A CN99815543 A CN 99815543A CN 1339159 A CN1339159 A CN 1339159A
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CN1213437C (zh
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M·G·约翰逊
T·H·李
V·苏布拉马尼安
P·M·法姆瓦德
J·M·克莱维斯
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SanDisk 3D LLC
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    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
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    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
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    • G11C2213/76—Array using an access device for each cell which being not a transistor and not a diode

Abstract

在此公开了一种极高密度现场可编程存储器。在衬底上利用几层(51a1,51a2,51b2)垂直地形成一个阵列,每个层(51a1)包括垂直构成的存储器单元。一个N层阵列中的单元可以利用N+1个掩膜步骤加接触所需要的掩膜步骤形成。最大限度利用自对准技术使光刻缺陷最小。在一个实施例中,外围电路形成在硅衬底上并且在该衬底上构成一个N层阵列。

Description

垂直叠式现场可编程非易失存储器和制造方法
本发明背景
1.本发明技术领域
本发明涉及低成本、高密度半导体存储器，具体地涉及当去掉电源时存储在存储器内数据不丢失和改变，即其内容为“非易失”的半导体存储器。
2.本发明背景
对更密集的半导体存储器有着日益增加的需求，客户们以更大数量连续购买这些存储器，正如每三年芯片位数(近似)翻两番，需要以更低成本更快增加密度以满足市场需要。
半导体非易失存储器可以分成两类：(1)在制造过程中数据被永久地写入其中并且其内容随后不能改变的存储器，称为“掩膜ROM”或“工厂编程ROM”；(2)在加工后存储器器件离开工厂之后可以向其提供数据的存储器。后一类称为“现场可编程存储器”，因为当半导体存储器芯片被用于最终用途时“在现场”由用户写入其内容。现场可编程存储器进一步分成“一次写入”存储器和“写入/擦除/再写入”存储器。这些一次写入存储器称为“PROM”(可编程只读存储器)或“OTPROM”(一次可编程只读存储器)。而提供写入/擦除/再写入能力的存储器被称为“UVEPROM”(紫外线擦除可编程只读存储器)或“EEPROM”(电擦除可编程只读存储器)或“Flash EEPROM”(快速和灵活EEPROM)。相反，在制造期间掩膜ROM的内容被永久存储，因此掩膜ROM不可擦除并且实际上是“在工厂一次写入”存储器。
现场可编程存储器比掩膜ROM灵活得多，因为它允许系统产品制造商为许多应用库存一种单独的通用零件类型，并且以大量不同方式在系统产品流程最后使一种零件类型个人化(对存储器内容编程)。这种灵活性使系统制造商更容易适应不同系统产品需求的波动，和更新和修改系统产品而不废弃(报废)现有的预编程掩膜ROM库存。但这种灵活性是有代价的：现场可编程存储器通常比掩膜ROM有着更低密度(每个芯片位更少)和更高成本(每一位更高价格)。客户更愿意买提供灵活性和方便性的现场可编程存储器，同时达到掩膜ROM的成本和密度。不幸地是，这种器件还不能获得。
掩膜ROM比现场可编程存储器密度高和便宜有两个原因。首先，由于掩膜ROM不支持擦除和重新写入功能，它们的外围电路不需要包含输入数据引导、写入定时或写入控制的任何专用电路或I/O端子。因此，掩膜ROM的外围电路可以比现场可编程非易失存储器的电路小。与现场可编程非易失存储器的模具尺寸相比，这减少了掩膜ROM模具尺寸的，使更多的掩膜ROM芯片可以安装在一个半导体晶片上，而降低了成本。
其次，由于掩膜ROM仅仅在工厂写入，它们的存储器单元可以仅仅为读取而设计和优化，通常它们的存储器单元仅仅包括单一电路元件(例如，单一MOS晶体管)。但是现场可编程非易失存储器的存储器单元必须包括对写入操作的支持。因此，现场可编程存储器单元通常包含几个电路元件：通常是在单一读取所需要的MOS晶体管上增加第二沟道氧化物镀膜栅极，或写入/擦除系列晶体管。现场可编程单元的额外元件消耗了额外的硅面积，使存储器单元面积比掩膜ROM存储器单元大。因此现场可编程非易失存储器的密度比掩膜ROM的密度低。
具有写入/读取/重新写入能力的现场可编程存储器也提供了更多的灵活性。它们允许更新、现场重新配置和能够使主机进行新应用，例如数字摄影、固态盘等。不幸地是，这些器件通常具有比一次可编程存储器低的密度和高的成本。
现在考虑用于这些存储器中存储器单元的设计，大多数非易失存储器单元已经利用了半导体器件，例如在单晶半导体衬底上构造的MOS场效应晶体管，结型晶体管，或结型二极管。这种方案只允许有限地垂直集成为第三维(即，与衬底平面相垂直)，因为每个存储器单元包含构造在衬底上的一些元件。
常规非易失存储器单元使用大量连续光刻步骤制造，这限制了单元图形的几何形状。例如，图1所示的现有技术的掩膜ROM制造需要至少五次光刻掩膜步骤：(a)氮化物LOCOS构图；(b)多晶硅栅极构图：(c)触点构图：(d)金属构图；(e)利用离子注入构图的编程。这些步骤顺序执行，并且小心地将每个后续层与已经在存储器电路上构图的前一层对准，以保证每层的几何图形被印制在所需要的空间位置上。例如，在图1中的单元10中，离子注入层常规地对准以前构图的多晶硅层。
不幸地是，在大量半导体加工中所使用的光刻机不能完全地执行这些对准。它们具有“层失准容差”指标，该指标表示为当新的层对准存储器电路已经存在的层时可能引起的对准容差。这些失准容差迫使存储器单元设计人员使用比如果对准容差可忽略时所需要的更大的图形尺寸。
例如，如果金属层上的某些图形需要完全覆盖接触层上的图形，这两层之间的几何重合必须设计得至少与接触层和金属层之间的失准容差一样大。另一个例子，如果多晶硅栅极层上的某些图形需要避免与LOCOS层上的图形接触，这两层之间的几何间隔必须增加到至少多晶硅栅极层和LOCOS层之间的失准容差一样大。
存储器单元尺寸由这些失准容差放大，这增加了模具尺寸，减少密度和增加了成本。如果找到需要更少连续光刻步骤的新的存储器单元结构，该单元在其图形尺寸上会包括较少的失准误差，并可以制造得比更多光刻步骤的单元小。
并且如果找到完全不需要对准的新存储器单元结构(一种“自对准”单元)，在X或Y方向上，就不需要在其图形尺寸中包括任何对准容差。新单元可以制造得比没有自对准存储器单元的相应单元更小。
图1表示了掩膜ROM中使用的非常普通的电路设计。这是“虚地”类ROM电路的例子，如同美国专利4281397所教导的。其存储器单元例如单元10包括在平面半导体衬底上构成的单一MOS晶体管，连接到多晶硅字线(例如WL1，WL2)，金属位线(例如BL1，BL2)和虚地线(例如VG1，VG2)。该单元通过极大增加MOS晶体管门限电压的掩膜编程，例如通过离子注入。例如，如果注入，该单元保持为逻辑1，如果没有注入，该单元保持逻辑0。
图2表示现场可编程非易失存储器，例如如同美国专利4203158所教导的。其存储器单元12包含字线，编程线，浮栅，位线和地线。通过在位线和编程线上施加适当的电压，该单元可以支持写入操作，擦除操作和重新写入操作以及读取。
图3表示可编程逻辑阵列(PLA)半导体结构，如同美国专利4646266所教导的。其基本单元14包括一对背对背二极管，给出四个状态：在两个方向上都不导电，在两个方向上都导电，在第一方向上导电而在第二方向上不导电，和在第二方向上导电而在第一方向上不导电。该结构不建立在平面半导体衬底上，而是将大量PLA单元垂直地一个一个层叠形成3维结构。
现有技术掩膜ROM电路的另一个类型如同美国专利5441907所教导。其存储器单元包含X导体，Y导体和可能的二极管。该单元通过掩膜编程，该掩膜允许(或阻止)在X导体和Y导体交叉点上的“插头”二极管的形成。例如，如果二极管出现，该单元保持逻辑1，而如果没有，该单元保持逻辑0。
使用熔丝和二极管两者的现场可编程非易失存储器单元在美国专利5536968中所教导。如果熔丝没有烧断(导电)，二极管连接到X导体和Y导体之间，而该单元保持逻辑0。如果熔丝烧断(不导电)，在X导体和Y导体之间没有连接的二极管，该单元保持逻辑1。
使用肖特基二极管和反熔丝两者的现场可编程非易失存储器单元在美国专利4442507中所教导。其存储器单元包含多晶硅半导体材料制造的X导体，肖特基二极管，形成反熔丝的本征或轻微掺杂半导体，和金属制造的Y导体。本征或轻微掺杂半导体反熔丝具有非常高电阻，并且对应存储器单元中所存储的逻辑零。但是，如果在该单元上施加适当高的电压，反熔丝转变为非常低电阻，对应该单元中所存储的逻辑一。
本发明概述
公开了一种包括用于增强一个方向上电流的引导元件和状态改变元件的存储器单元。状态改变元件保持被编程的状态并且串联连接到引导元件上。
使用这些单元的阵列垂直地构造成多层单元。自对准方法允许利用最少掩膜步骤的非常高密度。利用形成在衬底内或衬底上薄膜晶体管中的解码器和I/O电路，该阵列可以制造在硅衬底上。
附图简介
图1是现有技术掩膜ROM电路图。
图2是现有技术现场可编程存储器电路图。
图3是现有技术PLA电路图。
图4(a)是按照本发明构成的存储器单元实施例的透视图。
图4(b)是利用图4(a)单元阵列的示意图。
图5是利用图4(a)单元阵列的截面图。
图6(a)是用于制造图4(a)单元的不同实施例层的三个截面图。
图6(b)是用于制造图4(a)单元的导体层和层堆叠的透视图。
图6(c)是表示构图后图6(a)结构。
图6(d)表示已经形成额外导体层和层堆叠之后的图6(c)结构。
图6(e)表示构图后图6(d)结构。
图6(f)表示已经形成额外导体层和层堆叠之后的图6(e)结构。
图6(g)表示另一个构图步骤后图6(f)的结构。
图7是利用图4(a)单元阵列的截面图，其中这些单元在垂直方向上交错排列。
图8(a)是垂直层叠单元的透视图。
图8(b)是图8(a)单元的示意图。
图9(a)是表示衬底上电路布局的衬底平面图。
图9(b)是表示衬底上另一个电路布局的衬底平面图。
图9(c)是表示用于本发明衬底上一个电路布局的衬底平面图。
图9(d)是使用多个子阵列的本发明实施例电的平面图。
图10(a)是连接到阵列的外围电路示意电路图。
图10(b)是连接到阵列的外围电路的另一个示意电路图。
图11是连接到用于本发明优选实施例中阵列的外围电路示意电路图。
图12是阵列垂直截面图，表示存储器阵列三层之间的接触。
图13(a)表示层1和3之间的接触。
图13(b)表示连接层1、2和4的接触。
图13(c)表示层1、3和5之间的接触。
图13(d)表示层1到5之间的接触。
图13(e)表示层1和3之间的接触。
本发明详细说明
公开了一种现场可编程非易失存储器单元和存储器阵列。在下列说明中为提供对本发明更彻底理解而阐述了大量特定细节。可是，对于本领域技术人员来说可以不利用这些特定细节实现本发明是显而易见的。在其它例子中，公知电路和过程不详细描述，以便不使本发明混乱。
本发明综述
本发明的现场可编程非易失存储器单元构造在平面衬底上而非内部。因此，该存储器单元可以垂直层叠许多层形成三维阵列。存储器单元的每层只与上面层和下面层交互，这使垂直层叠相当简单。
也描述了安置在衬底上具有建立在衬底内外围电路的三维存储器阵列中这些单元的独特组成。
图4(a)表示新发明的存储器单元一个实施例。它具有两个明显的端子：输入端子20和输出端子21。这些端子之间，存储器单元包含引导元件22和串联连接的状态改变元件23。输入端子20、输出端子21、引导元件22和状态改变元件23都不建立在平面半导体衬底内。
引导元件22是具有强非对称电流对电压特性的器件；它在一个方向上比其它方向上更容易导电。引导元件22的用途是保证通过存储器单元的电流基本上为单向。该单向性能使存储器解码器建立到每个单独存储器单元的唯一电路路径，允许它单独被访问(用于读取和写入)而不论所有其它单元的状态。
状态改变元件23是能够设置在几个状态的器件，当电源消失时其状态不丢失或改变。在下面讨论的许多实施例中的一种可能是具有状态(高阻抗)和(低阻抗)的电介质击穿反熔丝。这两个存储状态完成存储器一位编码。
如图4(a)所示，引导元件22和状态改变元件23垂直层叠为通常具有矩形截面的“柱”型设计。该柱垂直，电流也垂直。取决于单向引导元件22的方向，电流可以向上或向下流动。实际上，在实施例中电流在某些垂直层叠单元向上流动，而在其它层中向下流动。
状态改变元件23被选择得可以通过电方法从初始状态向另一个状态切换，由此使存储器可现场编程。例如，通过在存储器单元输入和输出端子上施加相对大电压(当与读取所用电压相比时)可以电方式改变电介质击穿反熔丝的状态。
本发明的存储器单元能够利用在X(东西)和Y(南北)方向两者上完全自对准制造。这意味着柱子由输入导体和输出导体交叉限定和自动形成。因此，该单元可以制造得相当小，因为其图形尺寸不需要包含通常失准容差所用的容差。
另外，建立图4(a)的单元所需要的光刻掩膜步骤数量少。对于图4(a)和4(b)所示的单层单元，需要三个掩膜步骤：一个构图底层导体和单元材料，另一个构图上层导体和单元材料，而第三个提供阵列外的接触孔用于垂直电连接。该构图方案导致单元柱对上层和下层导体的自对准(即，引导元件和状态改变元件)。如果在第一层上增加垂直第二层元件，只需要两个另外光刻步骤：一个用于下层导体和单元材料，第二个用于阵列外接触。底层单元的顶导体形成了顶层单元的底导体。总之，如果阵列包含(N)层单元，则有(N+1)层导体和(N+1)个制造单元阵列自身的光掩膜步骤。也有大量另外光掩膜步骤以形成接触。这些接触在单元阵列之外；它们进行阵列导体层与外围电路之间连接。
存储器单元也可以使用替代实施例制造；上面描述的自对准柱形成可以由涉及利用柱形成光掩膜的形成替代。这消除了柱子对导体的自对准，但是在有可能利用自由侧壁物理性的制造过程中有利。这些过程包括使用非晶硅固相结晶的引导元件形成，非晶或多晶硅激光结晶，和本领域技术人员明显知道的其它过程。上述自对准制造过程和非自对准制造过程两者中的上导体接触是通过绝缘材料平面化而暴光的，不需要光掩膜步骤。该过程可以由接触形成光掩膜步骤所替代，对于本领域技术人员是明显的。
假设图5的第一导体25走向为东西。则第二导体26将走向南北(正交)，而存储器单元柱27将形成在第一导体垂直投影与第二导体交叉处。第三导体29将走向东西，而存储器单元柱30将形成在第三导体29与第二导体26交叉处。类似地，第四、第六、第八、第十，…导体将南北走向，而第五、第七、第九、第十一，…导体将东西走向。奇数导体在一个方向走向，而偶数导体带垂直方向走向。因此，第J号导体形成向下柱子(到引线J-1层)和形成向上柱子(到引线J+1层)。
由于存储器单元不需要接触单晶半导体衬底，存储器单元阵列之下的衬底可以使用而不限定存储器单元。在本发明的一个实施例中，通过直接在存储器单元阵列下面布置行解码器，列解码器，I/O多路通道和读取/写入电路而有利地利用了该面积。这有助于使不形成存储器单元的模具表面面积部分最小，这增加了称为“阵列效率”的品质指标：
可见，(不形成存储器单元的总面积的)减少使阵列效率增加。
存储器单元：柱体
图4(a)表示的本发明存储器单元的实施例中，有两个明显的本地端子：一个输入端子20(也称为字线)，和一个输出端子21(也称为位线)。另外，该单元也可以包含“隐含”或“广泛共享”端子，这是其结构的必然结果，并且同时对于大单元组是通用的。明显端子的一个例子是半导体衬底，它对于每个存储器单元形成寄生电容。为简化附图和讨论，这些隐含端子被省略，但是如同所认为的那样，这些隐含端子可能影响存储器单元的功能和性能。因此所发明的存储器单元成为“两端子结构”，意味着有两个显性、本地端子，并可能具有另外的隐性而非显性的端子。
在输入端子和输出端子之间，存储器单元包括引导元件和状态改变元件的串联连接。在某些实施例中，引导元件可以连接到输入端子(并且状态改变元件连接到输出端子)，而在其它实施例中它们可以相反：状态改变元件可以连接到输入端子而引导元件连接到输出端子。
引导元件是具有强不对称电流对电压特性的半导体元件；它在一个方向上比在其它方向上更容易导电。引导元件的某些实施例是(1)一个PN结二极管，在非结晶、微晶、多晶或单晶半导体中(例如，Si，Ge，SiGe，GaAs，InP等)；(2)一个金属半导体肖特基二极管；(3)一个结型场效应晶体管具有连接到源极(或漏极)的栅极；(4)一个MOSFET具有浮动栅极，或连接到源极或连接到漏极；(5)一个齐纳二极管，雪崩二极管，或沟道二极管；(6)一个四层二极管(SCR)；(7)一个P-I-N二极管，在在非结晶、微晶、多晶或单晶半导体中；和其它对于本领域技术人员为显而易见的元件。
在本说明书中为说明的目的，引导元件的两端称为“阳极”和“阴极”，设计得常规电流从“阳极”到“阴极”流动比从“阴极”到“阳极”容易。这些标记与PN结二极管的标准术语一致；PN结二极管中常规电流从阳极向阴极流动。当然，本发明不限于使用PN结二极管作为引导元件(如同前面段落所讨论的)；采用与二极管相同的端子标记是因为方便和熟悉。另外，如果在引导元件阳极上的电压大于阴极上电压，该引导元件为“正向偏置的”。但是当阴极电压超过阳极电压时，引导元件将称为“反向偏置的”。这些词组也借助标准的二极管术语，也为了方便和熟悉。
引导元件可以用两个不同方式定向：(1)阳极面对输入端子和阴极面对输出端子；(2)阴极面对输入端子而阳极面对输出端子。每个定向都可以被使得正确起作用，通过适当设计存储器解码器和读取/写入电路，而没有一个定向明显优于另一个定向。
状态改变元件是存储器单元内实际存储数据的地方。正是该器件可以被设置为几个状态，并且被选择得当电源消失时其状态不丢失或被改变。
按照本发明在状态改变元件中使用的状态类型的例子是(1)(高阻抗状态)和(低阻抗状态)；(2)(在电压V1上的峰值电容状态)和(在电压V2上的峰值电容状态)；(3)(霍尔效应正电压状态)和(霍尔效应负电压状态)；(4)(上极化矢量状态)和(下极化矢量状态)和其它。
状态改变元件的一些可能实现方法包括，但不限于，(a)电介质击穿反熔丝；(b)本征或轻微掺杂多晶半导体反熔丝；(c)非结晶半导体反熔丝；(d)金属灯丝电迁移熔丝，可逆转(美国专利3717852)或不可逆转类型；(e)多晶硅电阻熔丝，可逆转(美国专利4420766)或不可逆转类型；(f)铁电体电容；(g)陷波感应滞后电容；(h)库仑封锁器件，和其它元件。
在集成电路制造期间，存储器单元的状态改变元件被制造和设置为一种可能状态；该状态称为“初始状态”。例如，如果状态改变元件是具有两个状态的电介质击穿反熔丝(击穿电介质)和(完整电介质)，在制造后和编程前该元件的初始状态是(完整)。状态改变元件的其它实施例将具有不同状态和因此不同的初始状态组。通过约定初始状态，“逻辑零”状态代表半导体制造期间存储在存储器单元内的初始值。当然对于其它约定，例如称初始状态为“逻辑一”，也可以同等有效，并且该选择仅仅凭喜好和方便而已而非技术必需。
存储器单元通过使状态改变元件从初始状态转变为新状态被编程。状态改变元件的许多实施例可以通过在存储器单元上从输入端子向输出端子施加适当大的电压改变状态。例如，如果状态改变元件以电介质击穿反熔丝实现，通过在单元端子上施加大电压编程(或通过强制大电流通过单元)，而极性选择得以便引导元件被正向偏置。这在电介质反熔丝上直接施加了大电场，该电场击穿该电介质，因此改变状态改变元件的状态。
对电介质击穿状态改变元件编程的一种可能方法是将存储器单元输出端子接地并且同时将其输入端子提高到大的正电压(假设引导元件定向得其阳极面对输入端子而阴极面对输出端子，即当输入端子在比输出端子更高电压时引导元件被正向偏置)。如果引导元件以其他方式定向，阳极面对输出端子而阴极面对输入端子，设计人员可以简单地反向编程电压和保持编程期间引导元件正向偏置：接地输入端子和同时提高输出端子到大正电压。正向偏置引导元件和对电介质击穿状态改变元件编程的许多其它电压设计对于本领域技术人员是显而易见的。
状态改变元件的其它实施例可以通过强迫适当大电流通过存储器单元实现，而非强迫在存储器单元上施加大电压。例如，如果状态改变元件以多晶硅-电阻熔丝实现，可以通过将电流源连接到其输入端子和同时将输出端子接地编程(假设该极性正向偏置引导元件)。假设电流足够大，它改变多晶硅电阻熔丝的阻抗，因此改变了状态改变元件的状态和对该单元编程。
在编程期间，有可能由全部编程电压反向偏置不选择的存储器单元。可能发生不选择存储器单元的意外写入，如果引导元件的反向漏电流超过为改变状态改变元件的状态所需的编程电流。因此，引导元件和状态改变元件的特性应当相互匹配；需要大电流编程的状态改变元件(例如，本征多晶硅熔丝)可以与相当高漏电流引导元件一起使用，而以非常低电流编程的状态改变元件(例如，电介质击穿反熔丝)需要低漏电流的引导元件。
本发明的存储器单元可以用一次可编程非易失存储器或用写入/擦除/重新写入非易失存储器实现，取决于所选择的状态改变元件。在第一例子中，如果利用薄、高阻多晶硅膜反熔丝作为状态改变元件(如同美国专利4146902所教导的)，其编程操作是不可逆转的和该单元是一次可编程。在制造后编程前，所有单元包含“逻辑零”。通过强制状态改变元件为新状态，对需要内容为“逻辑一”的那些单元不可逆转地编程。逻辑零可以变成逻辑一(通过编程)，但逻辑一不可以变成逻辑零(因为在这类状态改变元件中编程是不可逆转)。
在第二例子中，如果金属对绝缘层硅灯丝熔丝作为状态改变元件(如同美国专利3717852所教导的)，其编程操作是可逆转的并且该单元可以被写入、擦除和重新写入。制造后和编程前，所有单元包含“逻辑零”。对那些内容希望为“逻辑一”的单元编程。可是，对于该状态改变元件，编程是可逆转的并且逻辑值可以从零到一改变和从一到零改变回来，如果需要的话。
在第三例子中，可以利用具有写入/擦除/重新写入能力的状态改变元件，其编程操作是电的而其擦除操作不需要电。该擦除操作可以选择地施加在单一存储器单元上，或可以同时施加在所有存储器单元上，“大批”，例如通过将它们暴露在强紫外线光下，如同UVEPROM存储器所作的。或者，大批擦除操作可以通过加热集成电路，从IC外部热源或从直接在IC上的加热器，进行；或者，大批擦除可以通过将状态改变元件放置在强磁场中进行。
尽管上面的讨论是基于具有两个状态的状态改变元件，但这不是必要的。能够提供预定范围电阻例如部分熔化的反熔丝可以提供三种状态的元件。浮栅MOS器件允许大量可能的多层存储实施，为状态改变元件提供比多于2个的状态，如同本领域所公知的。
存储器单元：导体
如图4(a)所示，现场可编程非易失存储器单元包括垂直柱体，在柱体底部有导体而在柱体顶部有另一个导体。
底部导体为第一导体层上的相对长导体或导线。该导体在一定方向上走向(例如，东西方向)。顶部导体为第二导体层上相对长导体或导线，与形成底部导体层垂直。顶部导体在另一个方向上走向(例如，南北方向)。顶部导体和底部导体之间的角度最好为九十度(即，最好正交)但不是强制性。存储器单元柱体位于顶部导体与底部导体投影的交叉处。
实际上每层上的导体是平行间隔开的导体，其中每个导体之间的间隔例如等于导体的宽度。
第一导体层(“导体1”)包含全部在相同方向走向的大量平行导体，例如东西方向。而第二导体层(“导体2”)也包含全部在相同方向走向的大量平行导体，例如南北方向，最好与第一导体层的导体方向垂直，如同5所示。是凡在导体2上的导体跨过(或交叉)导体1上的导体的地方，都构成现场可编程非易失存储器单元之一。在图4(b)中表示。
垂直地从底部到顶部，本发明的存储器单元包含导体，然后是柱体，然后是另一个导体：导体1-柱体-导体2。导体1在底部而导体2在顶部。但是导体2是存储器单元新的层的底部，垂直层叠在第一层上：导体1-柱体1-导体2-柱体2-导体3。本发明一层层地层叠多层存储器单元：具有(N)层存储器单元的垂直层叠包含(N)层柱体和N+1层导体。(它采用(N+1)层导体层制造N层单元：每层柱体底部上的一个导体，和然后阵列顶部上又一个导体)。图5表示了按照本发明的三维存储器阵列一部分，具有N＝6层存储器柱体和(N+1)＝7层导体。(N)个柱体的垂直层叠使用与不垂直层叠(N)个柱体组件表面积的1/N面积；垂直层叠提供了N倍密度改善。
存储器柱体底部导体是下面存储器柱体的顶部导体，而存储器顶部导体是上面存储器柱体的底部导体。这使层叠特别简单而灵活。
在实施例中，存储器柱体每端上的两个导体是垂直的。并且由于在个层柱体之间共享导体，使得该实施例中偶数导体在一个方向走向，而奇数导体在垂直方向上走向。例如，假设导体1在东西向走向。导体2应当垂直于导体1，所以导体2在南北向走向。导体3垂直于导体2，所以导体3在东西向走向。导体4在南北向走向(垂直于导体3)，等等。因此导体1、3、5…在东西向走向，而导体2、4、6…在南北向走向(在该例子中)。
制造
在本发明的实施例中，一个导体层(假设，导体层号码J)南北向走向，而相邻导体层(号码J-1或J+1)东西向走向。凡在层(J)上导体垂直投影交叉层(J-1)上导体的地方，都产生一个存储器单元柱体。同样地，凡在层(J+1)上导体投影交叉层(J)的地方，都产生一个存储单元柱体。存储器单元柱体由导体的交叉限定和构图，所以柱体与导体自对准。自对准是非常重要的优点，因为它能够进行存储器单元光刻构图而不需要包括任何另外的失准容差公差。因此本自对准存储器单元构图图形可以制造得更小，产生更小的单元面积，而给出更高的密度和更低成本。
为说明这些柱体的自对准制造，考虑使用四个连续材料层(“层堆叠”)制造引导元件和状态改变元件的实施例。在该说明性例子中，引导元件包括一个多晶硅PN结二极管，而状态改变元件包括一个多氧化物多电介质击穿反熔丝。在本申请还中阐述其它的实施例。
在该实施例中，柱体包含一个层堆叠中的四层材料，如图6(a)所示顺序安置：(1)一层P+掺杂多晶硅40；(2)一层N-掺杂多晶硅41；(3)一层二氧化硅42；(4)一层N+掺杂多晶硅43。层(40)和(41)形成一个PN结二极管(引导元件)，而层(41-43)形成多氧化物多电介质击穿反熔丝。在该实施例中，一起产生存储器单元的四层材料层叠称为“层堆叠”45。在层堆叠45上和下也有如同所要描述的导体层。在图6(a)所示的导体46和48。
在图6(a)中表示了一种替代层叠，如层叠450。它也包括层叠端上的导体，尤其是460和480可以用任何导电材料例如金属或多晶硅制造。层叠450中的引导元件包括P+掺杂半导体的第一层400，例如微晶硅，和N掺杂半导体的第二层例如微晶硅。
状态改变元件包括层420。层420可以是用于形成反熔丝的非结晶硅。该层具有额定高电阻，可是，为编程通过大电流后，其电阻明显更低。该层430表示为N+层以提供对重叠导体480的良好电接触。层430可以是非结晶、微晶或多晶硅，但是加工方法需要低温保持层420中的非结晶结构。
图6(a)也表示了另一个层叠405。它包括一个N-多晶硅层400，一个二氧化硅层402和一个N+多晶硅层403。层400或403也可以是微晶硅或非结晶半导体层。层叠405是导体406和408之间的夹层。在此，引导元件是由导体406金属和层400形成的肖特基二极管。该状态改变元件是层402形成的反熔丝。作为例子，层406和408可以是具有近似1000A厚度的钛硅化物或铝。层400、402和403可以分别是500A、80A和500A厚度。
存储器单元的制造顺序在图6(b)-6(g)中示意性说明。在沉积后和构图前，层堆叠45(或堆叠450和405)是在整个集成电路上伸展的连续薄膜(确实横过整个晶片)，例如如图6(b)所示。自对准方法原理上是两蚀刻步骤过程：在第一蚀刻步骤，该层堆叠(连续薄膜)被构图成为东西走向的长直带(譬如说)，利用在下面导体层上蚀刻东西导体相同的构图步骤进行蚀刻。层间电介质沉积和极化之后，沉积第二导体和层堆叠。该堆叠被构图成为南北走向的长直带。用于构图南北线的蚀刻继续，直到第一层堆叠已经蚀刻穿过引导元件为止。这在东西走向线路上形成柱体。产生的柱体与下面导体和上面导体两者完全对准，因为柱体和导体两者被同时蚀刻。在替代实施例中，层堆叠(45或450或405)内的半导体层可以沉积为微晶或多晶硅，然后被激光处理改善结晶度和增强掺杂物活性。
柱体的截面是矩形，一边等于底部导体的宽度而另一个边等于顶部导体的宽度。如果这些导体具有相等宽度则截面为正方形。
在东西和南北两个方向上的构图使用在半导体行业广泛使用的公知光刻步骤，和可以使用湿或干蚀刻。当用作导体时也在单元中使用的硅可以原地掺杂或在沉积后通过例如离子注入掺杂。
当然，可以使用其它构图技术而非蚀刻，例如“发射”技术或“镶嵌”技术或添加技术而非减少方式的构图技术可以被利用替代蚀刻。但是，层堆叠理想地由两个单独步骤构图，一次利用掩膜限定下面的导体，再次利用掩膜限定上面的导体。不论使用特定制造技术构图各种层都如此。
实际上建立了大量垂直层叠存储器单元，每个导体层自对准下面层堆叠和上面层堆叠。因此将导体自对准柱体的蚀刻步骤必须从三个不同层上蚀刻下材料：上面层堆叠，导体层，和下面层堆叠。
加工可以从晶片开始，该晶片可能已经接受了前面的加工步骤，例如在单晶硅衬底上制造了外围电路的CMOS晶体管。然后沉积绝缘层，最好平面化(使用化学-机械-抛光(“CMP”)，抗深腐蚀平面化，或大量其它平面化技术中的任何一个)。第一导体层被沉积为图6(b)的层46，然后第一层堆叠45被沉积。图6(b)表示了这一阶段的晶片。
接着，施加限定导体1层上图形的掩膜，这些图形被蚀刻在柱体层堆叠45上和导体1层46下面。在晶片上沉积绝缘层并且使用CMP或其它平面化技术进行平面化。特别注意，柱体层堆叠和底层已经被蚀刻成为长连续带(46a和45a)和(46b和45b)，不是绝缘的单独柱体。也注意，柱体层堆叠45a和45b的边缘对准导体46a和46b层的边缘，因为两者以相同的掩膜同时蚀刻。注意导体通常包括共平面导体，例如每层上的铝或其它金属，硅化物，或掺杂硅导体。
尽管图6(c)或其它图中没有表示，电介质填充到带(和柱体)之间的空隙并且因此增加对阵列的支持。也应当注意，平面化必须展露出带的顶表面以便随后的导体层接触带。平面化的电介质也形成一些层，通过这些层图13的通路和垂直导体穿过。
接着，沉积第二导体层50(“导体2”)，和沉积第二柱体层叠51(“层叠2”)。图6(d)表示该阶段的晶片。注意平面化自动给出柱体层堆叠(例如45b)和其上随后导体层(例如50)之间的自对准接触。
现在，施加导体2掩膜，并且其图形被向下蚀刻成三个不同层：柱体层叠2(51)，导体2层50，和柱体层叠1(45a和45b)。(该蚀刻在45a和45b内的引导元件下面停止，提供了通过存储器单元的唯一电路路径)。在晶片上沉积绝缘层并且进行平面化(使用CMP或其它方法)。图6(e)表示该阶段的晶片。注意，导体2掩膜+蚀刻已经完成了对层堆叠1中单个柱体(45a1，45a2，45b1和45b2)的限定。也注意，层堆叠1层中的这些柱体对准导体1层(46a，46b)和导体2层(50a，50b)两者，由此实现自对准目的。
接着，沉积第三导体层52(“导体3”)，和沉积第三柱体层堆叠53(“层堆叠3”)。图6(f)表示给阶段的晶片。
现在，施加导体3掩膜，和其图形被向下蚀刻成层堆叠3、导体3和层叠2中。(该蚀刻在层堆叠2的引导元件下面停止，并且将留下完整的导体2层)。在晶片上沉积绝缘层并且平面化(使用CMP或其它方法)。图6(g)表示该阶段的晶片。导体3掩膜+蚀刻已经完成了对层堆叠2中单个柱体(例如51a1，51a2，51b1和51b2)的限定。图6(g)表示需要N+1＝3导体层和此后N+1＝3掩膜步骤以构图N＝2层柱体层堆叠(不计算层间通道层，该层用于外围电路但不在存储器阵列内)。该晶片现在准备好任凭制造者容纳更多层堆叠和导体层。
在本发明存储器单元一种可能实施例中，柱体被直接垂直地一个一个向上层叠，如图6所示。注意柱体排列成垂直对准层叠。可是，因为自对准，这种直接一个一个向上的柱体垂直层叠不是一种要求。
凡在导体层(J+1)上的导体跨过导体层(J)上的导体处自动形成存储器单元柱体。即使导体层不直接一个在一个上面排列而给出柱体垂直层叠，这也成立。实际上，最好柱体不垂直层叠；即它们相互偏离，如图7所示。比较图5(垂直层叠柱体)与图7(相互偏离柱体)可以看出效果。如图7所示的偏离或交错柱体排列实际上可能有利。这可以有助于给出更平滑晶片表面，更适合于平面化和抛光。
在上述步骤序列中，电极与导体材料与器件材料被一起蚀刻。由于大多数等离子体金属蚀刻也蚀刻多晶硅，能够进行这种双蚀刻实际复合材料为例如铝和多晶硅。如果需要通过使用可选择的蚀刻化学物(例如，优先蚀刻多晶硅，但在铝上停止)，或通过使用不被消除电极和器件材料的蚀刻剂蚀刻的阻挡层材料，可以实现蚀刻过程的控制。状态改变元件也可以用作蚀刻停止材料，特别是如果它是氧化物击穿类型的话。
耐熔金属例如钼和钨适合于硅的常规CVD沉积温度，可以用作导体。金属硅化物适合于用作激活硅中掺杂物的更高温度。甚至重掺杂硅自身也可以用作导体。可以根据电阻系数和集成考虑包括蚀刻特性进行选择。
在上述前半部分步骤之后描述的平面化对于形成与半蚀刻单元的自对准接触(即，在上述例子中东西向走向的线路)上是必要的。这种平面化可以通过本领域公知的各种方法实现，例如化学-机械抛光(CMP)，再次蚀刻自旋电介质层，并且再次蚀刻自旋聚合物，引用三种公知例子。为允许平面化期间可能出现的过度抛光或过度蚀刻，在电极层沉积之后可以进行第二次平面化以保证器件材料层随后沉积有一个平整电极表面。
上述处理顺序利用自对准以减少柱体和导体之间所需要的对准容差。该实施例可以由涉及一个或几个额外光掩膜步骤清楚地限定柱体自身的实施例所替代，而非使用两个导体光掩膜步骤的交叉限定，如同在自对准过程中所做的。这在可以利用清楚限定这种过程中产生的侧壁的各种过程中有利。例如，可以使用非结晶硅的固相结晶形成引导元件层堆叠。预计侧壁的自由能量促进引导元件中的单晶或晶粒形成，这在某些系统实施例中或许是有利的。
能利用清楚限定侧壁的另一种处理是激光感应结晶化。仍然，预计侧壁自由能量促进引导元件中的单晶或晶粒形成。
在涉及柱体明显限定的过程中，将使用光掩膜步骤限定底部导体。可以进行蚀刻。然后，沉积形成状态改变和引导元件所需要的层堆叠。将使用另一个光掩膜步骤限定柱体，可以进行蚀刻。在蚀刻后，沉积绝缘材料并且如在自对准单元中那样平面化，暴光柱体顶部形成自对准接触。顶部导体然后被沉积和对所需要的随后单元层重复该过程。
上述过程中掩膜步骤的顺序也可以相反。例如，在构图底部导体之前形成柱体。在该过程中，将沉积底部导体，引导元件和状态改变元件的整个层堆叠。然后平版印刷限定柱体并且穿过引导元件向下蚀刻。然后限定和蚀刻底部导体。将使用平整后绝缘层接触方案钝化该结构，如上所述。在所有三个过程中，自对准接触可以用形成光掩膜步骤的明显接触替代。
各种器件制造步骤可能产生的残余化学物或不饱和键可以减弱器件的性能。实际上，可能由这种不饱和键或化学物引起器件漏电流(例如，没有完全消除的光刻胶)。低温(例如小于400C)等离子体氧化暴光可用于在器件柱体边缘上生长清洁的氧化物，由此钝化边界缺陷。氧化物生长是自限性的，因为氧元素只通过以前生长的氧化物慢慢扩散，产生非常均匀的氧化物厚度，因此改善了工艺性。(等离子体氧化也可以用于形成反熔丝层。)氧化物沉积也可以用于钝化表面，例如单独或与生长氧化物一起。
因为，在上述一些实施例中，器件材料(例如多晶硅)在电极材料(例如，金属)后沉积，希望在最低实际温度下沉积和处理该器件材料以扩大适用金属的选择。举例，可以使用LPCVD(低压化学汽相沉积)，PECVD(等离子体增强化学汽相沉积)，PVD(物理汽相沉积)，或UHVCVD(超高真空化学汽相沉积)在低温下沉积原位掺杂多晶硅。一种替代方法是沉积不掺杂多晶硅，随后利用低温处理掺杂和激活。(传统激活步骤例如长时间加热退火显露出晶片可能不可接受高温)。也可以希望在某些情况下以微晶或非晶硅或结晶非晶硅替代多晶硅，以保证进行低温制造。
另一个考虑是在处理期间电极材料(例如金属)扩散到器件层的可能性。低温处理有助于减少问题的严重性，但可能不足以完全解决问题。为防止此问题，可以利用大量阻隔材料。例如包括本领域公知的许多材料中的氮化钛(TiN)，钽(Ta)或氮化钽(TaN)。
在单元的实施例中，利用薄电介质层作为反熔丝元件。在这种单元中，电介质厚度的良好均匀性，以及低的膜缺陷密度(例如在电介质中的小孔)是非常需要的性能。通过各种方法可以增强电介质质量，例如在沉积期间旋转(连续或周期性)衬底和/或源极；利用等离子态或低温生长化学物通过加热方法形成电介质；或通过利用液相电介质沉积方法。
希望减少涉及严格对准容差的掩膜步骤数量。减少掩膜步骤的一种方法是利用相互连接几个电极层的通道。该通道可以是矩形，而非正方形，以允许放宽对准容差。例如，为互连X方向走向几个层中的金属线，Y方向上X边缘通道尺寸可以制造得基本上松于X线的间距，产生矩形通道。结合图12和13讨论通道。
接触形成
如同前面所指出，需要每层接近一个掩膜步骤形成存储器层中的单元。可是，需要额外掩膜形成到阵列中导体的接触，通道和垂直导体(有时集体称为接触)，如同下面所要讨论的。首先，回忆到只需要为每个阵列导体制造一个接触。因此，如果接触位于阵列导体的端部，在给定层中每个其它导体的接触可以在阵列的相反一侧上。这是重要的，因为这为接触提供了更多面积。另外，在相同层上的导体不需要有相同长度。即，例如它们渐渐缩短，或加长，或在相同层加长而在其它层缩短，以便允许在阵列外围上用于接触的面积。这些接触可以向下到达下面层，例如每个其它下面层而不干扰中间层的导体。
需要阵列之外的接触将阵列中导体连接到驱动电路。建立在衬底上的晶体管一般提供驱动。驱动晶体管也可以利用为阵列共有的材料建立在衬底之上。接触的最简单实施方法是具有阵列每层的通道掩膜。这些接触用于将上面层通过所有其下面的层电连接到衬底。这些接触直接一层一层层叠或交错建立，两个方法在半导体行业中是普通的。
总之，通道和接触用于提供阵列中导体与外围电路之间的导电路径。例如，形成在阵列周遍的接触可接触到图9(a)、9(b)和9(c)所示的解码器，列I/O电路和行地址解码器。在另一个实施例中，可能希望在，例如，玻璃衬底上制造阵列，并且利用具有接触的薄膜晶体管在层上形成外围电路，而该接触提供了从该层到阵列中导体的导电路径。在另一个实施例中，最顶层可以用于功率分配。
制造接触的一种直接方案，对每层使用一个掩膜和蚀刻步骤，该步骤出现在用于限定导体的层形成之前。该掩膜步骤形成层下的开孔并且提供所需要的接触。
在图12中表示了这样一个例子。由结构基础开始，在开始制造阵列之前穿过衬底绝缘层100到衬底接触101掩膜和蚀刻接触110。
在存储器层叠131之前沉积导体层106。在该例子中存储器层叠107的底层是重掺杂半导体。这在该例子中很重要，因为重掺杂半导体将提供欧姆连接，并且因此不需要从导体层上完全去除。
在构成层1的带形成期间区域120和接触110上的区域形成。在此情况下，依靠层1掩膜布局120与层1上的其它导体绝缘。然后沉积电介质并且平整暴露出层1的顶表面。然后通过层1层向下至少到重掺杂层107形成接触开孔111。
然后以构图层1相同的方式沉积和构图层2导体122和存储器层堆叠。再次，使用掩膜将该区域与层2阵列的导体绝缘。再次沉积电介质并且再次蚀刻以暴露层2的顶表面。正如层1中一样，接触掩膜用于形成穿过存储器单元元件向下到重掺杂材料的开孔112。
最后，层3导体被沉积到开孔112中以形成从层3到衬底的连续电连接。
根据上述说明书应当清楚，来自任何层的接触可以利用每层的另外掩膜步骤制造得到衬底区域。在另一个实施例中，使用每层少于一个掩膜步骤形成到衬底的导电路径。这在几个导体接触单一衬底区域情况下是可能的。注意图13(c)，例如，导体1、3和5连接到相同衬底区域。
图13(a)-13(e)表示了接触的几种可能结构。在图13(a)中表示了其中接触被制造在层1(或层N)和层3(或层N+2)中的导体之间的设计。注意在该设计中，层N+1中的导体制造得比层N和层N+2中的导体短些，以允许制造接触而不干扰层N+1中导体的所用的足够空间。在此，由于在相邻层之间，该接触穿过存储器层叠延伸，以交叉线阴影表示。
在图13(b)中，表示了来自接触层1和2(或层N和N+1)中导体的层4(或层N+3)中导体的接触。注意在该设计中，层N+2中的导体比层N中的导体短，允许根据层N+3制造的结构下达和接触两个下面导体。只需要在绝缘层中限定一个单一开孔以形成该接触，和该开孔通过平整步骤中所使用的氧化物或其它绝缘材料沉积。
图13(c)表示了另一个接触，其中来自层1、3和5的导体连接到衬底区域。在此层2和4中的导体交错以致不干扰接触。再次仅仅使用单一掩膜步骤限定该接触。
在图13(d)中表示了接触的结构，其中层1、2、3、4和5各具有连接到公共衬底区域的导体。
最后图13(e)中表示了从层3(或层N+2)到层1(或层N)的接触。在此不同与图13(a)，穿过绝缘材料制造单一开孔。
在形成结构13(a)-(e)中，垂直导体的电阻系数是重要的。可以使用金属、硅化物和原位掺杂硅。注入硅现在不是最佳选择，因为在接触侧壁上掺杂硅有困难。
应当注意，在形成图13(d)的接触中，首先从顶层穿过几个底层蚀刻一个开孔。在绝缘层已经被蚀刻暴露该层边缘之后，然后均质地蚀刻存储器单元材料以暴露更多导体。这样，均质沉积材料象多晶硅或CVD W可以用于获得每个导体上的大表面面积以保证低接触阻抗。
尽管图13(c)的接触使用相同的原理，因为各层交错，只需要均质地蚀刻绝缘材料以暴露层1和3导体的边缘。
图13(d)和13(c)表示的技术用于限制该过程中所需要掩膜步骤的数量。使用任何一个都可以将掩膜数量从2N+1减少到N+2。
存储器单元：小图形尺寸
如同前面所讨论的，自对准允许存储器单元构图图形小，因为当布置该图形时不需要失准容差。这些更小的图形允许减少存储器单元面积，实际上比没有使用自对准的面积更小。
但是存储器单元的第二个有利处允许该单元进一步减小：在每个掩膜层上几何图形的高重复构图。
本发明存储器单元阵列每层的几何形状尤其简单：它们只是靠近间隔长直平行导体线路的高重复规则集群。可以在照相制版光刻中利用其简单性和规则性，允许比其他任意几何形状可能更小的图象尺寸有更好的分辨率。例如，如果(晶片分挡器和照射光源和镜头和光刻胶)系统正常评定为几微米分辨率(例如0.18微米)，本发明的简单和非常规则形状允许明显小于几微米的线和间隔。本发明可以利用这一事实的优点，即，没有任意几何形状，反而有高度重复非常简单构图，这在光学领域是公知的并且在教科书中称为“衍射光栅”。对本专业技术人员显而易见的是，如何利用衍射光栅构图的优点达到更好的分辨率。
三维阵列构成
从来没有假设具有六层存储器单元柱体，和因此具有七个导体层的实施例。如果底部导体层(导体1)东西向走向，则导体3、导体5和导体7也东西向走向。而导体2、导体4和导体6南北向走向。为简单起见，在该实施例中柱体没有偏离或交错，当然一个一个向上直接层叠。图8(a)表示了六个这种柱体的单一垂直层叠。
图8(a)的六存储器单元柱体层叠表示为图8(b)中的电路图。注意在该电路图中导体层1、3、5、7相互间隔，但是在物理结构上(图8(a))它们一个一个向上直接层叠。同样地，在图8(a)中导体层2、4、6垂直层叠，而在图8(b)中间隔开。
图8(a)中有六个存储器单元柱体：一个在导体2跨过导体1处，一个在导体3跨过导体2处，…，一个在导体7跨过导体6处。在图8(b)的图示中，这些沿对角线表示。在底部左侧，表示了导体2和导体1之间的存储器单元(包含引导元件和状态改变元件)。图8(b)也表示了在导体3跨过导体2处的一个存储器单元和在导体4跨过导体3处的另一个单元，等等。
存储器单元柱体的相邻层共享一个导体层，因此它们也共享一个I/O端子。在实施例中，共享仅仅在相同类型端子之间进行：输入端子与其它输入端子共享一个导体层，而输出端子与其它输出端子共享一个导体层。该实施例是有利的，因为这意味着每个导体层不会不清楚，或者是输入层或者是输出层。没有如果导体层在输入端子和输出端子之间共享所出现的混乱，所以外围电路简化。输入端子驱动器电路和输出端子接收器电路不需要搭配和重合在相同导体上。
类似端子共享选择的结果是存储器单元中的引导元件定向得阴极向上，然后阴极向下，然后阴极向上，等等。为此，假设导体层导体2是一个输出层；则柱体60和柱体61的阴极两者连接到导体2。这样柱体60必须定向阴极向上而柱体61阴极向下。继续地，如果导体2是一个输出层，则导体3是一个输入层。柱体61和柱体62的阳极连接到导体3。所以柱体62阴极向上。对于该实施例柱体层必须交替，阴极向上，阴极向下，向上，向下，向上，等等(见图6(b))。这意味着在制造期间，柱体夹心的分层必须以不同顺序沉积。在某些柱体层中，阳极材料分层在阴极材料分层之前沉积，而在其它柱体层中阴极材料首先沉积。因此图6(a)所示的层必须是所示的交替阵列层顺序，而在其余层中是相反顺序。可是，应当回忆起在某些实施例中不必交替层叠材料。
选择共享相同存储器单元端子的进一步结果是使导体层只在输入端子之间和输出端子之间交替。因为连续的导体层东西走向，然后南北走向，然后东西走向等，这意味着所有输入端子在相同方向走向(例如东西向)，而所有输出端子在相同方向走向(例如南北向)。所以，一起安置输入端子驱动器电路(例如沿存储器阵列西边缘)，和一起安置输出端子接收器电路(例如，沿存储器阵列南边缘)特别容易。
这对应了常规存储器设计中的标准做法：输入端子驱动器电路67沿阵列西边缘安置，而输出端子接收器电路68沿阵列南边缘安置，如图9(a)所示。有时，常规存储器将半个输入端子驱动器电路沿东边缘放置，而半个沿西边缘；当存储器单元行间距非常紧密时经常这样做。类似地，有时常规存储器将半个输出接收器电路沿南边缘放置，而半个沿北边缘放置；当存储器单元列间距非常密时经常这样做。图9(b)表示了这种分开实现的常规存储器。
现在应当注意，非易失存储器(常规技术和本发明的)中输入端子驱动器电路具有更短和更少麻烦的名称“行地址解码器”电路。非易失存储器(常规技术和本发明的)中输出端子接收器电路具有更短和更少麻烦的名称“列地址解码器和列I/O”电路。在这部分讨论存储器单元底板外部阵列结构的公开中，使用这个缩短的名称。
有可能在存储器阵列下面重叠行解码器电路和列解码器列I/O电路。(有可能这样是因为存储器阵列在下面的单晶硅衬底之上而不接触该衬底。)完全重叠所有行解码器电路和所有列电路在阵列之下是所不到的；这种重叠会在角落中重叠。在一个实施例中，列解码器和列I/O电路被折叠在存储器阵列下面，但是行地址解码器电路保留在阵列之外。在另一个实施例中，列电路在阵列下面，而行解码器的中心部分被折叠在阵列下面(其中不与列电路发生冲突)。这给出了在角落上具有小的行电路“标签”的布局，如图9(c)所示。这些标签可以与其它存储器阵列的标签相互交叉，使四个(或更多)阵列紧密座落在一起，如图9(d)所示。其它各种在阵列下面部分折叠解码器的方案对于本领域技术人员是显而易见的。
如同前面段落所暗示的，本发明的现场可编程非易失存储器包括将存储器芯片构成为几个更小子阵列，而非单一大阵列。子阵列给出三个重要好处：(1)它们允许简单模块层解决冗余的方法；(2)它们增加了操作速度；(3)它们降低了操作功率。子阵列冗余可以相当直接。如果最终产品是具有(假如)8N位存储器，很容易在模具上建立九个子阵列，每个包括N位。然后九个子阵列之一可能有缺陷，而模具仍然可以配置和作为8N位存储器销售，通过简单地将缺陷子阵列旁路。
将存储器分成子阵列也增加了速度；这是因为导体更短(减少了它们的电阻)，和每个导体附加了更少的存储器单元(减少了电容)。因为延迟与阻抗和电容的乘积成正比，截短导体长度一般就截短延迟四倍。因此子阵列减少了延迟，即增加了速度。
子阵列也提供了降低功率操作。因为功率的重要元件是对存储器阵列中导体充电和放电的电容，减少导体电容将减少功率消耗。截短导体长度一半就截短电容一半，这截短了电容充电和放电电流一半。
电路设计：行解码和选择
在本发明的实施例中，存储器阵列的行(也称为“字线”)是存储器单元的输入，而列(也称为“位线”)是存储器单元的输出。对存储器单元输入(字线)施加强迫功能，为读取存储器单元输出(位线)的结果被检测，同时为写入对存储器单元输出施加另一个强迫功能(由此强迫该单元两个端子)。用于本发明的强迫功能可以是电压源，电流源，波形发生器(高阻抗或低阻抗的)，充电分组，或其它驱动激励。
为不含糊地访问每个单独存储器单元，为读取或写入，从行线路穿过存储器单元到列线路建立唯一的电路路径。唯一性要求的结果是所有行线路不能同时被驱动；而可以通过考虑图8(b)来了解。图8(b)中的行线(字线)在导体层1、3、5、7上。列线(位线)在导体层2、4、6上。回忆图8表示存储器单元柱体单一垂直层叠；其是单一行和单一列的物理交叉。图8(b)的图为容易观察表示间隔开的导体，但是实际上它们被一个一个向上层叠。
假设同时驱动所有字线，例如，假设导体层1、3、5、7被强迫到高电压。没有到电路输出上的清楚电路路径(在位线上，即导体层2、4、6)，所以不能确定存储器单元的内容。例如，假设检测电路确定导体2是高电压；这意味着什么？这意味着或者导体1和导体2之间的存储器单元被编程为低阻抗状态，或者导体2和导体3之间的存储器单元被编程为低阻抗状态。这两个可能性的任何一个都建立了从高电压源(字线)到导体2上位线的电路路径。但是不幸地是不能确定这些可能性的哪一个事实上为真：没有到导体2的唯一电路路径。而且对于其它两个位线，导体4和导体6，情况也是这样。
因此所有字线不能同时驱动；这产生了到存储器阵列输出不唯一的电路路径。一种直接解决方法是只驱动单一字线，使其它字线不驱动。这在图10(a)中图示。行解码器70选择是否沿该行的任何字线应当启动。而四个层选择信号选择在所选择的行中哪个导体层字线被启动。除了一个层选择信号外的所有信号在不选择条件下(例如，低电压)，而仅仅一个层选择信号在选择条件下(例如，高电压)。因此只有一个字线被驱动，而其它三个不驱动。
图10(a)中的设计清楚地建立了到阵列输出的唯一路径。假设选择导体5上的字线，并且假设检测电路确定导体4是高电压。导体4只有两个方法到高电压：一个是通过导体3和导体4之间的存储器单元71，另一个是通过导体4和导体5之间的存储器单元72。由于导体5被驱动而导体3不驱动，唯一存在的电路路径是从导体5上的字线穿过导体5和导体4之间的存储器单元72出到导体4上的位线。如果导体4是被检测为高电压，则该存储器单元被编程为逻辑零；反之该存储器单元是逻辑一。
但是，图10(a)的设计成本高；它包括存储器阵列中对于每个字线层的开关晶体管。如果在阵列中有大量垂直层(例如，十六层存储器柱体，需要九个字线导体层和八个位线导体层)，开关晶体管消耗了许多硅面积。这减弱了模具效率，使成本升高和密度降低。
可是，我们看出图8(b)中模糊度上升，因为到每个位线有两个路径：一个来自直接在下面的导体层上的字线，而一个来自直接在上面的导体层上的字线。为避免含糊，所有我们必须要做的是保证两个可能路径中只有一个被启动。这可以通过将字线分成组容易地实现：“第一组”和“第二组”。在导体层导体1、导体5、导体9、导体13、导体17，…，等上的字线是在第一组，而在导体层导体3、导体7、导体11、导体15、导体19，…，等上的字线是在第二组。关键是只要没有第二组中的其它字线被驱动，同时驱动所有第一组中的字线是绝对安全的，反之也相同(图10(b))。
图10(b)中的电路只包括了两个开关晶体管75和76，而不管在阵列中垂直存储器单元层的数量。第一组字线有一个开关晶体管，和第二组字线有一个开关晶体管。同样地，有两个组选择信号，其决定驱动两个字线组的哪个。在芯片中存储器单元垂直层越多，图10(b)与图10(a)相比节省越多。
假设第一组选择信号为选择条件(高电压)而第二组选择信号为不选择条件。则驱动层导体1，导体5，导体9，…，等上的字线，同时不驱动导体3，导体7，导体11，…，等上的字线。到导体2上的位线只有一个(唯一)路径：这是从导体1穿过导体1和导体2之间的存储器单元到导体2层上的位线的路径。从导体3穿过导体3和导体2之间的存储器单元到导体2上的另一个可能路径被禁止，因为导体3是第二组字线中并且不被驱动。
电路设计：列解码和选择
两组字线结构(图10(b))的结果是每个位线具有其上的一个存储器单元行被选择。因此，如果有N个导体层用于位线，每个所选择的列将同时读取或写入存储器的N位。本发明的一个实施例确实在每个所选择列中一次读取(和/或写入)N位。另一个实施例引入了列多路通道电路，该电路减少了同时访问的存储器单元数量。
图11表示了另一个实施例。给每个位线提供其自己的开关晶体管例如晶体管77和78；这些晶体管连接一个位线到双向I/O总线，如果给列被选择。在读取工作期间，位线驱动I/O总线，但在写入工作期间，I/O总线驱动位线。如果有N层位线，就有N个开关晶体管和N个I/O总线导体。I/O总线导体连接到外围电路，包括检测放大器(用于读取)和写入驱动器(用于写入)。
列选择电路比图10(b)所示的行选择电路成本高的多。因为必须有对于每个位线有一个开关晶体管，如果垂直层叠的存储器单元层越来越多，位线也越来越多，因此开关晶体管越来越多。
这样列选择电路将比行选择电路消耗更多硅面积，特别是当有大量存储器单元垂直层堆叠时。这就是为什么最好将列选择电路折叠在存储器阵列下面，而不是折叠行选择电路，如同图9(c)所示：列电路大得多。实际上，将列电路折叠在存储器阵列下面而完全不试图将行选择电路折叠在下面是合理的设计决定。折叠列选择有好处。
预充电存储器阵列
在许多情况下认为在开始读取或写入操作之前应当将所有字线“预充电”到一个中间电平例如供电电源电压的0.5倍，并且将位线“预充电”到一个中间电压电平例如供电电源电压的0.4倍。
电路设计：读取/写入外围电路
本发明的几个实施例利用状态改变元件，该元件的不同状态对应阻抗的不同数值。例如，电介质击穿反熔丝具有两个状态：非常低阻抗和非常高阻抗，其中阻抗变化达几个数量级。这样的实施例可以使用“电流模式读取”和“电压模式或电流模式写入”，如同下面所解释的。
当读取这种存储器单元时，电流源可以选择作为强制功能驱动字线。如果存储器单元被编程(电介质被击穿，因此为低阻抗)，该驱动电流将通过存储器单元到位线上。所选择的位线将被导通到(双向)I/O线上，并且驱动电流将被传递到I/O线上。连接到I/O线的检测放大器检测是否驱动电流被传递到I/O线上。如果是，被读取的该单元包含“逻辑一”，如果不是，该单元包含“逻辑零”。
电流模式读取的重要优点是速度：通过强制和检测电流(而非电压)，可以避免对高电容字线和位线充电和放电的需要，所以字线和位线不在大电压偏移上来回摆动，这加速了读取操作。因此在本发明的许多实施例中优选电流模式读取。
在写入存储器单元的一个实施例中，可以选择电压源作为强制功能驱动字线。另外，双向I/O总线可以由另一个电压源驱动。该I/O总线连接到所选择列的位线(借助列选择开关晶体管)，所以所选择存储器单元(在所选择字线和所选择位线交叉点上)将由两个电压源驱动：一个在字线上，另一个在I/O总线上。这两个电压源之间的大电压差将直接施加到所选择存储器单元上，实现电压模式(在字线和位线上的大电压偏差)写入。
尽管电压模式写入比较慢，由于它必须对高电容字线和位线充电和放电，它仍然在本发明的某些实施例中被选用。电压模式写入如果需要可以提供通过存储器单元的非常高电流，这利对于状态改变元件的几个实施例有利，例如非晶体半导体反熔丝。在电压模式写入的某些实施例中，可以优选将最大电流限制到特定数值。限制最大电流的一个可能好处是减少了沿阵列导体上的IR电压降效果，以保证将一致的编程能量分配给每个存储器单元，而不取决于该单元在阵列中的位置。一致编程能量可能很重要，因为某些状态改变元件材料特性或许对编程能量检测。
在一些实施例中，编程状态改变元件所必需的电压可能超过外围晶体管的电压容量。当晶体管缩小为小尺寸时(例如，沟道长度小于0.2微米)尤其如此。在这些情况下，外围电路可以被设计得在写入周期期间行解码器根据+V伏供电电源工作，而列解码器和列I/O电路和写入数据驱动器根据-V伏供电电源工作。该设计在被写入的存储器单元上施加了2×V伏的电压差((+V)-(-V)＝2×V)，同时在任何一个晶体管上施加了最多V伏的电压。
因此，公开了允许制造得非常高密度阵列的垂直层叠非易失存储器。

Claims (94)

1.一种存储器单元，包括：
一个引导元件，用于提供在一个方向上流过引导元件的增强电流；
一个状态改变元件用于保持被编程的状态，与引导元件串联连接以便引导元件和状态改变元件提供两个端子单元；
该引导元件和状态改变元件相互垂直对准。
2.权利要求1所定义的单元，其中引导元件由多晶硅制造。
3.权利要求2所定义的单元，其中多晶硅是掺杂的以便形成一个二极管。
4.权利要求1所定义的单元，其中引导元件是金属半导体肖特基二极管。
5.权利要求1所定义的单元，其中引导元件是结型场效应二极管具有连接到源极和漏极区之一的一个栅极。
6.权利要求1所定义的单元，其中引导元件是场效应二极管具有绝缘的连接到源极和漏极区之一的栅极。
7.权利要求1所定义的单元，其中引导元件是一个PN结型二极管，由非结晶半导体形成。
8.权利要求1所定义的单元，其中引导元件是一个齐纳二极管。
9.权利要求1所定义的单元，其中引导元件是一个雪崩二极管。
10.权利要求1所定义的单元，其中引导元件是一个隧道二极管。
11.权利要求1所定义的单元，其中引导元件是一个四层二极管(SCR)。
12.权利要求1所定义的单元，其中状态改变元件是一个反熔丝。
13.权利要求12所定义的单元，其中反熔丝由多晶硅形成。
14.权利要求12所定义的单元，其中反熔丝包括硅二极管。
15.权利要求1所定义的单元，其中状态改变元件是一个电介质击穿反熔丝。
16.权利要求1所定义的单元，其中状态改变元件是多晶硅半导体反熔丝。
17.权利要求1所定义的单元，其中状态改变元件是非结晶半导体反熔丝。
18.权利要求1所定义的单元，其中状态改变元件是一个金属灯丝电迁移熔丝。
19.权利要求1所定义的单元，其中状态改变元件是一个多晶硅电阻熔丝。
20.权利要求1所定义的单元，其中状态改变元件利用陷波感应迟滞。
21.权利要求1所定义的单元，其中状态改变元件利用一个铁电体电容。
22.权利要求1所定义的单元，其中状态改变元件利用霍尔效应器件。
23.权利要求1所定义的单元，其中引导元件包括一个二极管而状态改变元件包括一个反熔丝，和其中二极管能够承载足够改变反熔丝状态的电流。
24.权利要求1所定义的单元，其中引导元件包括一个再结晶半导体。
25.权利要求1所定义的单元，其中引导元件和状态改变元件包括非结晶硅。
26.权利要求1所定义的单元，其中该单元端子之一连接到字线。
27.权利要求26所定义的单元，其中该单元的其它端子连接到位线。
28.一种存储器单元包括：
一个柱体，通常具有矩形截面并且具有在一端上的引导元件和位于柱体另一端的状态改变元件，该引导元件在一个方向上更容易导通电流，该状态改变元件用于记录一个状态。
29.权利要求28所定义的存储器单元，其中引导元件包括一个二极管。
30.权利要求29所定义的存储器单元，其中二极管包括多晶硅。
31.权利要求28所定义的存储器单元，其中状态改变元件包括一个电介质击穿反熔丝。
32.权利要求31所定义的存储器单元，其中反熔丝包括一个硅二极管层，夹心在两层多晶硅之间。
33.权利要求28所定义的存储器单元，具有与引导元件接触的第一导体，第一导体具有近似等于矩形截面一边的宽度。
34.权利要求33所定义的存储器单元，具有与状态改变元件接触的第二导体，第二导体具有近似等于矩形截面另一个边的宽度。
35.一种存储器阵列，包括：
第一组间隔分开，平行，基本上同平面的导体；
第二组间隔分开，平行，基本上同平面的导体，通常垂直配置在第一导体之上并且与第一导体间隔分开，所述第一和第二导体通常相互正交；和
一组第一存储器单元，每个单元配置在第一导体之一和第二导体之一之间并且位于第一导体垂直投影与第二导体交叉处，该单元垂直对准至少导体之一。
36.权利要求35所定义的阵列，其中该单元与第一和第二导体两者对准。
37.权利要求35所定义的阵列，其中这些单元各包括一个引导元件和一个状态改变元件。
38.一种存储器阵列包括：
第一组间隔分开，平行，基本上同平面的导体；
第二组间隔分开，平行，基本上同平面的导体，通常垂直配置在第一导体之上并且与第一导体间隔分开，所述第一和第二导体通常相互正交；和
一组第一存储器单元，每个单元配置在第一导体之一和第二导体之一之间并且位于第一导体垂直投影与第二导体交叉处，
第三组间隔分开，平行，基本上同平面的导体，通常垂直配置在第二导体之上并且与第二导体间隔分开，该第三导体在与第一导体相同方向走向
一组第二存储器单元，每个单元配置在第二导体之一和第三导体之一之间并且位于第二导体垂直投影与第三导体交叉处。
39.权利要求38所定义的阵列，其中第一单元和第二单元相互垂直对准。
40.权利要求38所定义的阵列，其中第一单元和第二单元相互交错。
41.权利要求38所定义的阵列，其中第一单元和第二单元的每个包括一个引导元件和一个状态改变元件。
42.权利要求38所定义的阵列，其中第一和第二单元的引导元件连接到第二导体。
43.权利要求41所定义的阵列，其中第一和第二单元的状态改变元件连接到第二导体。
44.权利要求38所定义的阵列，其中第一和第二单元具有通常矩形截面。
45.权利要求38所定义的阵列，其中第一和第二单元包括多晶硅和硅二极管。
46.权利要求38所定义的阵列，其中第一和第二单元包括多晶硅。
47.权利要求38所定义的阵列，其中该阵列制造在一个硅衬底上。
48.权利要求47所定义的阵列，包括第一接触，从第二导体之一向衬底上的第一区域延伸。
49.权利要求48所定义的阵列，包括第二接触从第一导体之一向衬底上的第二区域延伸。
50.权利要求38所定义的阵列，其中第一和第二导体包括一个耐熔金属。
51.权利要求50所定义的阵列，其中耐熔金属是钨。
52.权利要求38所定义的阵列，其中第一和第二导体是硅化物。
53.一种存储器阵列，包括：
在层1、2、3、4…上的一组导体，其中层是平行和间隔分开的，奇数层1、3…上的导体在第一方向走向，偶数层2、4…上的导体在通常与第一方向垂直的第二方向上走向，和
一组存储器单元，具有一个输入端子和输出端子，该单元配置在每层1、2、3、4…上的导体之间。
54.权利要求53所定义的阵列，其中该单元的输入端子连接到奇数层1、3…上的导体上，而该单元的输出端子连接到偶数层2、4…上的导体上。
55.权利要求53所定义的阵列，其中该单元的输出端子连接到奇数层1、3…上的导体上，而该单元的输入端子连接到偶数层2、4…上的导体上。
56.权利要求54或55所定义的阵列，其中该单元包括在输入和输出端子之间耦合的一个引导元件和一个状态改变元件。
57.权利要求53所定义的阵列，其中该单元具有通常矩形的截面。
58.权利要求53所定义的阵列，其中该单元包括硅和硅二极管。
59.权利要求53所定义的阵列，其中层1、3…的导体相互垂直对准。
60.权利要求53所定义的阵列，其中层1、3…和层2、4…中的一组上的导体在垂直方向交错。
61.权利要求53所定义的阵列，其中该导体包括多晶硅。
62.权利要求53所定义的阵列，其中该阵列制造在硅衬底上。
63.权利要求62所定义的阵列，包括一个接触从奇数层1、3…上的导体之一向衬底延伸。
64.权利要求62所定义的阵列，包括一个接触从偶数层2、4…上的导体之一向衬底延伸。
65.权利要求62所定义的阵列，包括至少一个从最高层向衬底延伸的接触。
66.权利要求62所定义的阵列，其中一个接触由几个接触组成，每层有一个。
67.一种用于制造存储器阵列的加工方法包括：
(a)形成导电材料的第一层；
(b)形成多个第二层用于限定第一层上的存储器单元；
(c)将第二层构图成为多个平行、间隔分开的带；
(d)与第二层形成的带对准蚀刻第一层；
(e)在第一层材料的带和第二层形成的带之间形成绝缘材料；
(f)在绝缘材料和第二层形成的带上形成导电材料的第三层；
(g)形成多个第四层用于限定第二层的存储器单元；
(h)将第四层构图成为多个平行分开的带，该带由第四层形成通常垂直于第一层形成的带走向；
(i)蚀刻第三层和由第二层形成的带与第四层形成的带对准。
68.权利要求67所定义的加工方法，包括在第四层形成的带上形成导电材料的第五层；
构图第五层形成多个平行间隔分开的导体，通常垂直于第四层上的带走向；和
对准该导体蚀刻第四层形成的带，由此限定另外的存储器单元。
69.权利要求67所定义的加工方法重复步骤(a)到(i)。
70.权利要求69所定义的加工方法，具有权利要求68的步骤。
71.权利要求67所定义的加工方法，重复步骤(a)到(i)多次。
72.权利要求71所定义的加工方法，具有权利要求68的步骤。
73.权利要求67所定义的加工方法，其中一种电介质被应用并且在第一层蚀刻之后和第三层形成之前出现平整步骤。
74.权利要求73所定义的加工方法，其中平整包括化学-机械抛光。
75.权利要求67所定义的加工方法，包括沉积一个绝缘层并且对其再次蚀刻以平整该结构，和在步骤(d)和(e)之间开孔到第二层形成带的电接触。
76.权利要求67所定义的加工方法，其中多个第二层和多个第四层各包括多晶硅和硅二极管层。
77.权利要求76所定义的加工方法，其中多晶硅是掺杂的以便每个存储器单元包括一个二极管。
78.权利要求76所定义的加工方法，其中每层中的硅二极管形成一个反熔丝的一部分。
79.权利要求67或73所定义的加工方法，其中平整步骤出现在第二层形成之后和第三层形成之前。
80.权利要求79所定义的加工方法，其中通过化学-机械抛光执行平整。
81.权利要求79所定义的加工方法，包括在平整之后形成开孔用于接触。
82.权利要求76所定义的加工方法，其中多晶硅在低温下利用化学汽相沉积沉积。
83.权利要求67所定义的加工方法，包括在形成第一层之后和形成第二层之前沉积一个阻挡金属层。
84.权利要求67所定义的加工方法，包括在形成第三层之后和形成第四层之前沉积一个阻挡金属层。
85.权利要求67所定义的加工方法，其中制造包括接触的制造和其中接触开孔制造后将硅沉积到开孔中。
86.权利要求67所定义的加工方法，包括使用离子注入硅。
87.权利要求67所定义的加工方法，包括使用原位掺杂硅。
88.权利要求87所定义的加工方法，其中硅是利用LPCVD沉积的。
89.权利要求87所定义的加工方法，其中硅是利用PECVD沉积的。
90.权利要求87所定义的加工方法，其中硅是利用PVD沉积的。
91.权利要求87所定义的加工方法，其中硅是利用UHVCVD沉积的。
92.一种存储器包括：
一个单晶硅硅衬底，具有形成在衬底上的行地址解码器和列地址解码器和输入/输出电路；
一个存储器阵列，具有形成在衬底上的多个列导体和行导体，并且电连接到解码器和输入/输出电路；
该阵列包括第一组层，每个具有间隔分开平行通常同平面的行导体；
第二组层，与第一组层交织，每个具有间隔分开平行通常同平面的列导体，通常与行导体垂直；
和每层之间的多个存储器单元，每个单元连接到行导体之一和列导体之一。
93.权利要求92定义的存储器，其中列解码器和输入/输出电路被折叠在该阵列之下并且连接到列导体。
94.权利要求92定义的存储器，其中该阵列被分成多个子阵列。
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US6185122B1 (en) 2001-02-06
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WO2000030118A1 (en) 2000-05-25
US6034882A (en) 2000-03-07
CN1213437C (zh) 2005-08-03
JP3639786B2 (ja) 2005-04-20
CN1691339A (zh) 2005-11-02
JP2002530850A (ja) 2002-09-17
TW425561B (en) 2001-03-11
AU3874599A (en) 2000-06-05

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