CN1341278A - 在有源的电路之上敷金属衬垫 - Google Patents

在有源的电路之上敷金属衬垫 Download PDF

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CN1341278A
CN1341278A CN00804109A CN00804109A CN1341278A CN 1341278 A CN1341278 A CN 1341278A CN 00804109 A CN00804109 A CN 00804109A CN 00804109 A CN00804109 A CN 00804109A CN 1341278 A CN1341278 A CN 1341278A
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metal level
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CN1211847C (zh
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S·L·斯卡拉
S·波斯拉
E·德穆伊宗
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Koninklijke Philips NV
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Abstract

在半导体晶片中以可靠和有效的成本方式在有源的电路之上形成金属粘合衬垫(110、510、610)。按照本发明的一个实施例,在半导体晶片中金属粘合衬垫(110)在电路之上形成。金属层(230)在电路和金属粘合衬垫(110)之上形成,并且在金属层之上形成光刻胶掩模(340)图案。金属层(230)被腐蚀,并且未用光刻胶遮住的金属层部分被除去。以此方式,在衬垫部位仅仅使用一个附加的掩模步骤可以形成附加的金属,并且通过在随后的接线粘合处理中有用的衬垫上提供一个金属垫子,在衬垫部位厚的金属改善码片的可靠性。

Description

在有源的电路之上敷金属衬垫
发明领域
本发明通常涉及半导体器件和它们的制作，尤其是涉及半导体器件和包括用于形成电路的它们的制造技术。
发明背景
近来半导体工业已经经历技术的进步，在电路密度和复杂性方面允许显著的增加，并且同样地在能量消耗和封装尺寸方面显著的减少。伴随这些进步，不时地推动增加对半导体器件更快地操作、成本减少和较高的可靠性的需要。形成在日益小的面积上具有越来越密集的电路结构的能力，和在一个半导体薄片上放置更多半导体晶片的能力对于满足发展技术的这些及其他需要尤其重要。
半导体制造的一个方面包括在一个码片上形成粘合衬垫。该粘合衬垫通常放置在没有基础的电路的半导体晶片的边缘，并且用于为半导体薄片随后的接线粘合。但是，为了减少码片的尺寸，希望在有源的电路之上形成粘合衬垫。通过减少码片的尺寸，在给定的面积中可以粘合于半导体薄片更多的码片。
以这样的努力去增加电路和模具密度，半导体器件制造在设备中的电路之上和接近于电路形成金属衬垫已经遇到困难。一个这样的困难包括可靠的产品的生产。可靠性参与可以防止在有源的电路之上放置粘合衬垫。例如，现有的用于在电路之上形成衬垫的方法可以在基础的金属间氧化物(IMO)层产生裂缝。此外，满足可靠性目的的那些方法常常太昂贵而无利可图。
一种用于在有源的电路之上制造可靠的粘合衬垫的方法包括：增加一个附加的足够厚的钝化层，和一个另外的金属层作为用于接线粘合的金属。附加的IMO层和金属层两者应该足够厚以吸收和/或分配粘合力，用这样的方法不使基础的IMO层裂开。已经发现用于增加的钝化和金属层两者的厚度为1-2微米防止IMO断裂。但是，作为需要的二个掩模步骤添加厚的钝化层和厚的金属层是很昂贵的，一个用于经由腐蚀以及一个用于金属腐蚀。此外，对于厚的层的生产量是低的，它降低了制造进程的效率，并且导致较高的产品成本。
通过在多金属的码片上留下一个或多个非有源的金属层已经完成获得一个厚的IMO层。通过留下一个或多个非有源的金属层可以容易地实现厚度大于2微米的IMO。但是，也希望形成厚的敷金属衬垫，但是难以完成，因为最高的金属层的设计规则和工序典型地禁止使该层显著地厚于1微米。与现有的用于在有源电路之上粘合有关的方法的这些及其他问题阻碍了半导体技术的发展和进步。
发明概述
本发明提出了涉及在有源电路之上形成金属粘合衬垫的半导体器件的制造，并且以多个实施和应用举例说明，其中一些在下面概述。
按照本发明的一个实施例，在半导体晶片的电路面上厚的金属在金属粘合衬垫上形成。首先，金属粘合衬垫被在半导体晶片的电路面上的电路之上形成。其次，在电路面之上形成金属层，并且在金属层之上用光刻胶形成的图案遮住。电路面然后被腐蚀，并且未用光刻胶遮住的金属层部分被除去。剩余的光刻胶然后被除去，在金属粘合衬垫之上留下厚的金属。
在本发明的另一个实施例中，金属粘合衬垫被在半导体晶片上形成。金属粘合衬垫具有第一金属衬垫层，在第一金属衬垫层之上具有TiN扩散层，以及在TiN扩散层之上具有第二金属衬垫层。钝化层在该衬垫之上形成，并且随后被腐蚀以暴露第二金属衬垫层。
在本发明的再一个实施例中，一个系统被安排用于制造在有源的电路之上具有金属粘合衬垫的半导体晶片。第一金属沉积方案适合于在电路面上附着金属粘合衬垫，以及第二金属沉积方案适合于在电路面之上附着金属层。在附着金属层以后，光刻胶沉积方案适合于在金属层之上形成光刻胶掩模图案，并且腐蚀方案适合于腐蚀该电路面，以及除去未用光刻胶遮住的金属层部分。当电路面已经被腐蚀时，光刻胶除去方案适合于除去该光刻胶。
上述本发明的概述不是意欲描述每个说明的实施例或者本发明的每个实施。附图和随后的详细说明进一步详细地举例说明这些实施例。
附图的简要说明
连同伴随的附图，考虑到下面本发明的各种各样的实施例的详细说明，可以更彻底地理解本发明，其中图1-6举例说明按照本发明的实施例和方面的衬垫/码片制造的各个阶段，尤其是：
图1是在电路之上形成的金属粘合衬垫；
图2是经历附加处理的图1的金属粘合衬垫；
图3是经历附加处理的图2的金属粘合衬垫；
图4是经历附加处理的图3的金属粘合衬垫；
图5是经历附加处理的图1的金属粘合衬垫；和
图6是一个金属粘合衬垫。
虽然本发明会接纳各种各样的修改和替换形式，具体地已经在附图中通过例子示出，并且将详细描述。但是，应该明白本发明的目的不限于所述的特定的实施例。相反地，本发明的目的是覆盖所有的落在由所附权利要求书限定的本发明的精神和范围内的修改、等效和替换。
发明的详细说明
本发明被认为适用于许多不同种类的半导体器件，并且本发明已经被认为是特别适合于要求或者受益于在有源的电路之上形成金属粘合衬垫的弹抛片及其他类型设备。虽然本发明没有必要限于这样的设备，通过利用上下文讨论各种各样的例子可以理解本发明的各个方面。
结合本发明的实施例，一种方法和系统适宜于在半导体晶片中在有源的电路之上形成金属粘合衬垫，同时保持该码片的可靠性以及以有效成本制造工艺这样做。按照本发明的一个具体地的实施例，金属层被在半导体晶片的电路面上形成，半导体晶片具有在电路面的电路上形成的金属粘合衬垫。光刻胶掩模在金属层上形成图案，并且金属层被腐蚀。用这种方式光刻胶形成图案，以便在金属粘合衬垫之上掩盖该金属层，并且允许大多数或者所有剩余的金属层被腐蚀。一旦金属层被腐蚀，光刻胶被除去。各种各样的沉积方案，腐蚀布置包括腐蚀容器，以及典型地可用的光刻胶沉淀方案可用于实施此处所述的处理。用这样的方式，仅仅利用一个另外的腐蚀步骤，厚的金属被在金属粘合衬垫上形成，改善在有源的电路之上形成粘合金属衬垫的可靠性。本发明可以实现的一个可靠性改善是在随后接线粘合处理的时候防止金属间Al/Au的形成。
图1-4示出按照本发明的另一个在半导体晶片的制造中的顺序处理步骤具体的实施例。图1示出在一个半导体晶片的电路面105之上形成的金属衬垫110，在金属衬垫110的一部分和电路面105之上使用常规的半导体晶片制造法形成的钝化层。例如，金属衬垫110可以首先在码片的电路面之上附着一层诸如铝的金属而形成，然后在该金属层之上形成第一掩模图案，诸如光刻胶掩模。第一光刻胶被形成图案，使得它掩盖金属层部分，如示出的金属衬垫110。在光刻胶被形成图案以后，码片被腐蚀，并且金属衬垫110被留下。第一光刻胶被除去，并且钝化层被在码片的电路面上形成。然后钝化层以第二光刻胶形成图案，使得示出的钝化层120部分被掩盖。如图1所示，然后码片被腐蚀，并且金属衬垫110被暴露。
在图2中，第二金属层230在码片的电路面之上形成，该码片包括金属衬垫110和钝化层120。第二金属层230例如可以包括铝或者其他适当的粘合材料。如图3所示，光刻胶340被在金属衬垫110以及第二金属层230之上形成。光刻胶340掩盖在金属衬垫110之上的第二金属层230部分。如图4所示，在形成光刻胶340以后，码片被腐蚀，并且第二金属层230残留在金属衬垫110之上。然后光刻胶340被除去，在金属衬垫110之上留下厚的金属230。
按照本发明的一个更特别的实施例，使用粘合具有在有源的电路形成之上多个金属衬垫集成电路的弹抛片制造半导体器件，其中以结合图1-4所述的方式，具有厚的金属在衬垫之上形成。弹抛片经由厚的金属和多个衬垫被接线粘合于封装衬底。该金属足够厚防止在接线粘合处理的时候形成金属间Al/Au。
在本发明的另一个实施例中，金属衬垫被在有源的电路之上形成，包括材料如TiN的阻扩散剂层在金属衬垫之上形成，并且第二金属层被在金属衬垫和TiN层之上形成。图5示出了一个在半导体晶片上形成这样的结构的例子。以诸如上面结合图1所述的方式在码片上形成金属衬垫510和钝化层520。TiN层550被在钝化层520的暴露区域以及金属衬垫510之上形成。TiN层的厚度被选择充分地减少或者防止在随后的接线粘合处理的时候形成金属间Al/Au。在一个实施例子中，TiN层大约0.5微米厚，在另一个实施中，TiN层大约1微米厚。一旦TiN层550被形成，第二金属层530被在TiN层上形成。第二金属层530的厚度被选择去提供要求的规格用于码片将使用的特别的应用。在一个应用例子中，第二金属层大约3微米厚。TiN层的添加增加了好处，包括改善在有源的电路之上粘合的可靠性。
在图5中，TiN和第二金属层可以以各种各样的方式形成。例如，可以使用结合图1-4所述的光刻胶掩模和随后的腐蚀处理。在一个实施例中，TiN层使用常规的光刻胶掩模和腐蚀处理形成，其中光刻胶掩模被在TiN上形成，并且在形成第二金属层530之前TiN被腐蚀。然后在码片和TiN层550之上形成第二金属层530。光刻胶掩模被在第二金属层530之上形成，第二金属层530然后被腐蚀去形成图案的金属层，如图5所示。在另一个实施例中，TiN层被在码片的电路面505之上形成，并且第二金属层被在TiN层上形成。光刻胶掩模被在第二金属层之上形成图案，并且利用该掩模第二金属层和TiN层两者被腐蚀。产生的结构在图5中示出。
按照本发明的另一个实施例，具有阻扩散剂的金属粘合衬垫被形成足够的衬垫去防止在随后的接线粘合处理的时候金属间Al/Au的形成。参考图6，第一衬垫金属610被在半导体晶片的电路面605之上形成。TiN阻扩散剂650被在第一衬垫金属610之上形成，并且第二衬垫金属660被在TiN阻扩散剂650之上形成。用这样的方式，当保持可靠性和促进在有源的电路之上形成金属粘合衬垫时，金属粘合衬垫被形成具有大约正常金属粘合衬垫厚度。
图6的衬垫可以使用各种各样的掩模和腐蚀步骤形成，诸如在上面结合图5论述的。例如，第一衬垫金属、阻扩散剂，以及第二衬垫金属对于每层可以独立使用掩模和腐蚀步骤形成。换句话说，掩模和腐蚀步骤可以通过同时在上面掩模和腐蚀两个或更多层配合施行。
虽然参考几个特别的实施例已经描述了本发明，那些本领域技术人员将公认，不脱离本发明的精神和范围，此外可以进行很多的变化，这在下面的权利要求中阐述。

Claims (10)

1.一种用于制造具有电路的半导体晶片的方法，该方法包括：
在电路之上形成一个金属粘合衬垫；
在电路和金属粘合衬垫之上形成一个金属层；
在金属层之上形成光刻胶掩模图案；和
腐蚀该金属层，并且除去未用光刻胶遮住的金属层部分。
2.根据权利要求1的方法，进一步包括在形成该金属层之前在金属粘合衬垫之上形成一个阻扩散层。
3.根据权利要求2的方法，其中阻扩散层包括TiN。
4.根据权利要求2的方法，其中在金属粘合衬垫之上形成一个阻扩散层包括在之上形成阻扩散层的层并延伸超过金属粘合衬垫，以及其中腐蚀金属层包括除去未用光刻胶遮住的阻扩散层部分。
5.根据权利要求3的方法，其中在金属粘合衬垫之上形成阻扩散层包括在电路面之上形成金属层之前形成阻扩散层的层并延伸超过金属粘合衬垫，该方法进一步包括：
在阻扩散剂层之上形成光刻胶掩模图案；
腐蚀阻扩散剂，并且除去未用光刻胶遮住的阻扩散剂层部分，和
除去光刻胶掩模。
6.根据权利要求1的方法，其中形成光刻胶掩模图案包括在粘合衬垫之上附着光刻胶材料，以及其中腐蚀金属层和除去未用光刻胶遮住金属层部分包括除去未在粘合衬垫之上的金属层部分。
7.根据权利要求1的方法，其中形成金属粘合衬垫包括形成多个金属粘合衬垫。
8.根据权利要求7的方法，其中形成光刻胶掩模图案包括在多个粘合衬垫之上附着光刻胶材料，以及其中腐蚀金属层和除去未用光刻胶遮住金属层部分包括除去未在粘合衬垫之上的金属层部分。
9.根据权利要求1的方法，其中在粘合衬垫之上的金属层具有足够的厚度，在随后的接线粘合处理的时候防止金属间Al/Au的形成。
10.根据权利要求2的方法，其中阻扩散剂层具有足够的厚度，在随后的接线粘合处理的时候防止金属间Al/Au的形成。
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US6358831B1 (en) * 1999-03-03 2002-03-19 Taiwan Semiconductor Manufacturing Company Method for forming a top interconnection level and bonding pads on an integrated circuit chip
US6613671B1 (en) * 2000-03-03 2003-09-02 Micron Technology, Inc. Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby
DE102007050610A1 (de) * 2006-10-24 2008-05-08 Denso Corp., Kariya Halbleitervorrichtung, Verdrahtung einer Halbleitervorrichtung und Verfahren zum Bilden einer Verdrahtung
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US20200212536A1 (en) * 2018-12-31 2020-07-02 Texas Instruments Incorporated Wireless communication device with antenna on package
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Family Cites Families (13)

* Cited by examiner, † Cited by third party
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US4950623A (en) * 1988-08-02 1990-08-21 Microelectronics Center Of North Carolina Method of building solder bumps
JP3053675B2 (ja) * 1991-09-09 2000-06-19 ローム株式会社 半導体装置およびその製造方法
US5316976A (en) * 1992-07-08 1994-05-31 National Semiconductor Corporation Crater prevention technique for semiconductor processing
US5334804A (en) * 1992-11-17 1994-08-02 Fujitsu Limited Wire interconnect structures for connecting an integrated circuit to a substrate
US5677203A (en) * 1993-12-15 1997-10-14 Chip Supply, Inc. Method for providing known good bare semiconductor die
US5661081A (en) * 1994-09-30 1997-08-26 United Microelectronics Corporation Method of bonding an aluminum wire to an intergrated circuit bond pad
US5559056A (en) * 1995-01-13 1996-09-24 National Semiconductor Corporation Method and apparatus for capping metallization layer
US5808360A (en) * 1996-05-15 1998-09-15 Micron Technology, Inc. Microbump interconnect for bore semiconductor dice
US5693565A (en) * 1996-07-15 1997-12-02 Dow Corning Corporation Semiconductor chips suitable for known good die testing
JP3413020B2 (ja) * 1996-07-17 2003-06-03 株式会社東芝 半導体装置の製造方法
US5795818A (en) * 1996-12-06 1998-08-18 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection and method
US6082610A (en) * 1997-06-23 2000-07-04 Ford Motor Company Method of forming interconnections on electronic modules
US6451681B1 (en) * 1999-10-04 2002-09-17 Motorola, Inc. Method of forming copper interconnection utilizing aluminum capping film

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