CN1433573A - 具有窗口盖的、无引线的半导体产品封装装置及其封装方法 - Google Patents

具有窗口盖的、无引线的半导体产品封装装置及其封装方法 Download PDF

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CN1433573A
CN1433573A CN01807636A CN01807636A CN1433573A CN 1433573 A CN1433573 A CN 1433573A CN 01807636 A CN01807636 A CN 01807636A CN 01807636 A CN01807636 A CN 01807636A CN 1433573 A CN1433573 A CN 1433573A
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lead
wire
lead frame
packaging system
product packaging
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CN01807636A
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陈东生
张生
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ATS SERVICES Co
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ATS SERVICES Co
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
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    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49139—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture
    • Y10T29/4914—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture with deforming of lead or terminal

Abstract

一种可保存自然资源的、对环境有利的、具有较好的成本－效果比的、无引线的半导体封装装置(1000)，该装置具有优良的机械和电的性能，并且具有最佳的开有窗口的壳体，该壳体专门进行密封并且提供了一种机构，该机构可以观测内部封装的成一体的半导体电路(电路片/电路小片)(40)。在使用模子的专门压缩模制过程中，专门压制而成的和/或弯曲的引线架(30、41)通过聚含材料(12)来进行封装，该模子特别成形成避免现有技术中的普通“过度封装”问题。当外部是接触印刷电路板上的垫的有效可焊接区域时，这种特殊成形的模子有利于从引线架的外部描述内部，因此避免了艰苦的、对环境不利的护罩步骤和去飞边步骤，从而使装置封装过程合理化。压缩模制有效地提供了压缩密封喷口中，而引线架的有效可焊接区域从该喷口进行延伸并且被露出来，因此避免涂有聚合物，该聚合物通过模子专门来装，该聚合物用来封装引线架的内部。引线架专门被冲压和/或变形，从而使它符合特殊半导体产品的电－机械要求。借助于专门冲压和/或弯曲，不再需要引线的现有技术的“半蚀刻”，而该现有技术的“半蚀刻”用来使它符合封装过的半导体产品的电－机械要求。借助于保存自然资源和借助于消除有害材料的副产品可以实现环境改善，而这种有害材料副产品在现有技术的封装技术中被释放出来。

Description

具有窗口盖的、无引线的半导体产品封装装置及其封装方法
相关申请
本申请涉2000年3月30日提交的序列号为No.60/193319的待审U.S.临时专利申请和2000年9月22日提交的序列号为No.09/668423的U.S.非临时专利申请，这两个专利申请是同一申请人，两者的标题是“具有窗口盖的、无引线的半导体产品封装装置及其封装方法”。
技术领域
本发明涉及半导体产品封装和用来生产出该封装半导体产品的制造方法。尤其地，本发明涉及无引线的半导体产品封装和用来制造无引线的封装半导体产品的制造方法。更加尤其的是，本发明涉及无引线的半导体产品封装和用来大批量生产出封装半导体产品的制造方法，而没有采用与浪费时间、对环境不利的相关的技术引线架蚀刻和去飞边技术。
背景技术
为了提供更多的带有必需的功能电路的电子产品的印刷电路板，制造费用成了一个令人关注的问题，为此，半导体产品封装工业已开发出无引线的电路元件产品(也公知为可表面安装的电子产品)，下文中称为“无引线产品”。这种无引线产品，顾名思义，是一种封装的电子产品，该产品不要求将便于插入到一平板上配合孔内的物理引线用作一种机械安装装置，也不作为这一平板上形成电路的电子元件的电气连接。总之，这种无引线产品有助于印刷电路板的制造，并以此免除了将元件引线对电路板上的插入，以及将这些引线对于该电路板的焊接垫的焊接。自从1980年早期以来，无引线技术已被很好地接受为封装电子元件的一个选择。借助于例子，与目前有关的技术工业产品包括“QFN”(Quad FlatNo Lead，registered as JEDEC STD MO 197、198、208、209和220)。当然，在引线型的封装结构中仍然有电子元件功能。
在相关的无引线半导体产品封装技术中，“半蚀刻”技术用来形成引线架，从而产生了相当多的有害材料(如酸废料、金属废料和可能的有机溶剂废料)；并且一种粘结带被用于将该引线架(也公知为“外部I/O”)的有效焊接区域从在模制过程中施加的包装材料上临时遮蔽、以便将这种引线架的有效焊接区域保持在一种非焊接状态，从而产生了过多的带子和可能的有机溶剂废料。在另一个相关的半导体产品包装技术中，该引线架完全由一模制方法来完全封装；并且，引线架的有效可焊接区域必须在一工序中进行去飞边，其中这些部分通过颗粒的高压液状浆来进行清除(即湿消除)，从而除去“过多的封装”，因此产生了相当多的呈聚合废料浆形式的有害材料。因此需要提供一种用来封装无引线半导体产品的、可保存自然资源的、对环境有利的方法和装置。
本发明的公开内容
本发明即无引线半导体封装装置提供了一种成本效益较好的产品，该产品具有高级的机械、电子和热性能，并且具有一种可选择的窗口盖特征(即观测盖)，该窗口盖不仅提供了专门密封，而且还提供了用来观测内部封装的集成半导体电路(电路片/电路小片)的机构。费用的减少是这样得到实现的：(a)任意使用聚合材料如环氧树脂而不是使用封装装置的传统现有技术的陶瓷材料，及(b)简化封装过程，因此提供生产率。
与现有技术的“半蚀刻”的引线架相反，本发明采用了专门的“压制”和/或“弯曲”的标准焊接-涂敷过或者预先涂敷过的引线架，在模制过程中该引线架通过聚合材料来封装。本发明的方法包括提供专门的压缩型模子，它具有特殊的轮廓以避免引线架的有效焊接区域的“过量封装”，而这种过量封装在现有技术中是常见的问题。本申请人的发明使装置制造和封闭过程合理化。这种特殊轮廓的压缩模子有利于从引线架的外部描绘内部，其外部具有有效的可焊接区域，而该区域接触印刷电路板上的垫。该模子有效地提供了“压缩密封喷口”，引线架的有效可焊接区域可以从该该喷口进行延伸，并且被露出来，因此避免了被涂覆用来封装引线架内部的模子中所具有的聚合物，因此不需要艰苦的护罩步骤和令人讨厌的去飞边步骤。
本发明采用了引线架的“冲压”和/或“弯曲”的专门技术，从而使它符合特殊的半导体产品的电子-机械要求。借助于把引线架的材料冲压和/或弯曲成理想的结构，本发明不需要老技术的引线“半蚀刻”来使它符合封装的半导体产品的电子-机械要求。借助于例子，现有技术方法的“半蚀刻”引线架(例如10密耳的导电原料被蚀刻成大约5密耳，因此产生了大量的酸和导电材料的有害废料)，从而产生了所需要的形状。因此，本发明可以使用更薄的引线架材料如6密耳或者更小范围内的材料。本发明提供了许多更加与众不同的优点：(a)消费者规定封装尺寸大小；(b)可采用现有的表面安装技术(SMT)过程；(c)以较小的费用总体上提供性能；(d)在所有尺寸的产品中完全没有有害的材料副产品(有利于环境，即没有酸废料，没有金属废料，没有易挥发性的有机化合物的释放，及没有固体聚合物浆的废料)，及(e)引线架材料更薄(自然资源保存物)。
附图的简短描述
为了更好地理解本发明，参照下面优选的附图。
图1.1是本发明的接近电路片尺寸的基本的无引线的半导体封装装置的横剖视图，该装置具有相对于无引线的半导体装置结构所示出的封装型线，该半导体装置结构具有电路小片，该电路小片设置在“上部”位置上，而电线被连接到压制而成的引线架上，而另一个电线连接到电路小片连接垫上。
图1.2是本发明的接近电路片尺寸的无引线的半导体封装装置的横剖视图，该装置具有相对于无引线的半导体装置结构所示出的封装型线，该半导体装置结构具有压制而成的引线架和电路小片，而电线在它们之间连接在“下部”位置上。
图1.3是本发明的接近电路片尺寸的热的无引线的半导体封装装置的横剖视图，该装置具有相对于无引线的半导体装置结构所示出的封装型线，该半导体装置结构具有压制而成的引线架和电路小片、在其两者之间带有一根电线使其连接在“上部”位置上，并与该电路小片共用一个电路小片连接垫。
图1.3a是本发明的接近电路片尺寸的热的无引线的半导体封装装置的横剖视图，该装置具有相对于无引线的半导体装置结构所示出的封装型线，该半导体装置结构具有压制而成的引线架和电路小片，在其两者之间有一根电线使其连接在“上部”位置上，而电路小片连接垫的下表面没有被模制出来(即被露出来)。
图1.4是本发明的接近电路片尺寸的无引线的半导体封装装置的横剖视图，该装置具有相对于无引线的半导体装置结构所示出的封装型线，该半导体装置结构具有压制而成的引线架和中心垫，该中心垫设置在压制而成的引线架的下方，在其两者之间带有一根电线使其连接在“上部”位置上。
图1.4a是本发明的接近电路片尺寸的无引线的半导体封装装置的横剖视图，该装置具有相对于无引线的半导体装置结构所示出的封装型线，该半导体装置结构具有压制而成的引线架和中心垫，该中心垫设置在压制而成的引线架的下方，在其两者之间带有一根电线使其连接在“上部”位置上，并且中心垫的下表面没有被模制出来。
图1.4b是本发明的接近电路片尺寸的无引线的半导体封装装置的横剖视图，该装置具有相对于无引线的半导体装置结构所示出的封装型线，该半导体装置结构具有压制而成的引线架和倒装片，该倒装片设置在压制而成的引线架的下方，而至少一个导电颗粒接触和设置在引线架和倒装片之间。
图1.4c是本发明的电路片尺寸的无引线的半导体封装装置的横剖视图，该装置具有相对于无引线的半导体装置结构所示出的封装型线，该半导体装置结构具有压制而成的引线架和倒装片，该倒装片设置在压制而成的引线架的上方，带有至少一个导电颗粒在引线架和倒装片之间接触和设置。
图1.5是本发明的电路片尺寸的无引线的半导体封装装置的横剖视图，该装置具有相对于无引线的半导体装置结构所示出的封装型线，该半导体装置结构具有设置在引线架上的电路小片和在其间连接在在“上部”位置上的一根电线。
图1.6是根据本发明的电路片尺寸的无引线的半导体封装装置的横剖视图，该装置具有相对于无引线的半导体装置结构所示出的封装型线，该半导体装置结构具有位于至少一个引线架上的电路小片和一根在它们之间连接在“上部”位置上的电线。
图1.7是本发明的电路片尺寸的无引线的半导体封装装置的横剖视图，该装置具有相对于无引线的半导体装置结构所示出的封装型线，该半导体装置结构具有相对于引线架横向设置的露出电路小片和电线，该电线在它们之间连接在“上部”位置上。
图1.8是一表示制造过程期间可能产生的、本发明的无引线的半导体封装装置的横剖视图，该装置具有相对于至少一个无引线的半导体装置结构所示出的封装型线。
图2.0是一表示具有无引线半导体装置结构的、根据本发明的开有窗口的无引线的半导体封装装置的横剖视图，装置结构具有压制而成的引线架、电路小片和连接电线，由一观测盖相对于硬化过的聚合材料予以密封，具有位于压制而成的引线架的内部中的齐平的型线。
图3.0是一通过一个观测盖看去的、具有压制而成的引线架的、本发明的开有窗口的无引线的半导体封装装置的透视图，该引线架具有若干引线，这些引线借助于把它们之间的电线连接起来而共享一共用的电路小片。
图4.0是本发明的、用来封装无引线的半导体封装装置的制造方法的流程图。
图5.0是本发明的、用来封装开有窗口的、无引线的半导体封装装置的制造方法的流程图。
标号在整个附图部分中的许多图中指的是本发明的相同或者等同部分。
实现本发明的方式
图1.1以横截面示出了第一实施例，即示出了一种“接近电路片尺寸”的无引线的半导体封装装置1000(即封装和外部引线部分最小延伸到给定片的平面区域之外)，该装置1000具有封装型线10和专门的“压制而成”、“弯曲”的引线架30，该引线架30通过“冲压”和“弯曲”可导电材料如铜来形成，该引线30具有有效的可焊接长度60并且能够产生弯曲部分34，根据本发明，专门借助模子11(未示出)来可压缩地保持住专门的压制而成、弯曲的引线架30。这里所示出的、其它的无引线半导体装置元件是电路小片40、可以由填料金属形成的电路小片连接垫41和连接电线50，该电线由导电材料如金形成。模子11(未示出)通过压缩(例如使用热压)可以特别有效地保持住聚合材料12如聚合模制化合物，从而只包围住压制而成的、弯曲的引线架30的内部，因此在该压制而成的、弯曲的引线架30上保存有干净的焊接区域，因此避免了与环境不利相关的技术需要，从而除去了过量的封装材料。一种用来修整压制而成的、弯曲的引线架30的方法可以包括沿着箭头70所示出的方向锯开或者进行阳模切割。
图1.2是第二实施例的横剖视图，即是一种接近电路片尺寸的无引线的半导体封装装置1000的横剖视图，根据本发明，该装置1000具有：封装型线10；专门的“压制而成”、“弯曲”的引线架30，该引线架30通过冲压和弯曲可导电材料如铜来形成，产生了弯曲部分34；及电路小片40，而电线50由导电材料如金形成，该电线在它们之间连接在“下部”位置上。这些元件可以以相对图1.1所描述的方法来进行专门的压缩模制。
图1.3是第三实施例的横剖视图，即是一种接近电路片尺寸的热的无引线的半导体封装装置1000的横剖视图，根据本发明，该装置1000具有：封装型线10；专门的“压制而成”、“弯曲”的引线架30，该引线架30通过冲压和弯曲可导电材料如铜来形成，产生了弯曲部分34；及电路小片40，而电线50由导电材料如金形成，该电线在它们之间连接在“上部”位置上，并且压制而成的、弯曲的引线架30和电路小片40共享一个没有被模制出来(即被露出来)的共用电路小片连接垫41。这些元件可以以相对图1.1所描述的方法来进行专门的压缩模制。
图1.3a是第四实施例的横剖视图，即是一种接近电路片尺寸的热的无引线的半导体封装装置1000的横剖视图，根据本发明，该装置1000具有：封装型线10；专门的“压制而成”、“弯曲”的引线架30，该引线架30通过冲压和弯曲可导电材料如铜来形成，产生了弯曲部分34；及电路小片40，而电线50由导电材料如金形成，该电线在它们之间连接在“上部”位置上，并且电路小片连接垫41的下表面没有被模制出来(即被露出来)。这些元件可以以相对图1.1所描述的方法来进行专门的压缩模制。
图1.4是第五实施例的横剖视图，即是一种接近电路片尺寸的无引线的半导体封装装置1000的横剖视图，根据本发明，该装置1000具有：封装型线10；专门的压制而成、弯曲的引线架30，该引线架30通过冲压和弯曲可导电材料如铜来形成，产生了弯曲部分34；及中心垫40a，该中心垫设置在冲压而成的、弯曲的引线架30的下方，而电线50由导电材料如金子形成，该电线在它们之间连接在“上部”位置上。这些元件可以以相对图1.1所描述的方法来进行专门的压缩模制。
图1.4a是第六实施例的横剖视图，即是一种接近电路片尺寸的无引线的半导体封装装置1000的横剖视图，根据本发明，该装置1000具有：封装型线10；专门的“压制而成”、“弯曲”的引线架30，该引线架30通过冲压和弯曲可导电材料如铜来形成，产生了弯曲部分34；及中心垫40a，该中心垫设置在冲压而成的、弯曲的引线架30的下方，而电线50由导电材料如金子形成，该电线在它们之间连接在“上部”位置上，并且中心垫40a的下表面没有被模制出来(即被露出来)。这些元件可以以相对图1.1所描述的方法来进行专门的压缩模制。
图1.4b是第七实施例的横剖视图，即是一种接近电路片尺寸的无引线的半导体封装装置1000的横剖视图，根据本发明，该装置1000具有：封装型线；专门的“压制而成”、“弯曲”的引线架30，该引线架30通过冲压和弯曲可导电材料如铜来形成，产生了弯曲部分34；及倒装片40b，该倒装片40设置在冲压而成的、弯曲的引线架30的下方，而至少一个导电颗粒51接触和设置在压制而成的、弯曲的引线架30和倒装片40b之间。这些元件以相对图1.1所描述的方法来进行专门的压缩模制。
图1.4c是第八实施例的横剖视图，即是一种“电路片尺寸”的无引线的半导体封装装置1000的横剖视图，根据本发明，该装置1000具有：封装型线10；专门的压制而成的引线架30，该引线架30通过冲压可导电材料如铜来形成；及一倒装片40b，该倒装片40设置在冲压而成的引线架30的上方，而至少一个导电颗粒51在压制而成的引线架30和倒装片40b之间接触和设置。这些元件以相对图1.1所描述的方法来进行专门的压缩模制。
图1.5是第九实施例的横剖视图，即是一种电路片尺寸的无引线的半导体封装装置1000的横剖视图(即封装和外部引线部分最最小地延伸到给定片的平面区域之外，该平面封装区域小于或者等于1.2倍的电路小片平面区域)，根据本发明，该装置1000具有：封装型线10；电路小片40，它设置在专门的压制而成的引线架30上，该引线架30通过冲压可导电材料如铜来形成；及电线50，该电线由导电材料如金形成，该电线在它们之间连接在“上部”位置上。这些元件以相对图1.1所描述的方法来进行专门的压缩模制。
图1.6是第十实施例的横剖视图，即是一种电路片尺寸的无引线的半导体封装装置1000的横剖视图，根据本发明，该装置1000具有：封装型线10；电路小片40，它设置在至少一个专门的压制而成的引线架30上，该引线架30通过冲压可导电材料如铜来形成；及电线50，该电线由导电材料如金形成，该电线在它们之间连接在“上部”位置上。这些元件以相对图1.1所描述的方法来进行专门的压缩模制。
图1.7是第十一实施例的横剖视图，即是一种无引线的半导体封装装置1000的横剖视图，根据本发明，该装置1000具有：封装型线；露出的电路小片40，它相对于专门的压制而成的引线架30横向地设置，该引线架30通过冲压可导电材料如铜来形成；及电线50，该电线由导电材料如金形成，该电线在它们之间连接在“上部”位置上。这些元件以相对图1.1所描述的方法来进行专门的压缩模制。
图1.8以横截面示出了与第三实施例相一致的一种接近电路片尺寸的无引线的半导体封装装置1000，根据本发明，该装置1000具有：封装型线10；至少一个专门的“压制而成”、“弯曲”的引线架30，该引线架30通过冲压和弯曲可导电材料如铜来形成，形成了具有有效的可焊接长度60的弯曲部分34，借助模子11(未示出)来保持住该引线架30，而该模子11与制造过程期间所产生的一样。这里所示出的、其它的无引线半导体装置元件是至少一个电路小片40、至少一个可以由填料金属形成的电路小片连接垫41和至少一个连接电线50，该电线由导电材料如金形成。在封装若干无引线的半导体装置时，一种在装配线方式中分开大批量生产的被封装装置的方法包括沿着箭头70所示出的方向锯开或者进行阳模切割。模子11(未示出)通过压缩力可以特别有效地保持住至少一个聚合材料12，从而只包围住该至少一个专门的压制而成的、弯曲的引线架30的内部(即不会泄漏到该至少一个压制而成的引线架的外部中)，因此在该至少一个专门的压制而成的、弯曲的引线架30的外部上保存有干净的焊接区域，因此避免了除去过量封装材料的相关技术需要。
图2.0以横截面示出了本发明的另一个实施例，即示出了开有窗口的、无引线的半导体封装装置2000，根据本发明，该封装装置2000具有：无引线的半导体装置，该半导体装置包括专门的压制而成的、弯曲的引线架30，该引线架通过冲压和弯曲导电材料如铜来形成，从而形成了弯曲部分34；电路小片40，借助于非导电粘性材料42把它粘结到电路小片连接垫41上；及电线50，它由材料如金形成，该电线由观测盖80来封闭，该观测盖由可视的透明材料如玻璃或者高温聚合物来形成，通过密封材料如可紫外线硬化的环氧树脂使之与硬化的聚合材料体13之间密封。通过观测盖80把密封材料14压入到专门的双通道密封座的外侧通道15中，因此一部分密封材料14流入到内侧通道16中，从而提供了特别大的密封表面区域，并且更好地密封了污染物入口。但是，本发明不局限于使用双通道，而是如要封装的给定半导体电路所需要的那样可以使用至少一个通道。硬化过的聚合材料体13具有：重叠的锥形型线，该线位于压制而成的引线架30的外部31和内部32处；及齐平型线，它位于电路小片连接垫41和压制而成的引线架30的内部33之间。加强填料15被硬化到压制而成的引线架30的内部33的下表面中，该内部33以前借助于模子11(未示出)来专门压缩地保持。
图3.0以透视图示出了开有窗口的、无引线的半导体封装装置2000，根据本发明，该封装装置2000具有：压制而成的和/或弯曲的引线架30，该引线架通过冲压和/或弯曲导电材料如铜来形成，这种专门冲压可以除去引线架材料，如空白35所示出的一样，借助于使电线50连接在它们之间而共享共用的电路小片40，如通过观测盖80所看到的一样，该观测盖80密封了专门的密封座15、16，该密封座15、16具有至少一个通道，该通道形成于硬化过的聚合体13中，该聚合体13通过上述的专门压缩模制技术来形成。
图4.0用流程图来表示了用来封装至少一个无引线的半导体封装装置1000的本发明总制造方法M-1。方法M-1包括这些步骤：(a)借助于锯开或者阳模切割引线架材料来提供至少一个压制而成的引线架，该引线架具有至少一个引线，如过程块100所示一样；(b)借助于施加非导电的粘结材料把电路小片连接到该至少一个引线架上(电路小片连接)，如过程块200所示一样；(c)使非导电粘结材料进行硬化，如过程块300所示一样；(d)把来自电路小片的电线连接到该至少一个引线中的每一个中，如过程块400所示一样；(e)借助于技术如使用具有上部压板和下部压板的热压机的热压缩模制，用另一种聚合材料如聚合模制化合物，模制出半导体装置零件，从而形成了专门的密封喷口，通过压缩力和极小的局部变形使外部引线部分从密封喷嘴处进行延伸，因此形成了该至少一个无引线的半导体封装装置1000，如过程块500所示一样；(f)借助于光激射，标记该至少一个所形成的无引线的半导体封装装置1000，如过程块600所示一样；(g)使该至少一个激光标记过的无引线的半导体封装装置1000单一化(singulating)，如过程块700所示一样；(h)封装该至少一个单一化过(singulated)的无引线的半导体封装装置1000，如过程块800所示一样；及(i)运送该至少一个封装过的无引线的半导体封装装置1000。如过程块900所示一样。
图5.0用流程图来表示了用来封装至少一个开有窗口的、无引线的半导体封装装置1000的本发明总制造方法M-2。方法M-2包括这些步骤：(a)借助于预先涂敷引线架材料来提供至少一个压制而成的引线架，该引线架具有至少一个引线，如过程块102所示一样；(b)借助于技术如使用具有上部压板和下部压板的热压机的热压缩模制，用聚合材料如聚合模制化合物，模制出该至少一个压制而成的、已预先涂敷过的引线架，从而形成了专门的密封喷口，通过压缩力和极小的局部变形使外部引线部分从密封喷嘴处进行延伸，如过程块103所示一样；(c)锯开或者阳模切割引线架材料，如过程块101所示一样；(d)把电路小片连接到该至少一个引线架上(电路小片连接)，如过程块202所示一样；(e)使非导电粘结材料进行硬化，如过程块303所示一样；(f)把来自电路小片的电线连接到该至少一个引线中，如过程块404所示一样；(g)借助于施加密封剂如可紫外线硬化的环氧树脂把窗口安装到模制出的引线架上，如过程块505所示一样，因此形成了该至少一个无引线的半导体封装装置2000；(h)借助于激光技术，标记该至少一个所形成的开有窗口的、无引线的半导体封装装置2000，如过程块606所示一样；(g)使该至少一个激光标记过的、开有窗口的、无引线的半导体封装装置2000单一化(singulating)，如过程块707所示一样；(i)封装该至少一个单一化过(singulated)的、开有窗口的、无引线的半导体封装装置2000，如过程块808所示一样；及(k)运送该至少一个封装过的、开有窗口的、无引线的半导体封装装置2000。如过程块909所示一样。
这里所详细示出的和描述的信息完全可以实现本发明的上述目的和本发明目前的优选实施例，因此这些信息表示本发明所广泛考虑的主题。本发明的范围完全包括了对于本领域普通技术人员来讲是显而易的其它实施例，因此本发明的范围不受除附加权利要求之外的任何事情的限制，其中单一的元件标号不是意味着“一个或者只有一个”，除非明确这样声明，不是“一个或者更多个”。上述优选实施例和辅助实施例的这些零件的所有结构和功能的等同物(对于本领域普通技术人员来是公知的)清楚地包括以作参考，并且通过权利要求来包括。而且，对于这些权利要求所包括的技术方案而言，不需要该装置或者该方法解决本发明所要解决的每个问题或者所有问题。此外，在所公开的内容中，没有元件、零件或者方法步骤是专用于公众的，而与该元件、零件或者方法步骤是否在权利要求中被引用无关。但是，对于本领域普通技术人员来讲，显而易见的是，各种各样在形式、半导体材料和制造材料细节上的改变和改进没有脱离附加权利要求所提出的本发明的精神实质和范围内。这里没有权利要求是可以根据35U.S.C112、第六段的规定来理解的，除非使用措词“用于…的装置”来明确引用该元件。

Claims (24)

1.一种用来封装半导体电路的无引线的半导体产品封装装置，该装置包括：
a.引线架；
所述引线架具有内部引线部分和外部引线部分；
所述引线架与所述半导体电路进行电接触，及
所述引线架通过冲压引线架材料来形成；及
b.壳体件；
所述壳体件包括壳体材料，及
所述壳体材料密封所述引线架，以便所述外部引线部分被露出，从而提供了可焊接的区域。
2.如权利要求1所述的无引线的半导体产品封装装置，其特征在于，所述半导体电路包括：
a.至少一个电路小片连接垫；
其中把所述半导体电路安装在所述电路小片连接垫上；及
b.至少一个电线；
其中所述至少一个电线通过电线来连接，从而在所述电路和所述内部引线部分之间形成电连接；
其中所述至少一个电线由从下面该组导电材料中选择出来的导电材料来形成，该组导电材料主要包括铜、铝和金子，
其中，所述壳体材料还被压缩模制在所述电路小片连接垫、所述至少一个电线和所述内部引线部分的周围上；
其中，所述壳体材料没有被压缩模制在所述引线外部的周围上；及
其中，所述压制而成的引线架被机械地弯曲成理想结构，从而有利于将所述无引线的半导体产品封装装置适合于一个从接近电路片尺寸到电路片尺寸的范围的尺寸。
3.如权利要求2所述的无引线的半导体产品封装装置，其特征在于，所述引线架材料具有一个在6密耳或者更小的范围内的厚度。
4.如权利要求1所述的无引线的半导体产品封装装置，其特征在于，所述引线材料具有这样的厚度：该厚度处于6密耳或者更小的范围内。
5.如权利要求4所述的无引线的半导体产品封装装置，其特征在于，所述无引线的半导体产品包括：
a.至少一个电路小片连接垫；
其中把所述半导体电路安装在所述电路小片连接垫上；及
b.至少一个电线；
其中所述至少一个电线通过电线来连接，从而在所述电路和所述内部引线部分之间形成电连接；
其中所述至少一个电线由从下面该组导电材料中选择出来的导电材料来形成，该组导电材料主要包括铜、铝和金子，
其中，所述壳体材料还被压缩模制在所述电路小片连接垫、所述至少一个电线和所述内部引线部分的周围上；
其中，所述壳体材料没有被压缩模制在所述引线外部的周围上；及
其中，所述压制而成的引线架被机械地弯曲成理想结构，从而有利于将所述无引线的半导体产品封装装置适合于一个从接近电路片尺寸到电路片尺寸范围的尺寸大小。
6.如权利要求1所述的无引线的半导体产品封装装置，还包括：
a.窗口盖件；
其中，所述窗口盖件形成了所述壳体件的一部分，及
其中，所述窗口盖件由从下面该组目视透明材料中所选择出来的目视透明材料形成，该组目视透明材料主要包括聚合物和玻璃；
b.密封材料；
c.密封座；
所述密封座包括至少一个通道，该通道设置在所述壳体件的上表面上，从而提供了较大的密封表面区域；及
所述密封材料在所述至少一个通道内设置在所述壳体件和所述窗口盖件之间，从而防止污染物进入。
7.如权利要求2所述的无引线的半导体产品封装装置，其特征在于，电路小片借助于非导电聚合物可连接到所述引线架的每个所述内部部分上。
8.如权利要求5所述的无引线的半导体产品封装装置，其特征在于，电路小片借助于非导电聚合物可连接到所述引线架的每个所述内部部分上。
9.如权利要求1所述的无引线的半导体产品封装装置，其特征在于，所述壳体材料包括聚合模制混合物，
其中，所述壳体件包括被压缩模制的所述壳体材料，
以便所述外部引线部分被露出；
以便在所述外部引线部分上保存有可焊接的区域；及
以便避免对所述外部引线部分进行去飞边。
10.如权利要求1所述的无引线的半导体产品封装装置，其特征在于，所述引线架由从下面该组导电材料中所选择出来的至少一种导电材料来形成，该组导电材料主要包括铜、铝和金；
其中，所述壳体材料至少包括一种从下面该组壳体材料中所选择出来的材料，该组壳体材料主要包括聚合物和陶瓷；及
其中，所述聚合物从下面该组聚合物中选择出来，该组聚合物主要包括环氧树脂、聚酰亚胺和双马来酰亚胺。
11.一种制造用来封装半导体电路的无引线的半导体产品封装装置的方法，该方法包括这些步骤：
a.提供引线架；
所述引线架具有内部引线部分和外部引线部分，
所述引线架与所述半导体电路进行电接触，及
所述引线架通过冲压引线架材料来形成；及
b.提供壳体件；
所述壳体件包括壳体材料，及
所述壳体材料密封所述引线架，以便所述外部引线部分被露出，从而提供了可焊接的区域，及
以此形成所述无引线的半导体产品封装装置。
12.如权利要求11所述的制造无引线的半导体产品封装装置的方法，其特征在于，所述无引线的半导体电路包括：
a.至少一个电路小片连接垫；
其中把所述半导体电路安装在所述电路小片连接垫上；及
b.至少一个电线；
其中所述至少一个电线通过电线来连接，从而在所述电路和所述内部引线部分之间形成电连接；
其中所述至少一个电线由从下面该组导电材料中选择出来的导电材料来形成，该组导电材料主要包括铜、铝和金，
其中，所述壳体材料还被压缩模制在所述电路小片连接垫、所述至少一个电线和所述内部引线部分的周围；
其中，所述壳体材料没有被压缩模制在所述引线外部的周围；及
其中，所述引线架被机械地弯曲成理想结构，从而有利于将所述无引线的半导体产品封装装置适合于一个从接近电路片尺寸到电路片尺寸的范围内的尺寸上，及
以此形成所述无引线的半导体产品封装装置。
13.如权利要求12所述的制造无引线的半导体产品封装装置的方法，其特征在于，所述引线架材料具有处于6密耳或者更小的范围内的厚度。
14.如权利要求11所述的制造无引线的半导体产品封装装置的方法，其特征在于，所述引线架材料具有处于6密耳或者更小的范围内的厚度。
15.如权利要求14所述的制造无引线的半导体产品封装装置的方法，其特征在于，所述无引线的半导体产品包括：
a.至少一个电路小片连接垫；
其中把所述至少一个半导体电路安装在所述电路小片连接垫上；及
b.至少一个电线；
其中所述至少一个电线通过电线来连接，从而在所述电路和所述内部引线部分之间形成电连接；
其中所述至少一个电线由从下面该组导电材料中选择出来的导电材料来形成，该组导电材料主要包括铜、铝和金，
其中，所述壳体材料还被压缩模制在所述电路小片连接垫、所述至少一个电线和所述内部引线部分的周围；
其中，所述壳体材料没有被压缩模制在所述引线外部的周围；及
其中，所述引线架被机械地弯曲成理想结构，从而有利于将所述无引线的半导体产品封装装置适合于一个从接近电路片尺寸到电路片尺寸的范围内的尺寸上，及
以此形成所述无引线的半导体产品封装装置。
16.如权利要求14所述的制造无引线的半导体产品封装装置的方法，该方法还包括这些步骤：
a.提供窗口盖件；
其中，所述窗口盖件形成了所述壳体件的一部分，及
其中，所述窗口盖件由从下面该组目视透明材料中所选择出来的目视透明材料形成，该组目视透明材料主要包括聚合物和玻璃；
b.提供密封材料；
c.提供密封座；
所述密封座包括至少一个通道，该通道设置在所述壳体件的上表面上，从而提供了较大的密封表面区域；及
所述密封材料在所述至少一个通道内设置在所述壳体件和所述窗口盖件之间，从而防止污染物进入，及
以此形成所述无引线的半导体产品封装装置。
17.如权利要求12所述的制造无引线的半导体产品封装装置的方法，其特征在于，电路小片借助于非导电聚合物可连接到所述引线架的每个所述内部部分上。
18.如权利要求15所述的制造无引线的半导体产品封装装置的方法，其特征在于，电路小片借助于非导电聚合物可连接到所述引线架的每个所述内部部分上。
19.如权利要求11所述的制造无引线的半导体产品封装装置的方法，
其中，所述壳体材料包括聚合模制混合物，
其中，所述壳体件包括被压缩模制的所述壳体材料，
以便所述外部引线部分被露出；
以便在所述外部引线部分上保存有可焊接的区域；及
以便避免对所述外部引线部分进行去飞边。
20.如权利要求11所述的制造无引线的半导体产品封装装置的方法，
其中，所述引线架由导电材料形成，所述导电材料包括铜；
其中，所述壳体材料包括从下面该组壳体材料中所选择出来的至少一种材料，该组壳体材料主要包括聚合物和陶瓷；及
其中，所述聚合物从下面该组聚合物中选择出来，该组聚合物主要包括环氧树脂、聚酰亚胺和双马来酰亚胺。
21.一种制造用来封装至少一个半导体电路的至少一个无引线的半导体产品封装装置的方法，该方法包括这些步骤：
a.冲压引线架材料，从而提供至少一个压制而成的引线架，所述引线架材料具有一个处于小于6密耳的范围内的厚度，所述至少一个压制而成的引线架具有内部引线部分和外部引线部分；
b.把非导电粘结材料施加到电路小片和所述内部引线部分之间的交界面上，从而把所述电路小片连接到每个所述至少一个引线架的所述内部引线部分中；
c.使每个所述至少一个压制而成的引线架的所述非导电粘结材料进行硬化；
d.为每个所述至少一个压制而成的引线架提供电线；
所述电线具有第一端和第二端，
其中所述第一电线端连接到所述电路小片上，及
其中所述第二电线端连接到所述引线的内部部分上；
e.使用热压机，在模子的所述引线内部周围模制壳体材料，从而为每个所述至少一个压制而成的引线架形成壳体件，所述模子具有上部和下部；
所述热压机具有相互平行的上压板和下压板，
所述模子上部向内地设置在所述上压板上；
所述模子下部向内地设置在所述下压板上；
所述引线内部被连接到所述电路小片上；
所述热压机的上压板和所述热压机的下压板各自沿着垂直于所述压板的方向移动到一起，从而使所述上部模子部分压靠在所述下部模子部分上；
以此通过所述模子部分把压力施加在所述外部引线部分上，从而在所述外部引线部分上形成极小的局部变形；
以此通过所述压缩力和所述极小的局部变形，在所述内部引线部分和所述外部引线部分之间形成了防泄漏密封；及
以此所述壳体材料在所述模子内进行硬化；
以此形成所述壳体件；及
以此形成所述至少一个无引线的半导体产品封装装置；
f.借助光激射，标记每个所述至少一个所形成的无引线的半导体产品封装装置的所述外部引线部分；
g.使每个所述至少一个所形成的无引线的半导体产品封装装置的所述外部引线部分相互单一化(singulating)；
h.封装所述单一化过的所述至少一个无引线的半导体产品封装装置；及
i.运送所述封装过的无引线的半导体产品封装装置。
22.如权利要求21所述的制造用来封装至少一个半导体电路的至少一个无引线的半导体产品封装装置的方法，其特征在于，使所述引线架机械弯曲成理想的结构，从而有利于将所述无引线的半导体产品封装装置适合于一个从接近电路片尺寸到电路片尺寸的范围内的尺寸上。
23.一种制造用来封装至少一个半导体电路的至少一个开有窗口的无引线的半导体产品封装装置的方法，该方法包括这些步骤：
a.冲压引线架材料，从而提供至少一个压制而成的引线架，所述引线架材料具有一个处于小于6密耳的范围内的厚度，所述至少一个压制而成的引线架具有内部引线部分和外部引线部分；
b.预先涂敷所述至少一个压制而成的引线架；
c.使用热压机，在模子的所述引线内部周围模制壳体材料，从而为每个所述至少一个压制而成的引线架形成壳体件，所述模子具有上部和下部；
所述模子上部具有型线，从而容纳观测盖；
所述热压机具有相互平行的上压板和下压板，
所述模子上部向内地设置在所述上压板上；
所述模子下部向内地设置在所述下压板上；
所述引线内部被连接到所述电路小片上；
所述热压机的上压板和所述热压机的下压板各自沿着垂直于所述压板的方向移动到一起，从而使所述上部模子部分压靠在所述下部模子部分上；
以此通过所述模子部分把压力施加在所述外部引线部分上，从而在所述外部引线部分上形成极小的局部变形；
以此通过所述压缩力和所述极小的局部变形，在所述内部引线部分和所述外部引线部分之间形成了防泄漏密封；及
以此所述壳体材料在所述模子内进行硬化；
以此形成所述壳体件；及
以此形成所述至少一个无引线的半导体产品封装装置；
d.把非导电粘结材料施加到电路小片和所述内部引线部分之间的交界面上，从而把所述电路小片连接到每个所述至少一个引线架的所述内部引线部分中；
e.使每个所述至少一个引线架的非导电粘结材料进行硬化；
f.为每个所述至少一个引线架提供电线；
所述电线具有第一端和第二端，
其中所述第一电线端连接到所述电路小片上，及
其中所述第二电线端连接到所述引线内部部分上；
g.借助于使密封材料硬化到密封座中，把窗口盖件安装到所述壳体件上，该密封座具有至少一个通道；
所述密封剂相互混合地设置在所述窗口和所述模制出的引线架之间；
所述密封剂通过所述观测盖来压缩，一部分所述密封材料因此而被挤压到所述至少一个通道中；
以此形成密封，及
以此形成具有所述窗口盖件的、所述至少一个开有窗口的无引线的半导体产品封装装置；
h.借助光激射，标记所述至少一个开有窗口的所形成的无引线的半导体产品封装装置的所述外部引线部分；
i.使所述至少一个开有窗口的、所形成的无引线的半导体产品封装装置的所述外部引线部分相互单一化(singulating)；
j.封装所述单一化过的至少一个开有窗口的无引线的半导体产品封装装置；及
k.运送所述封装过的至少一个开有窗口的无引线的半导体产品封装装置。
24.如权利要求22所述的制造用来封装至少一个半导体电路的至少一个开有窗口的无引线的半导体产品封装装置的方法，其特征在于，使所述引线架机械弯曲成理想的结构，从而有利于将所述无引线的半导体产品封装装置适合于一个从接近电路片尺寸到电路片尺寸的范围内的尺寸上。
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WO2001075938A2 (en) 2001-10-11
EP1295338A2 (en) 2003-03-26
WO2001075938A3 (en) 2002-07-25
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