CN1437256A - 半导体元件及其制造方法,和半导体器件及其制造方法 - Google Patents

半导体元件及其制造方法,和半导体器件及其制造方法 Download PDF

Info

Publication number
CN1437256A
CN1437256A CN03104240A CN03104240A CN1437256A CN 1437256 A CN1437256 A CN 1437256A CN 03104240 A CN03104240 A CN 03104240A CN 03104240 A CN03104240 A CN 03104240A CN 1437256 A CN1437256 A CN 1437256A
Authority
CN
China
Prior art keywords
columnar projections
film
semiconductor element
pad
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN03104240A
Other languages
English (en)
Other versions
CN100511658C (zh
Inventor
西山知宏
田子雅基
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Godo Kaisha IP Bridge 1
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CN1437256A publication Critical patent/CN1437256A/zh
Application granted granted Critical
Publication of CN100511658C publication Critical patent/CN100511658C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/0347Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361Physical or chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/039Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10145Flow barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • H01L2224/11462Electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • H01L2224/11464Electroless plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1181Cleaning, e.g. oxide removal step, desmearing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1182Applying permanent coating, e.g. in-situ coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/119Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/119Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902Multiple masking steps
    • H01L2224/11906Multiple masking steps with modification of the same mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13023Disposition the whole bump connector protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/1356Disposition
    • H01L2224/13563Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13565Only outside the bonding interface of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13609Indium [In] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011Chemical cleaning, e.g. etching, flux
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81013Plasma cleaning
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909Post-treatment of the bump connector or bonding area
    • H01L2224/8191Cleaning, e.g. oxide removal step, desmearing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00013Fully indexed content
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01018Argon [Ar]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01024Chromium [Cr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0103Zinc [Zn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01049Indium [In]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01087Francium [Fr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049Nitrides composed of metals from groups of the periodic table
    • H01L2924/04944th Group
    • H01L2924/04941TiN
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0364Conductor shape
    • H05K2201/0367Metallic bump or raised conductor not used as solder bump
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2081Compound repelling a metal, e.g. solder
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Abstract

用能使组件成形的电解镀敷法,将由铜等形成的柱状块,经过晶片上的接合膜和粘接膜,形成在布线薄膜上。例如金的防氧化膜在柱状块的上表面或一部分上表面和侧表面形成。例如氧化膜这样的防沾湿膜,按需要形成在柱状块上。如果这个块焊接至布线基板上的焊盘,焊料将沾湿于柱状块上表面整个区域,和侧表面的部分区域。因此能形成稳定而可靠的连接。另外,由于柱状块不熔化,半导体线路板和组装线路板之间的距离不因焊料而变窄。

Description

半导体元件及其制造方法,和半导体器件及其制造方法
技术领域
本发明涉及半导体元件及其制造方法,和半导体器件及其制造方法,特别是涉及面朝下安装的倒装晶片型半导体元件的块结构及其制造方法,和它的组装结构及其制造方法。
技术背景
半导体元件的电极与外部端子的连接方法有两种类型,就是用金属细线焊接的方法,和用半导体元件电极上形成的焊料块的倒装晶片方法。倒装晶片方法在近年来的高密度和高引脚数量的趋势中,被认为是有利的。近年来,为了提高半导体组件的组装密度,大量采用以焊料块作为外部端子的球格栅阵列型半导体组件工艺,它能响应高引脚数量的趋势,而保持较大的端子间距。倒装晶片型在许多情况下,也适用于安装至组装板(内插器)上的半导体元件。这种倒装晶片型连接方法有许多发展,例如被称为控制熔榻(高度)芯片连接(C4)技术是首先的值得一提的。
图35是倒装晶片型半导体元件常规结构的剖视图。如图35中所示,在半导体衬底1上,形成连接至内部接线的电极2和在电极2上有开口的覆盖膜3。在电极2上,经过接合膜4和粘接膜5形成电极20。至于形成电极20的方法,通常是用各种方法例如蒸发法、电解镀敷法、焊糊印刷法、和焊球装载和供应法,和用焊剂进行焊料回流处理,供应焊料而形成半球形的块。
图36是倒装晶片型半导体元件的常规倒装晶片组装结构的剖视图。焊盘14和焊料阻挡膜13形成在布线基板(内插器)12的表面上,布线基板的焊盘14上预先供有焊料。然后,加上焊剂后的半导体元件装在布线基板12上。通过焊料回流处理,形成焊料带11,完成块20和焊盘14之间的连接。接着,布线基板12和半导体衬底1之间的裂隙(未示)填充以欠填充树脂(underfill resin)。
除了焊料块以外,使用焊接丝在半导体芯片上形成金的柱状块的方法,以及通过电解镀金形成金块的方法,是通常所知的。这些块粘附在布线基板上形成的金属膜,例如镀金、银/锡焊料和铟/锡/铅焊料上。
为保证可靠性,在倒装晶片安装完成以后,在半导体芯片和布线基板之间的裂隙中填充,欠填充树脂。进行树脂充填时,最好保持半导体芯片和布线基板之间的裂隙大一些,以便进行良好的充填而不产生空隙。但是,如果要求焊料块在高度上高一些,以便在电极上熔化并形成半球形,供应的焊料量应该增加。这就有可能在细微间距的电极之间,使毗邻的焊料块短路。所以,在精细间距的发展趋势下,在电极上形成高的焊料块就变得困难。另一方面,就细微间距趋势来说,由于充填的树脂流在外表上要变窄,细微的间距使充填欠填充树脂的困难剧升。
用蒸发法和焊糊印刷法形成焊料块,涉及到增加制造成本,因为除了对掩模的要求以外,掩模的耐用性也是难得的。
焊料球供应方法涉及到与焊料球本身可比的高成本,需要按要求的布局统调焊料球,并在半导体芯片上进行。因为在晶片单元上装载组件困难,所以块成形总成本变高。另外,与细微间距相应的更小直径焊料球的制造也是困难的。因此,要求的球尺寸(直径)变得越小,制造成品量下降越多,招致高成本的结果。
还有,当有电极安排在存储单元,当焊料用作块材料时,从包含在构成焊料的铅或锡中的放射性成分产生的α射线,可能引起软误差。
有些镀敷块和柱状块用金。问题是金材料的成本高。还有一个问题是块的数量越增加,成形成本也越提高,因为是进行金柱状块的单独成形。
进一步说,当进行镀金块的焊料连接时,因为金有良好的可沾湿性,焊料从侧面向上沾湿,从电极和镀金层的界面进入。这可能引起界面强度下降,或在端部剥离,这涉及到可靠性问题。
也有建议用铜做镀敷块的焊接工艺,例如在用电解镀敷法形成铜块以后,在半导体基板上形成聚酰亚胺膜,使铜块的上半部分可以暴露出来,然后用浸渍法在铜块上形成焊料膜,这个工艺揭示在JP-A-3-22437中。但用这种方法在倒装晶片上覆盖厚树脂膜,当装在布线基板上以后,以欠填充树脂充填变得困难。此外,由于铜块和聚酰亚胺膜的粘着力低,焊料容易沾上去,散布到电极上,除非对铜块方面做特殊处理。因此,与金块的情况类似,出现可靠性问题。
发明内容
本发明的一目的是保证芯片和基板之间有充分的距离,即使电极有细微的间距也是如此。
本发明的另一目的是提供能以低成本制造的、倒装晶片的块结构。本发明的又一目的是提供一种组装结构,其引起可靠性降低如软误差或焊盘剥离的可能性小。
根据本发明的一种半导体元件,包括柱状凸起,其用作为块,并经接合膜或粘接膜形成在电极上。所述柱状凸起的上表面,或所述柱状凸起的上表面和侧表面的上部,被覆盖以可沾湿性极好的盖膜。
根据本发明的另一方面的一种半导体元件,包括柱状凸起,其用作为块,并经接合膜或粘接膜形成在电极上。至少在接近柱状凸起的侧表面的电极的一部分上,形成防沾湿膜。
一种制造根据本发明的半导体元件的方法,包括步骤:
在其上有电极形成的半导体衬底整体上,形成金属膜,用作镀敷电极;
在所述金属膜上形成阻挡膜,其在所述电极位置上有一个开口;
用电解镀敷法以柱的形状淀积高电导率金属,形成柱状凸起;
除去所述阻挡膜;
利用所述柱状凸起作为掩模,蚀刻除去所述金属膜;和
在所述柱状凸起表面形成防沾湿膜。
一种制造根据本发明另一方面的半导体元件的方法,包括步骤:
在所述半导体衬底上形成阻挡膜,所述阻挡膜在所述半导体衬底上形成的电极位置上有一个开口;
进行无电镀敷激活处理,在所述阻挡膜上形成活性膜;
除去所述阻挡膜上的活性膜;
用无电镀敷法在所述开口淀积高导电率金属,形成柱状凸起;
除去所述阻挡膜;和
在所述柱状凸起的表面形成防沾湿膜。
根据本发明的一种半导体器件,包括:导电柱状凸起,其形成在半导体元件的电极上,并与布线基板上的焊盘焊接。所述柱状凸起的至少一部分侧表面,被覆盖以防沾湿膜。
根据本发明的另一方面的一种半导体器件,包括:导电柱状凸起,其形成在半导体元件的电极上,并与布线基板上的焊盘焊接。所述导电柱状凸起的焊接部分,局限于所述柱状凸起的上表面。
根据本发明的另一方面的一种半导体器件,包括:导电柱状凸起,其形成在半导体元件的电极上,并与布线基板上的焊盘焊接。所述柱状凸起经过焊接沾湿性极好、难以氧化的金属膜焊接,所述金属膜形成在所述柱状凸起的上表面,或所述柱状凸起侧表面的上部或上表面。
根据本发明的另一方面的一种半导体器件,包括:导电柱状凸起,其形成在半导体元件的电极上,并与布线基板上的焊盘焊接。所述柱状凸起的上表面和所述布线基板的焊盘表面,经过焊接沾湿性极好、难以氧化的金属膜连接。
一种制造根据本发明的半导体器件的方法,包括步骤:
向形成在半导体元件电极上的柱状凸起末端供应具有焊剂活性效果的热固性树脂;
将所述柱状凸起和布线基板的焊盘对准,焊盘上已供有以预定量的焊料;和
加热并仅将所述柱状凸起末端部焊接至所述布线基板的焊盘。
一种制造根据本发明另一方面的半导体器件的方法,包括步骤:
向形成在半导体元件电极上的柱状凸起末端提供焊剂;
将所述柱状凸起和布线基板的焊盘对准,焊盘上已供有以预定量的焊料;
加热并仅将所述柱状凸起末端部焊接至所述布线基板的焊盘;和
清洗并除去所述焊剂。
一种制造根据本发明另一方面的半导体器件的方法,包括步骤:
向布线基板的焊盘上供应具有焊剂活性效果的热固性树脂;
将形成在半导体元件电极上的柱状凸起和所述布线基板的焊盘对准,柱状凸起的末端部加有焊料膜;和
加热并仅将所述柱状凸起的末端部焊接至所述布线基板的焊盘。
一种制造根据本发明另一方面的半导体器件的方法,包括步骤:
向布线基板的焊盘上供应焊剂;
将形成在半导体元件电极上的柱状凸起和所述布线基板的焊盘对准,柱状凸起的末端部加有焊料膜;
加热并仅将所述柱状凸起的末端部焊接至所述布线基板的焊盘;和
清洗并除去所述焊剂。
一种制造根据本发明另一方面的半导体器件的方法,包括步骤:
用等离子体激发的惰性气体物理激波,清洗形成在半导体元件电极上的柱状凸起末端部表面和布线基板的焊盘表面;
将所述柱状凸起和所述布线基板的焊盘对准;和
在所述柱状凸起和所述布线基板之间加压,粘接所述柱状凸起和所述焊盘。
在本发明中,半导体元件和布线基板之间的连接系统与常规的连接系统是不同的,在常规系统中,焊料互相连接,或者金的柱状块与布线基板的焊料连接。但是,在本发明中,半导体元件侧的柱状块和布线基板的焊盘通过少量焊料连接,或者不通过焊料直接连接。此外,在本发明中,即使用焊料连接,柱状块和焊料的接触也只限于柱状块的上表面,或者仅仅是其上表面和侧表面极小的部分。柱状块是用在焊接温度下不熔化的金属,以电解镀敷法等形成的,由于它不被回流变圆,所以相对于底部尺寸能形成比较高的块。另外,当半导体芯片装上布线基板时,柱状块不熔化,而是保留早期成形阶段的形状。这使布线基板和半导体芯片之间的距离能充分保证。这还能在倒装晶片连接后,使得欠填充树脂能容易并高可靠性进行充填。也就是说,关于焊料的连接,在精细间距、块也是小直径尺寸时,能使半导体芯片和布线基板之间的裂隙减小,获得显著的实用性和可靠性。
能够进行晶片的批料投配处理,这一点将被认为是例如用电解镀敷法或非电镀敷法形成柱状块的其他特征。由此,能够进行比常规的球加载供应方法成本低的制造。在用具有焊剂活性效果的热固性树脂,代替在半导体晶片的布线基板上组装时用来清除块表面氧化膜的焊剂的情况下,清洗过程能被消去。这有助于清洗过程的缩减,使成本降低或者没有需清洗的废料。因此,可靠性的改善效果增强。
另外,由于能减少或取消所用的焊料量,所以能使α辐射剂量(它是不正常工作的原因之一)减少或降为零。这有助于改善可靠性。
根据本发明,在组装时,焊料不会向上沾湿远于块的柱形基底。因焊料进入接合膜/粘接膜或粘接膜/接合膜的界面而致的界面剥离,能得以防止,因而能改善可靠性。
还有,当做成的焊接结构是焊料向上沾湿远至柱状块的侧表面的一部分时,在形成块的时候要增加处理过程。但是,当柱状块和焊料的接触表面区域加宽时,应力被分布开来,焊接部分的可靠性能够提高。
在本发明的半导体器件制造方法中,盖膜或焊料镀敷被形成在柱状块的上表面,或其上表面或侧表面的一部分。所以,能稳定地制出这样的焊接结构,其中,焊料能覆盖柱状块的整个上表面,或者焊料能覆盖整个上端部。因此,能防止柱状块和粘接膜之间的焊接强度降低或形成应力集中部分,获得可靠的连接部。
附图说明
图1是本发明的半导体元件第一实施例的剖视图。
图2是本发明的半导体元件第二实施例的剖视图。
图3是本发明的半导体元件第三实施例的剖视图。
图4是本发明的半导体元件第四实施例的剖视图。
图5是本发明的半导体元件第五实施例的剖视图。
图6是本发明的半导体元件第六实施例的剖视图。
图7是本发明的半导体元件第七实施例的剖视图。
图8是本发明的半导体元件制造方法第一实施例的剖视图。
图9是本发明的半导体元件制造方法第二实施例的剖视图。
图10是本发明的半导体元件制造方法第三实施例的剖视图。
图11是本发明的半导体元件制造方法第四实施例的剖视图。
图12是本发明的半导体元件制造方法第五实施例的剖视图。
图13是半导体器件第一实施例的剖视图。
图14是半导体器件第二实施例的剖视图。
图15是半导体器件第三实施例的剖视图。
图16是半导体器件第四实施例的剖视图。
图17是半导体器件第五实施例的剖视图。
图18是半导体器件第六实施例的剖视图。
图19是本发明的半导体器件制造方法第一实施例的剖视图。
图20是本发明的半导体器件制造方法第二实施例的剖视图。
图21是本发明的半导体器件制造方法第三实施例的剖视图。
图22是本发明的半导体器件制造方法第四实施例的剖视图。
图23是本发明的半导体器件制造方法第五实施例的剖视图。
图24是本发明的半导体器件制造方法第六实施例的剖视图。
图25是本发明的半导体器件制造方法第七实施例的剖视图。
图26是本发明的半导体器件制造方法第八实施例的剖视图。
图27是本发明的半导体器件制造方法第九实施例的剖视图。
图28是本发明的半导体器件制造方法第十实施例的剖视图。
图29是本发明的半导体器件制造方法第十一实施例的剖视图。
图30是本发明的半导体器件制造方法第十二实施例的剖视图。
图31是本发明的半导体器件制造方法第十三实施例的剖视图。
图32是本发明的半导体器件制造方法第十四实施例的剖视图。
图33是本发明的半导体器件制造方法第十五实施例的剖视图。
图34是本发明的半导体器件制造方法第十六实施例的剖视图。
图35是半导体元件的常规示例的透视图。
图36是半导体元件的常规示例的透视图。
具体实施方式
下面,将参考附图,描述本发明的优选实施例。图1是根据本发明的半导体元件第一实施例的剖视图。如图1所示,在半导体衬底1上形成与内部电路连接的电极2。在半导体衬底1上,覆盖以覆盖膜3,它在电极2上有一个开口。在电极2上,经过由例如钛(Ti)和铜(Cu)构成的粘接膜4和粘接膜5,形成由例如铜构成的柱状块6。柱状块6的侧表面形成防沾湿膜7,防止焊料粘着并向上沾湿。柱状块6可使用除铜以外的铜合金,或镍和镍合金制成。
图2是本发明的半导体元件第二实施例的剖视图。在图2中,与图1用于解释的名称相同的那些部件,以相同的参考号码指示,省略和简化重复的解释(其他实施例也作类似的省略)。本实施例与图1所示第一实施例结构的不同之处是,形成由金(Au)构成的盖膜8,盖膜8防止柱状块6氧化,并划出焊接时的焊料沾湿区域。
图3是本发明的半导体元件第三示范性实施例的剖视图。它与本发明的图1所示第一实施例结构的不同之处是,在柱状块6的上表面或侧表面的一部分上形成由金(Au)构成的盖膜8,盖膜8防止柱状块6氧化,并划出焊接时的焊料沾湿区域,并且,防沾湿膜7从形成有盖膜8的柱状块6侧表面部分被除去。
关于第二和第三实施例,当盖膜8由高可沾湿性材料形成,覆盖在柱状块上时,防沾湿膜可以省去。另外,盖膜可用已知为预涂助溶剂材料的树脂材料形成,这种树脂材料在焊接时被助溶剂溶化,以此代替金属盖膜。
图4是本发明的半导体元件第四实施例的剖视图。在实施例与图1所示的第一实施例结构的不同之处是,焊料镀敷膜9形成在柱状块6的上表面。
图5是本发明的半导体元件第五实施例的剖视图。本实施例与图1所示的第一实施例结构的不同之处是,焊料镀敷膜9形成在柱状块6的侧表面的一部分上,并且,防沾湿膜7被从柱状块6侧面部分有焊料镀敷膜9形成之处除去。
图6是本发明的半导体元件第六实施例的剖视图。本实施例与图4所示的第四实施例结构的不同之处是,在焊料镀敷膜9的上表面上形成薄金层10。
图7是本发明的半导体元件第七实施例的剖视图。本实施例与图5所示的第五实施例结构的不同之处是,在焊料镀敷膜9的上表面或侧表面上形成薄金层10。
图8A至8E是本发明半导体元件制造方法的顺序的剖视图。如图8a所示,电极2和半导体衬底1的覆盖膜3的前表面,用溅射法等,覆盖有接合膜4和粘接膜5。接合膜4最好用钛形成。但除钛外,含钛合金例如氮化钛、钛/钨合金的单层或多层,含铬,铬/铜合金的单层或多层,可用来替代。粘接膜5最好用铜形成,但如果与不是用铜形成的柱状块(镀铜膜等)的粘结力强,并且电阻在小批金属范围的话,合成材料则不受限制。
下面,如图8B所示,以光阻材料形成镀敷阻挡膜19,其厚度大于将要形成的块的高度,并且在电极2上有开口。使其成为掩模,进行电解电镀,形成柱状块6。
然后,如图8C所示,通过灰化等方法除去镀敷阻挡膜19,再以柱状块6作掩模,将暴露部分的粘接膜5和接合膜4蚀刻除去。
往下,如图8D所示,在氧化性气氛中进行热处理,以在柱状块6的表面获得防沾湿膜7。
接着,如图8E所示,在暴露于惰性气体例如氩(Ar)离子区后,只除去柱状块6上表面的防沾湿膜。
替代将多余的防沾湿膜暴露在惰性气体等离子体中以便除去的方法,是在用掩模覆盖不需要形成防沾湿膜的部分以后,进行氧化处理,然后将掩模除去。防沾湿膜7可用薄膜成形工艺例如等离子CVD法,由氧化硅膜或碳化硅膜等淀积形成。在这种情况下,在前面形成防沾湿膜以后,多余的防沾湿膜被暴露在惰性气体的等离子体中,以待除去。如果用薄膜成形工艺例如CVD法形成防沾湿膜7,能在接合膜4和粘接膜5的侧表面获得防沾湿膜7,其膜厚几乎等效于柱状块6的侧表面。
图9A至9E是本发明半导体元件生产方法第二实施例的处理顺序剖视图。在本实施例中,上至图9B所示的处理与第一实施例是相同的。
然后,如图9C所示,用电解镀敷法或非电镀敷法,在柱状块6的上表面形成盖膜8。如图9D所示,除去镀敷阻挡膜19以及在它下面的粘接膜5和接合膜4。然后经过氧化性气氛中的热处理,在柱状块6的侧表面上形成防沾湿膜7。
图10A至10F是本发明半导体元件制造方法的第三实施例的处理顺序剖视图。在本实施例中,上至图10B所示的处理与第一实施例相同。然后对镀敷阻挡膜19进行半蚀刻,这样,柱状块6侧面的一部分就暴露出来,如图10C所示。
接着,用电解镀敷法或非电镀敷法,在柱状块6的上表面和上侧面形成盖膜8,如图10D所示。在经过氧化性气氛中的热处理,除去镀敷阻挡膜19以及下面的接合膜4和粘接膜5之后,在柱状块6的侧表面形成防沾湿膜7,如图10F所示。
参考第二和第三实施例,防沾湿膜7可以用薄膜形成工艺,例如等离子CVD法形成。那时,使用掩模覆盖不要形成膜的区域之后,可以形成需要的膜。所述其他实施例也相同。
在第二和第三实施例中,金被优选用作盖膜8的材料。但是,任何好的焊料可沾湿性材料,和可防止柱状块氧化的材料都能够使用。作为示例,金合金、锡、铟或钯被认为是可以利用的。
图11A至11E是本发明半导体元件制造方法的第四实施例的处理顺序剖视图。在本实施例中,上至图11B所示的处理与第一实施例相同。焊料镀敷膜9用电解镀敷法在块的柱状形成后,接着在柱状块6的上表面形成。(图11C)。下面,镀敷阻挡膜19其下面的接合膜4和粘接膜5,被除去(图11D)。然后,在柱状块6的上表面经过氧化性气氛中的热处理形成防沾湿膜7之后,对焊料镀敷膜9上的氧化膜进行溅射清除(图11E)。
图12A至12F是本发明半导体元件制造方法和第五实施例的处理顺序剖视图。本实施例与图11所示的第四实施例相同,不同之处是在形成焊料镀敷膜9之前,作半蚀刻处理(图12C)。
在第四和第五实施例中,用锡/低熔点铅合金可形成焊料镀敷膜9,但不限于此,用作焊接材料的材料,根据需要也是可利用的。最好采用不含铅的焊料。此外,在第四和第五实施例中,在焊料镀敷膜9成形之后,相继地进行电解或无电镀敷。在焊料镀敷膜9上可薄薄地形成金属膜,如图6和图7所示。
用无电镀敷法可形成块。在这种情况下,以图9所示的状态完成接合膜和粘接膜的构成,以便形成阻挡膜,它在形成块的部位上有一个开口。然后,例如用锌进行活化处理,根据需要除去不必要的活性层,并且,在阻挡膜除去之前,执行例如镍的无电镀敷以形成块。块可直接形成在电极上,而不形成接合膜和粘接膜。
图13是本发明半导体器件的第一实施例的剖视图。根据本发明的半导体元件被装在布线基板12上,基板的表面上形成有焊盘14和镀敷阻挡膜13。在本实施例中,半导体元件的柱状块6仅通过在上表面(在本说明书中,与柱状块的电极2相对的侧面称为上表面)上的焊料带11与布线基板12上的焊盘14连接。
图14是本发明半导体器件的第二实施例的剖视图。在实施例与图13所示的第一实施例结构的不同之处是,在柱状块6的上表面形成盖膜8。
图15是本发明的半导体器件第三实施例的剖视图。本实施例与图13所示第一实施例结构的不同之处是,半导体元件的柱状块6不仅在上表面而且在它的侧表面的第一部分,与焊料带11连接。
图16是本发明半导体器件的第四实施例的剖视图。
本实施例与图15所示第三实施例结构的不同之处是,在半导体元件的柱状块6上表面或它的侧表面的一部分形成盖膜8。
图17是本发明半导体器件的第五实施例的剖视图。在本实施例中,半导体元件的柱状块6不是借助于焊料而是直接与布线基板12上的焊盘14连接。
图18是本发明半导体器件的第六实施例的剖视图。在本实施例中,半导体元件的柱状块6经过盖膜8与布线基板12上的焊盘14连接。
图19A至19C是本发明半导体器件制造方法的第一实施例处理顺序的剖视图。本实施例涉及图1所示半导体元件的组装方法。焊剂15提供于半导体元件的柱状块6的末端部。另外,在布线基板12的焊盘14上事先形成焊料膜16,如图19A所示。在校准半导体元件以便使柱状块6定位到焊盘14上之后,半导体元件被装在布线基板12上,将受到焊料回流处理,柱状块6通过焊料带11与焊盘14连接,如图19B所示。然后,在以欠填充树脂17填充之前,进行对焊剂15的清洗和除去,并固化,如图19C所不。
焊料膜16可以是焊糊层,或是焊料回流层。锡/低熔点铅焊料最好用于焊料膜16,但不限于此。锡/铅(除低熔点外),锡/银,锡/铜,锡/锌,和将另外的元素加至这些材料的合金,都可以使用。
在本实施例中,焊剂15加至柱状块6的侧表面。替代此法,焊剂15也可以加在焊料膜16或焊盘14上。这一点在其他的实施例也有所述。在本实施例的焊接过程中,半导体元件最好以预定的压力压至布线基板。从而,可以避免应力集中的收缩结构。
图20A至20C是本发明半导体器件制造方法的第二实施例处理顺序的剖视图。本实施例涉及图2所示半导体元件的组装方法。与图19所示第一实施例结构的不同之处是,在柱状块6的表面形成盖膜8。顺便说说,当用能熔化在薄的金(或金合金)膜或焊剂中的树脂膜,形成盖膜8时,由于在焊料熔化时,盖膜8熔化焊料或焊剂之中,在焊料回流处理完成之后,该盖膜8消失,如图20B’和20C’所示。
图21A至21C是本发明半导体器件制造方法的第三实施例处理顺序的剖视图。本实施例涉及图4所示的半导体元件的组装方法。焊剂15加至柱状块6的末端部,如图21A所示,只在柱状块6上表面形成有焊料镀敷膜9,在对准之后,半导体元件被装在布线基板上,焊料回流过程产生焊料带11,如图11所示。接着的处理与图19所示的第一实施例相同。图22A至22C是本发明半导体器件的第四实施例处理顺序的剖视图。本实施例涉及图1所示半导体元件的组装方法。与图19所示第一实施例结构的不同之处是,替代焊剂,使用具有焊剂活性效果的热固性树脂(此后称活性树脂)焊接。也就是说,活性树脂18提供到半导体元件的柱状块6的末端部,而且,在布线基板12和焊盘14事先形成焊料膜16,如图22A所示。在对准之后,半导体元件被装在布线基板12上,然后经受焊料回流处理,柱状块6通过焊料带11与焊盘14连接,如图22B所示,再以欠填充树脂17填充并固化,保留活性树脂18,如图22C所示。
在本实施例中,活性树脂18加至柱状块6的侧表面。但是,作为替代,也可以加至焊料膜16或焊盘14。这在其他实施例也说到。
图23A至23C是本发明半导体器件制造方法第五实施例的处理顺序的剖视图。本实施例涉及图2所示半导体元件的组装方法。与图20所示第二实施例不同之处仅是使用盖膜8进行焊接,因此,省略详细说明。顺便说一下,当用能溶解在焊剂中的薄的金膜(或金合金)或树脂膜,形成盖膜8时,盖膜8在焊料熔化时熔化在焊料或活性树脂中,因此,在焊料回流处理完成之后,盖膜8消失,如图23B’和23C’所示。
图24A至24C是本发明的半导体器件制造方法的第六实施例处理顺序的剖视图。本实施例涉及图4所示半导体元件的组装方法。本实施例与图21所示第三实施例不同之处仅是用活性树脂18代替焊剂进行焊接。因此,详细说明将被省略。
图25A至25C是本发明的半导体器件制造方法的第七实施例的剖视图。本实施例涉及图3所示半导体元件的组装方法。焊剂15供应至其上表面和侧表面的一部分形成有盖膜8的柱状块6的末端部,事先在布线基板12的焊盘14上形成焊料膜16(图25A)。在对准之后,半导体元件被装在布线基板12上,并经受回流焊接处理。然后,焊料沿盖膜8向上沾湿,以便使焊料带11形成在远至柱状块6侧表面,如图25B所示。在填充并固化欠填充树脂17之前,清洗并除去焊剂15,如图25C所示。顺便说说,当用能熔化在薄的金(或金合金)膜或焊剂中的树脂膜,形成盖膜8时,由于盖膜8在焊料熔化时熔化在焊料或焊剂中,所以在焊料回流处理完成之后,盖膜8消失,如图25B’和25C’所示。
图26A至26C是本发明的半导体器件制造方法的第八实施例处理顺序的剖视图。本实施例涉及图5所示半导体元件的包装方法。由于本实施例与图21所示的第三实施例相同,不同之点是在柱状块6侧表面的一部分形成焊料镀敷膜,所以,详细说明被省略。
图27A至27C是本发明半导体元件的第九实施例处理顺序的剖视图。本发明涉及图3所示半导体元件的组装方法。本实施例与图25所示第七实施例不同之处,仅是使用活性树脂18代替焊料进行焊接,因此省略详细说明。顺便说说,当用能熔化在薄的金(或金合金)膜或焊剂的树脂形成盖膜8时,由于在焊料熔化时盖膜8熔化在焊料或焊剂中,所以在焊料回流处理完成之后,盖膜8消失,如图27B’和27C’所示。
图28A至28C是本发明的半导体器件制造方法的第十实施例处理顺序的剖视图。本实施例涉及图5所示半导体元件的组装方法。本实施例与图26所示第八实施例的不同之处,仅是使用活性树脂18代替焊料进行焊接,因此,省略详细说明。
在第七实施例至第十一实施例中,涉及焊剂或活性树脂的氧化膜除去能力和供应量,为了得到内圆角形状,在那里焊料向上沾湿至柱状块侧面的一部分,这是本实施例的特征结构,要按照需要进行调整。
图29A至29C是本发明的半导体器件制造方法的第十一实施例处理顺序的剖视图。本实施例半导体元件的柱状块6上表面或侧面的上部,以盖膜8’进行覆盖,盖膜8’由树脂材料构成,它在焊接时熔化在焊剂中。柱状块6的连接部在大气环境中不被氧化,并保持清洗状态。焊剂事先加至在布线基板12的焊盘14上形成的焊料膜16,如图29A所示。在校准半导体元件致使柱状块6定位至焊盘14上之后,如果半导体元件被装在布线基板12上,并受到焊料回流处理,则盖膜8’熔化,柱状块6的连接部被暴露,柱状块6被焊接至焊盘14,如图29B所示。然后,在填充和固化欠填充树脂17之前,清洗和除去焊剂15,如图29C所示。
在本实施例中,焊剂15被加至焊料膜16。但是,作为替换,可加至柱状块6的侧表面。同样,代替焊剂,也可使用具有焊剂作用的活性树脂。
在第七实施例至第十实施例中,涉及焊剂或活性树脂的氧化膜的除去能力和供应量,有必要进行适当的调整,以便得到内圆角的形状,其中焊料向上沾湿元至柱状块侧面的一部分,这是本实施例的特征结构。这就是说,在本发明半导体器件的制造过程中,要得到需要的连接形状,最重要的是焊剂是否供应合适的数量,同时活性树脂具有合适的氧化膜除去能力。如果氧化膜除去能力太强,焊料就会向上沾湿远至不希望沾湿的柱状块根部,并假定包围柱状块。因此,这种可能性随着焊料在柱状块与粘接膜之间,或者在粘接膜与接合膜之间推进而上升,减小粘结强度,引起剥落。同样,如果氧化膜除去能力太弱,坚固的金属连接不能在焊料与铜块的界面实现,由于这个原因,连接性能变得很差。因此,重要的是选择焊料或具有合适的氧化膜除去能力的话性树脂,和均匀地供应合适的数量。
但是,在本发明的半导体元件焊接中,焊剂或活性树脂不是必不可少的,当连接界面和焊料膜表面保持足够清洁时,半导体元件不使用这些材料也可以焊接。下面第十二和第十三实施例涉及不使用焊剂和活性树脂的焊接方法。
图30A至30C是本发明的半导体器件制造方法的第十二实施例处理顺序的剖视图。本实施例涉及图7所示半导体元件的组装方法。在本实施例中,当在提供于柱状块6上部的焊料镀敷膜9表面上形成金膜10时,金膜10也在焊盘14上形成,如图10A所示。通过形成这些金膜,使焊料镀敷膜9和焊盘14保持没有氧化的清洁状态。在对准半导体元件以使柱状块6定位在焊盘14上之后,如果半导体元件被装在布线基板12上并受到焊料回流处理,金膜10就熔化在焊料中,柱状块6经过焊料带11与焊盘14连接,如图30B所示,然后,在填充欠填充树脂17之后,进行固化,如图30C所示。
在本实施例中,在焊料镀敷膜9和焊盘14两者上都形成金膜10。但是,只在它们之一形成金膜10也是足够的。在这种情况下,一系列的堆放、输送和组装处理在非氧化性气氛中进行,例如真空和还原气氛。这里,重要的是连接部表面不要被污染。
图31A至31C是本发明的半导体器件制造方法的第十三实施例处理顺序的剖视图。本发明这个实施例的半导体元件的柱状块6上表面和侧面上部,用薄的金膜10覆盖。金膜10也在焊盘14的焊料膜表面上形成,如图31A所示。在对准之后,半导体元件被装在布线基板12上,并受到焊料回流处理,金膜10熔化在焊料中,柱状块6经过焊料带11与焊盘14连接,如图11B所示,然后,填充欠填充树脂17之后固化,如图31C所示。
本实施例涉及图7所示半导体元件的组装方法。在本实施例中,当金膜10在提供于柱状块6上表面的焊料镀敷膜9表面上形成时,金膜10也可在焊盘14上形成,如图31A所示。通过形成这些金膜,焊料镀敷膜9和焊盘14的表面保持没有氧化的清洗状态。在对准半导体元件以使柱状块6定位在焊盘14上之后,如果半导体元件被装在焊盘14上,并受到焊料回流处理,金膜10就熔化在焊料中,柱状块6经过焊料带11与焊盘14连接,如图31B所示,然后,填充欠填充树脂17之后固化,如图31C所示。
图32A至32C是本发明的半导体器件制造方法的第十四实施例处理顺序的剖视图。半导体元件和布线基板的表面被暴露在惰性气体例如氩的等离子体气氛中,焊盘14与柱状块6的连接面被清洗,如图32A所示。在对准之后,半导体元件被装在布线基板12上,通过加压将柱状块6的末端部粘贴至焊盘14,如图32B所示。这时,可以采用加热或超声波方法之一种,或使用两者的组合。然后,注入欠填充树脂17并固化,如图32C所示。
图33A至33C是本发明的半导体器件制造方法第十五实施例处理顺序的剖视图。在本实施例中,在布线基板的焊盘14上,事先形成由金等构成的盖膜8。与本实施例中图32所示的第十一实施例结构的不同之处,仅是在焊盘14上形成盖膜8,因此省略详细说明。
在本实施例中,盖膜8只在布线基板的焊盘侧形成,相反地盖膜也可只在柱状块侧形成。同样,类似于第十一实施例和第十二实施例,当盖膜至少在一个连接侧表面上也没有形成时,连接最好在真空或非氧化性气氛中进行。也就是说,最好保持来自清洗处理的真空或非氧化性气氛状态的环境,直到用等离子体完成连接。
图34A至34C是本发明的半导体器件制造方法的第十四实施例处理顺序的剖视图。在本实施例中,关于半导体元件,可在柱状块6的上表面上形成盖膜8,也可以事先在布线基板的焊盘14上制备盖膜8。本实施例与图32所示第十一实施例结构不同之处,仅是在柱状块6或焊盘14上形成盖膜8,因此省略详细说明。(参看实施例3)
下面,将与附图一起,说明本发明的一些实施例。(实施例1)
现在,将参考图19,描述涉及本发明一个实施例的半导体元件的制造方法。
首先,在形成在半导体衬底1上的铝合金布线层上,形成硅氧化膜的覆盖膜3,并且对形成在布线层末端的的电极2上的覆盖层进行清除。然后,采用溅射方法,按顺序在整个表面上形成用作接合膜4的钛膜和用作粘接膜5的铜膜。覆盖层膜的厚度确定为4.5μm,接合膜的厚度确定为60nm,和粘接膜的厚度确定为500nm。其次,通过电解镀敷形成镀敷阻挡膜19,并且铜被沉积为柱状块6。这时,柱状块的尺寸被确定为直径约为140μm,高度为约为90μm。接着,进行镀金,在柱状块的上表面形成厚度约为0.1μm的盖膜8。在剥落阻镀膜之后,利用铜块作掩模,通过湿刻除去粘接膜和接合膜的多余部分。然后,经过氧化性气氛中的热处理之后,在柱状块侧形成防沾湿膜7,完成铜柱状块的构形。防沾湿膜7在组镀剥落之后,可立即形成。
下面,将参考图20解释在布线基板上组装具有铜柱状块的半导体元件的方法。首先,通过挤压将焊剂15均匀地加到光滑和平坦的例如玻璃板上,厚度约40μm。然后,推压柱状块,焊剂被输送至末端。一种输送焊剂的方法是向引脚输送焊剂的方法。这种方法不受限于向铜块末端稳定供应焊剂。此后,半导体芯片被装到布线基板上。锡/低熔点铅合金焊糊,通过印刷在焊盘部分事先供给布线基板。然后,在焊料回流处理之后,半导体元件板与焊剂布线基板表面平行地被推压,焊料上部被压碾,以使高度能均匀。往下,在对准半导体元件使柱状块可定位在布线基板的焊盘上之后,半导体元件被装到布线基板上。然后,随着半导体元件同时受到焊料回流处理和被挤压,柱状块6连接至布线基板的焊盘14。关于半导体元件与布线基板的连接形式,焊料沾湿性好的盖膜只在柱状块的上表面形成。由于在侧表面上形成防沾湿膜,所以,焊料不会转绕至侧面,只是柱状块的上表面与焊盘连接。也就是说,焊料不会从柱状块向上沾湿远至柱状块与粘接膜之间的部分,或粘接膜与接合膜之间的部分,以致引起连接强度下降,也不构成类似于收缩结构那样的应力集中部分。这有助于得到可靠的结构。下面,在清洗和除去焊剂15之后,欠填充树脂17从侧面被灌注。然后,在填充和固化之后,半导体元件的组装完成。在本实施例中,在倒装晶片装在这里之前,一旦焊糊供应至布线基板,首先将被熔化和固化。但是,不用熔化和固化焊糊,倒装晶片也可以装入并连接。(实施例2)
关于本发明的第二实施例,将结合附图10,解释半导体元件的制造方法。在与第一实施例类似的方法中,如图10B所示,在电极2上,形成厚度为60nm的接合膜,厚度为500nm的粘接膜,以及柱状块6,柱状块6具有约为140μm的直径和90μm的高度,然后,将氧等离子体注入镀敷阻挡膜19,使它们受到蚀刻处理。然后,柱状块的上部暴露约15μm,并用金镀敷,从而形成厚度约为0.1μm的盖膜8。接着,镀敷阻挡膜剥落,并使用柱状块作掩模,通过湿蚀刻,进行粘接膜和接合膜多余部分的化学清除,并在氧化性气氛中经受热处理。因此,在铜柱状块侧表面上形成防沾湿膜7。下面,将结合图25解释在半导体元件的布线基板的组装方法,该半导体元件具有由上述方法形成的柱状块。如图25A所示,事先在布线基板的焊盘上形成焊料膜16,接着焊剂15加至柱状块6的末端部。然后,在对准半导体元件以使柱状块定位在布线基板的焊盘上之后,将半导体元件装到布线基板上。然后,对半导体元件进行焊料回流处理并同时加压,这样柱状块6就连接至布线基板的焊盘14。关于半导体元件和布线基板的连接结构,由于在柱状块的上表面和侧表面的一部分形成粘湿性好的盖膜,在侧表面上形成防沾湿膜,所以能以焊料带11包围柱状块的上部的这种方式形成连接。这样就不会出现焊料向上粘湿远至柱状块基底的情况。下面,在清洗和除去焊剂15之后,欠填充树脂17从侧面灌入,在填充之后被固化。因此,半导体元件的组装完成。(实施例3)
作为本发明的第三实施例,现在将结合图12解释半导体元件的制造方法。类似于第一实施例,在形成覆盖层之后,溅射铬/铜用作接合膜4,溅射铜用作粘接膜5,这样,在整个表面形成接合膜和粘接膜。接合膜4的厚度确定为100nm,粘接膜5的厚度确定为500nm。在通过电解镀敷,形成镀敷阻挡膜19,以及形成具有直径约为140μm和高度约为90μm的铜柱状块6之后,通过干法进行蚀刻处理,利用镀敷阻挡膜和铜的不同蚀刻速度对铜块的上部进行暴光。将被暴光部分的高度设置为约15μm。其次,通过电解镀敷,在铜块上形成厚度为15μm的、由含锡重量为96.5%和含银重量为3.5%的低熔点合金构成的焊料镀敷膜9。
由于这时焊料镀敷膜9也在柱状块上形成形成,所以,控制膜的厚度是重要的,这样在下一步熔化连接时,不会发生电极之间的短路。其次,在经受氧化性气氛中的热处理之前,通过湿刻剥落阻镀膜,除去过量的接合膜和粘接膜,这样在柱状块6侧表面形成防沾湿膜7。然后,通过经受等离子体处理,焊料镀敷膜9上形成的氧化膜被除去。
下面,将结合图28,解释用上述方法形成的半导体元件组装到布线基板的方法。通过挤压平坦和光滑的板例如玻璃板,将厚度约为40μm的活性树脂18均匀地加至铜块上焊料镀敷膜9的末端。对着这块板推压柱状块,热固性的树脂(活性树脂18)输送至末端。这种输送活性树脂的方法不受限于能够向柱柱状块末端例如引脚输送稳定的供应。
通常,焊剂用于除去块表面上的氧化膜。关于组装之后的焊料清洗,有必要引入专门的清洗装置,以清洗半导体元件与布线基板之间窄裂隙。这需要较长的清洗时间,可以把它看成是成本上升的原因。另外,残余物的清洗易有遗留,构成可靠性下降的因素。从往后的细微间距趋势,可预料裂隙的清洗变得更为困难。如果象这个实施例应用活性树脂,省去清洗,减少工时以及工厂和设备的投资,通过省去清洗,在改善成品率和提高组装可靠性方面,是有效的。
在加上活性树脂18之后,半导体元件被对准并装到布线基板上,经受焊料回流处理,柱状块与布线基板的焊盘连接。在末端用欠填充树脂填充裂隙并固化,半导体元件的组装完成。
这里是活性树脂被输送并装载,焊剂可用来代替活性树脂。如果金薄薄地镀敷在柱状块上形成的焊料膜上,则连接进一步得到改善,达到不用焊剂也能连接的程度。
在本实施例中,向块的末端进行很小量的树脂输送,此后,用欠填充树脂填充。如果使用高于欠填充树脂等效可靠性的活性树脂,则树脂的填充也可以在不进行树脂灌注的情况下以这种方式实现,即适量的活性树脂供应至布线基板,半导体芯片装入板中,在焊料回流处理时,也进行树脂固化。在实施例1至3的情况下,为了防止氧化的目的,树脂膜可提供在焊盘、焊料膜和焊料镀敷膜上。另外,代替被输送至块末端并用于连接的焊剂,活性树脂也能够使用,活性树脂具有焊剂的效果,即在连接时由于热量关系而固化,连接之后增强连接部。(实施例4)
参考本发明的第四实施例,下面将结合图2解释半导体元件的制造方法。首先,硅氧化物沉积在整个半导体衬底1上,形成覆盖膜3。在以顺序方式进行铜膜溅射,确定钛作为接合膜4,确定铜膜作为粘接膜5之前,除去覆盖膜3的一部分,由铝合金制成的电极2表面暴露。因此,在整个表面上形成接合膜和粘接膜。覆盖层的厚度设置为4.5μm,接合膜的厚度设置为60nm,和粘接膜的厚度设置为500nm。其次,形成镀敷阻挡膜19,并且,通过电解镀敷沉积铜,得到柱状块6。柱状块6的尺寸设置为直径约140μm,高度约90μm。接着,通过在柱状块上表面镀敷金,继续形成厚度约5μm的盖膜8。然后,剥落镀敷阻挡层,并使用铜块作掩模,通过湿刻,除去接合膜和粘接膜的多余部分。在这个实施例中,不形成防沾湿膜。
下面,将结合图34,解释在布线基板上组装具有铜块的半导体元件的过程。在本实施例中,盖膜8(镀金膜)也在布线基板12的焊盘14上形成。正是在将半导体元件组装到布线基板之前,对半导体元件和布线基板进行氩等离子体清洗。此后,对准半导体元件和布线基板,将半导体元件装至布线基板。然后,加上每块约5至50gf(0.049-0.49N)的负载,同时加热到350度,以获得块和焊盘之间的连接。在这里,因为不使用焊剂,所以不需要清洗。紧接此后,欠填充树脂从侧面灌入,在填充之后得到固化的树脂。
如前所述,由于使用小量焊料或不使用焊料进行与布线基板焊盘的连接,所以,由α射线导致的软误差可被减小,提高可靠性。另外,由于与柱状块的焊料连接的部分限于柱状块的上表面,或邻近上表面的块的侧表面,所以块的直径不必厚,即使块变高,并且,响应高的引脚总数,半导体板和布线基板之间的距离能有保证。因此,即使LSI的发展有高密度趋势,根据本发明,填充以欠填充树脂,能简易而可靠地进行。此外,根据本发明,焊料不向上沾湿远至柱状柱底部招致柱状块和粘接膜之间,或粘接膜和接合膜之间连接强度降低。因此,能达到改善可靠性的目的。
因为本发明的柱状块是在晶片阶段用电解镀敷法形成的,与焊球装载法相比,能以低成本制造。另外,根据一个实施例,使用有焊剂活性效果的热固性树脂(活性树脂),代替倒装晶片组装时用的焊剂,由于清洗过程减少和取消对残余物的清洗,能以低成本实现可靠性的改善。

Claims (43)

1.一种半导体元件,其特征在于:所述半导体元件包括:
柱状凸起,其用作块,形成在半导体衬底上的电极上并暴露在所述半导体衬底上;和
盖膜,其覆盖在所述柱状凸起的侧表面上部和上表面,所述盖膜确定防止所述柱状凸起氧化和焊接时被焊料沾湿的区域。
2.一种半导体元件,其特征在于:所述半导体元件包括:
柱状凸起,其用作块,形成在半导体衬底上的电极上并暴露在所述半导体衬底上;和
防沾湿膜,其至少形成在所述柱状凸起的侧表面的靠近所述电极的部分上。
3.如权利要求1或2所述的半导体元件,其特征在于:所述柱状凸起经过接合膜或粘接膜,形成在所述电极上。
4.如权利要求2所述的半导体元件,其特征在于:所述柱状凸起的上表面,或所述柱状凸起的侧表面上部和上表面,被盖膜覆盖,所述盖膜防止所述柱状凸起氧化,并划分由所述柱状凸起的焊料沾湿的范围。
5.如权利要求1或4所述的半导体元件,其特征在于:所述盖膜由金、金合金、锡、铟、或钯形成。
6.如权利要求1或4所述的半导体元件,其特征在于:所述盖膜是树脂覆盖膜,其在焊接时在焊剂中熔化。
7.如权利要求2所述的半导体元件,其特征在于:所述柱状凸起的上表面,或所述柱状凸起的侧表面上部和上表面,被焊料膜覆盖。
8.如权利要求7所述的半导体元件,其特征在于:所述焊料膜由其中不含铅的材料形成。
9.如权利要求7或8所述的半导体元件,其特征在于:所述焊料膜被覆盖以薄金膜或金合金膜。
10.如权利要求2至9中任一项所述的半导体元件,其特征在于:所述防沾湿膜是氧化物膜或氮化物膜。
11.如权利要求2至9中任一项所述的半导体元件,其特征在于:所述防沾湿膜是由所述柱状凸起的表面氧化形成的膜。
12.如权利要求1至11中任一项所述的半导体元件,其特征在于:所述柱状凸起由铜或铜合金形成。
13.一种制造半导体元件的方法,其特征在于:所述方法包括步骤:
在有电极形成于其上的整个半导体衬底上,形成金属膜,作为镀敷电极;
在所述金属膜上形成阻挡膜,其在所述电极位置有开口;
用电解镀敷法,以柱的形状沉积高电导率金属,形成柱状凸起;
除去所述阻挡膜;
用所述柱状凸起作为掩模,蚀刻除去所述金属膜;和
在所述柱状凸起表面形成防沾湿膜。
14.一种制造半导体元件的方法,其特征在于:所述方法包括步骤:
在其上有电极的半导体衬底上,形成阻挡膜,其在所述电极位置有开口;
通过对无电镀敷的活化处理,形成活化处理层;
除去所述阻挡膜上的所述活性层;
用无电镀敷法,在所述开口沉积高电导率金属,形成柱状凸起;
除去所述阻挡膜;和
在所述柱状凸起的表面形成防沾湿膜。
15.如权利要求13或14所述半导体元件的制造方法,其特征在于:在所述柱状凸起的表面形成防沾湿膜以后,除去在所述柱状凸起连接至组装基板的部分上的所述防沾湿膜。
16.如权利要求13或14所述半导体元件的制造方法,其特征在于:在所述柱状凸起的表面形成防沾湿膜以前,在所述柱状凸起的不应形成防沾湿膜的区域形成掩模,在所述柱状凸起的表面形成防沾湿膜以后,除去所述掩模。
17.如权利要求13至16中任一项所述的所述半导体元件的制造方法,其特征在于:在所述防沾湿膜是用CVD法淀积的硅氧化物膜或氮化物膜。
18.如权利要求13至16中任一项所述的所述半导体元件的制造方法,其特征在于:在所述柱状凸起的表面上所述防沾湿膜的形成,是使所述柱状凸起暴露在氧化气氛中,在所述柱状凸起的表面上形成氧化物膜。
19.如权利要求15、17和18中任一项所述的所述半导体元件的制造方法,其特征在于:所述柱状凸起连接部分的所述防沾湿膜的所述除去,相应于将所述柱状凸起暴露在惰性气体的等离子体中。
20.如权利要求13至19中任一项所述的所述半导体元件的制造方法,其特征在于:在形成所述柱状凸起以后,和除去所述阻挡膜以前,在所述柱状凸起的上表面覆盖盖膜,所述盖膜由比所述柱状凸起难氧化的金属形成。
21.如权利要求13至19中任一项所述的所述半导体元件的制造方法,其特征在于:在形成所述柱状凸起以后,和除去所述阻挡膜以前,对所述阻挡膜施行半蚀刻,使所述柱状凸起的所述侧表面的上部暴露,在所述柱状凸起的上表面和侧表面上部,覆盖比所述柱状凸起难氧化的金属盖膜。
22.如权利要求13和15至19中任一项所述的所述半导体元件的制造方法,其特征在于:在形成所述柱状凸起以后,和除去所述阻挡膜以前,在所述柱状凸起的上表面覆盖焊料膜。
23.如权利要求13和15至19中任一项所述的所述半导体元件的制造方法,其特征在于:所述方法包括步骤:在形成所述柱状凸起以后,和除去所述阻挡膜以前,
对所述阻挡膜施行半蚀刻,使所述柱状凸起的侧表面上部暴露;和
在所述柱状凸起的上表面和侧表面上部覆盖焊料膜。
24.一种半导体器件,其特征在于:所述器件包括:
在半导体元件上的电极上形成的导电柱状凸起;
焊接至所述导电柱状凸起的布线基板焊盘;和
至少覆盖所述柱状凸起的一部分侧表面的防沾湿膜,该部分侧表面靠近所述电极。
25.一种半导体器件,其特征在于:所述器件包括:
在半导体元件上的电极上形成的导电柱状凸起;和
焊接至所述导电柱状凸起的布线基板焊盘,
其中,所述柱状凸起的焊接部分仅是所述柱状凸起的上表面。
26.一种半导体器件,其特征在于:所述器件包括:
在半导体元件上的电极上形成的导电柱状凸起;和
其上焊接所述导电柱状凸起的布线基板焊盘,
其中,所述柱状凸起经金属膜焊接至所述焊盘,所述金属膜比所述柱状凸起难氧化,并形成在所述柱状凸起的所述上表面或所述柱状凸起的所述侧表面上部和上表面。
27.一种半导体器件,其特征在于:所述器件包括:
在半导体元件上的电极上形成的导电柱状凸起;和
其上焊接所述导电柱状凸起的布线基板焊盘,
其中,所述柱状凸起的上表面和所述布线基板的焊盘表面,经过比所述柱状凸起难氧化的金属膜粘接。
28.如权利要求26或27所述的半导体器件,其特征在于:所述难氧化的金属膜由金或金合金形成。
29.如权利要求24至28中任一项所述的半导体器件,其特征在于:所述半导体元件和所述布线基板之间填充以树脂。
30.一种制造半导体器件的方法,其特征在于:所述方法包括步骤:
向形成在半导体元件的电极上的柱状凸起末端部,或者向焊接至那里的布线基板焊盘,供应具有焊剂活性效果的热固性树脂;
对准所述柱状凸起和供有预定量焊料的布线基板焊盘;和
仅将所述柱状凸起的末端部加热,并焊接至所述布线基板的焊盘。
31.一种制造半导体器件的方法,其特征在于:所述方法包括步骤:
向形成在半导体元件的电极上的柱状凸起末端部,或者向焊接至那里的布线基板焊盘,供应具有焊剂活性效果的热固性树脂;
对准所述柱状凸起和供有预定量焊料的布线基板焊盘;
仅将所述柱状凸起的末端部加热,并焊接至所述布线基板的焊盘;和
清洗并除去所述焊剂。
32.如权利要求30或31所述半导体器件的制造方法,其特征在于:至少在所述焊接过程以前,所述柱状凸起的上表面或所述柱状凸起的侧表面上部和上表面,被覆盖以由可沾湿性极好的金属形成的盖膜。
33.如权利要求30或31所述半导体器件的制造方法,其特征在于:在焊接以前,盖膜覆盖在所述柱状凸起的上表面或所述柱状凸起的侧表面上部和上表面,所述盖膜由树脂材料形成,这种树脂材料在进行焊接时,熔化在具有焊剂活性的材料中。
34.一种制造半导体器件的方法,其特征在于:所述方法包括步骤:
向柱状凸起的末端,或者向焊接至那里的布线基板焊盘,供应具有焊剂活性效果的热固性树脂;
将形成在半导体元件电极上、并且其末端有焊料膜的所述柱状凸起和所述布线基板上的焊盘对准;和
仅将所述柱状凸起的末端部加热,并将其焊接至所述布线基板上的焊盘。
35.一种制造半导体器件的方法,其特征在于:所述方法包括步骤:
向柱状凸起的末端,或者向焊接至那里的布线基板焊盘,供应焊接;
将形成在半导体元件电极上、并且其末端有焊料膜的所述柱状凸起和所述布线基板上的焊盘对准;
仅将所述柱状凸起的末端部加热,并将其焊接至所述布线基板上的焊盘;和
除去并清洗掉所述焊剂。
36.一种制造半导体器件的方法,其特征在于:所述方法包括步骤:
将形成在半导体元件电极上的柱状凸起和供有预定量焊料的布线基板焊盘对准;和
仅将所述柱状凸起的末端部加热,并将其焊接至所述布线基板的焊盘;
其中,至少在所述柱状凸起的焊接部分或所述焊盘上焊料的焊接部分之一上,形成薄金膜。
37.一种制造半导体器件的方法,其特征在于:所述方法包括步骤:
将形成在半导体元件电极上、并且其末端有焊料膜的柱状凸起和将要焊接至那里的布线基板上的焊盘对准;和
仅将所述柱状凸起的末端部加热,并将其焊接至所述布线基板的焊盘;
其中,薄金属膜至少形成在所述柱状凸起上的焊料膜和所述焊盘之一上。
38.如权利要求30至37中任一项所述半导体器件制造方法,其特征在于:在所述焊接过程中,在所述半导体元件和所述布线基板之间施加压力。
39.一种制造半导体器件的方法,其特征在于:所述方法包括步骤:
用等离子体激发的惰性气体物理激波,清洗形成在半导体元件电极上的柱状凸起末端部表面和布线基板上的焊盘表面;
将所述柱状凸起和所述布线基板的焊盘对准;和
在对所述半导体元件和所述布线基板进行所述施加压力时,粘接所述柱状凸起和所述焊盘。
40.如权利要求39所述半导体器件的制造方法,其特征在于:所述粘接,用加热和/或超声波振动两者或两者之一方法进行。
41.如权利要求39或40所述半导体器件的制造方法,其特征在于:在所述柱状凸起的上表面和/或所述焊盘的外表面两者之一或两者上,形成难氧化的金属膜,以便经过难氧化的所述金属膜,粘接所述柱状凸起和所述焊盘。
42.如权利要求39至41中任一项所述半导体器件的制造方法,其特征在于:所述柱状凸起和所述焊盘的粘接,在真空或非氧化性气氛中进行。
43.如权利要求30至42中任一项所述半导体器件的制造方法,其特征在于:在所述柱状凸起焊接至所述焊盘,或所述柱状凸起粘接至所述焊盘以后,在所述半导体元件和所述布线基板之间填充树脂。
CNB031042406A 2002-02-07 2003-02-08 半导体元件及其制造方法,和半导体器件及其制造方法 Expired - Lifetime CN100511658C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002030334 2002-02-07
JP2002030334A JP3829325B2 (ja) 2002-02-07 2002-02-07 半導体素子およびその製造方法並びに半導体装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CNA2005100897126A Division CN1873939A (zh) 2002-02-07 2003-02-08 半导体器件的制造方法

Publications (2)

Publication Number Publication Date
CN1437256A true CN1437256A (zh) 2003-08-20
CN100511658C CN100511658C (zh) 2009-07-08

Family

ID=27654741

Family Applications (2)

Application Number Title Priority Date Filing Date
CNB031042406A Expired - Lifetime CN100511658C (zh) 2002-02-07 2003-02-08 半导体元件及其制造方法,和半导体器件及其制造方法
CNA2005100897126A Pending CN1873939A (zh) 2002-02-07 2003-02-08 半导体器件的制造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CNA2005100897126A Pending CN1873939A (zh) 2002-02-07 2003-02-08 半导体器件的制造方法

Country Status (5)

Country Link
US (4) US7135770B2 (zh)
JP (1) JP3829325B2 (zh)
KR (1) KR100545008B1 (zh)
CN (2) CN100511658C (zh)
TW (1) TWI223361B (zh)

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100399561C (zh) * 2004-06-28 2008-07-02 株式会社东芝 半导体器件及其制造方法
CN1988143B (zh) * 2005-12-20 2011-07-27 富士通半导体股份有限公司 半导体器件及其制造方法
CN102157479A (zh) * 2010-01-20 2011-08-17 台湾积体电路制造股份有限公司 半导体装置及其制造方法
CN102222642A (zh) * 2010-03-26 2011-10-19 星科金朋有限公司 具应力再分布层的集成电路系统
CN102376665A (zh) * 2010-08-25 2012-03-14 瑞鼎科技股份有限公司 半导体结构及其制造方法
CN102593068A (zh) * 2011-01-11 2012-07-18 颀邦科技股份有限公司 斜锥状凸块结构
CN102760664A (zh) * 2011-04-29 2012-10-31 英飞凌科技股份有限公司 半导体装置和制造半导体装置的方法
CN102800599A (zh) * 2011-05-25 2012-11-28 颀邦科技股份有限公司 凸块工艺及其结构
CN102867758A (zh) * 2011-07-08 2013-01-09 颀邦科技股份有限公司 凸块制造工艺及其结构
CN102915981A (zh) * 2012-11-08 2013-02-06 南通富士通微电子股份有限公司 半导体器件及其封装方法
CN101681853B (zh) * 2007-04-05 2013-02-06 丘费尔资产股份有限公司 对电连接中具有高迁移率的组分的束缚
CN103050420A (zh) * 2008-06-05 2013-04-17 丘费尔资产股份有限公司 对电连接中具有高迁移率的组分的束缚
CN103928433A (zh) * 2013-01-15 2014-07-16 矽品精密工业股份有限公司 半导体装置及其制法
CN102054810B (zh) * 2009-10-30 2015-04-29 日月光半导体制造股份有限公司 具有金属柱结构的芯片
CN105390473A (zh) * 2010-03-24 2016-03-09 台湾积体电路制造股份有限公司 集成电路装置及封装组件
CN103765566B (zh) * 2011-11-24 2016-10-19 松下知识产权经营株式会社 倒装片接合装置
CN106486444A (zh) * 2015-08-31 2017-03-08 中芯长电半导体(江阴)有限公司 凸块结构、封装组件及其形成方法
CN104064550B (zh) * 2013-03-18 2017-05-03 富士通株式会社 半导体器件及其制造方法
CN107086213A (zh) * 2013-07-19 2017-08-22 日月光半导体制造股份有限公司 封装基板、覆晶式封装及其制造方法
CN108847396A (zh) * 2018-06-14 2018-11-20 通富微电子股份有限公司 倒装方法
CN110610870A (zh) * 2018-06-14 2019-12-24 通富微电子股份有限公司 倒装方法
CN110610914A (zh) * 2018-06-14 2019-12-24 通富微电子股份有限公司 封装结构
CN110610916A (zh) * 2018-06-14 2019-12-24 通富微电子股份有限公司 封装结构
CN110610915A (zh) * 2018-06-14 2019-12-24 通富微电子股份有限公司 倒装方法

Families Citing this family (150)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642136B1 (en) 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US8021976B2 (en) 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US6815324B2 (en) 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
TWI313507B (en) * 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US6818545B2 (en) 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US7902679B2 (en) 2001-03-05 2011-03-08 Megica Corporation Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
US7099293B2 (en) 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
JP3829325B2 (ja) * 2002-02-07 2006-10-04 日本電気株式会社 半導体素子およびその製造方法並びに半導体装置の製造方法
US20050003650A1 (en) 2003-07-02 2005-01-06 Shriram Ramanathan Three-dimensional stacked substrate arrangements
US20050003652A1 (en) * 2003-07-02 2005-01-06 Shriram Ramanathan Method and apparatus for low temperature copper to copper bonding
US7394161B2 (en) 2003-12-08 2008-07-01 Megica Corporation Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
WO2005093816A1 (en) * 2004-03-05 2005-10-06 Infineon Technologies Ag Semiconductor device for radio frequency applications and method for making the same
JP4094574B2 (ja) * 2004-03-08 2008-06-04 シャープ株式会社 半導体装置及びその製造方法
US7205486B2 (en) * 2004-07-16 2007-04-17 Cardiac Pacemakers, Inc. Thermally isolated via structure
US8067837B2 (en) 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
JP2006100552A (ja) * 2004-09-29 2006-04-13 Rohm Co Ltd 配線基板および半導体装置
FR2876243B1 (fr) * 2004-10-04 2007-01-26 Commissariat Energie Atomique Composant a protuberances conductrices ductiles enterrees et procede de connexion electrique entre ce composant et un composant muni de pointes conductrices dures
JP4880218B2 (ja) * 2004-12-22 2012-02-22 三洋電機株式会社 回路装置
KR101030238B1 (ko) 2004-12-27 2011-04-22 매그나칩 반도체 유한회사 반도체 소자의 범프 형성 방법
US8294279B2 (en) 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
KR100705757B1 (ko) 2005-03-15 2007-04-10 한국과학기술원 극미세피치를 가지는 플립칩 및 이의 제조방법
US7786592B2 (en) 2005-06-14 2010-08-31 John Trezza Chip capacitive coupling
US7838997B2 (en) 2005-06-14 2010-11-23 John Trezza Remote chip attachment
US7969015B2 (en) 2005-06-14 2011-06-28 Cufer Asset Ltd. L.L.C. Inverse chip connector
US7767493B2 (en) 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US7781886B2 (en) * 2005-06-14 2010-08-24 John Trezza Electronic chip contact structure
DE112006001506T5 (de) * 2005-06-16 2008-04-30 Imbera Electronics Oy Platinenstruktur und Verfahren zu ihrer Herstellung
JP4305430B2 (ja) * 2005-08-24 2009-07-29 ソニー株式会社 部品実装方法および部品実装体
JP2007059652A (ja) * 2005-08-25 2007-03-08 Matsushita Electric Ind Co Ltd 電子部品実装方法
US20070045833A1 (en) * 2005-08-25 2007-03-01 Ting Zhong Copper bump barrier cap to reduce electrical resistance
JP4971769B2 (ja) * 2005-12-22 2012-07-11 新光電気工業株式会社 フリップチップ実装構造及びフリップチップ実装構造の製造方法
KR100772920B1 (ko) * 2006-02-20 2007-11-02 주식회사 네패스 솔더 범프가 형성된 반도체 칩 및 제조 방법
TWI296839B (en) * 2006-03-15 2008-05-11 Advanced Semiconductor Eng A package structure with enhancing layer and manufaturing the same
JP5437553B2 (ja) 2006-03-30 2014-03-12 日本電気株式会社 半導体素子及び半導体装置
US8097958B2 (en) * 2006-04-27 2012-01-17 Panasonic Corporation Flip chip connection structure having powder-like conductive substance and method of producing the same
US7435624B2 (en) * 2006-04-28 2008-10-14 Sandisk Corporation Method of reducing mechanical stress on a semiconductor die during fabrication
US8878346B2 (en) * 2006-04-28 2014-11-04 Sandisk Technologies Inc. Molded SiP package with reinforced solder columns
JP5162851B2 (ja) * 2006-07-14 2013-03-13 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US7652374B2 (en) * 2006-07-31 2010-01-26 Chi Wah Kok Substrate and process for semiconductor flip chip package
JP2008047732A (ja) * 2006-08-17 2008-02-28 Sony Corp 半導体装置及びその製造方法
US8193034B2 (en) 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
US8174119B2 (en) * 2006-11-10 2012-05-08 Stats Chippac, Ltd. Semiconductor package with embedded die
JP2008192833A (ja) * 2007-02-05 2008-08-21 Shinko Electric Ind Co Ltd 半導体装置の製造方法
KR100857365B1 (ko) * 2007-02-28 2008-09-05 주식회사 네패스 반도체 장치의 범프 구조물
US7919859B2 (en) * 2007-03-23 2011-04-05 Intel Corporation Copper die bumps with electromigration cap and plated solder
US9084377B2 (en) * 2007-03-30 2015-07-14 Stats Chippac Ltd. Integrated circuit package system with mounting features for clearance
EP1978559A3 (en) * 2007-04-06 2013-08-28 Hitachi, Ltd. Semiconductor device
KR100850212B1 (ko) * 2007-04-20 2008-08-04 삼성전자주식회사 균일한 무전해 도금 두께를 얻을 수 있는 반도체 소자의제조방법
US20090057909A1 (en) * 2007-06-20 2009-03-05 Flipchip International, Llc Under bump metallization structure having a seed layer for electroless nickel deposition
TWI378544B (en) * 2007-07-19 2012-12-01 Unimicron Technology Corp Package substrate with electrically connecting structure
US8779300B2 (en) * 2007-07-19 2014-07-15 Unimicron Technology Corp. Packaging substrate with conductive structure
WO2009028538A1 (ja) * 2007-08-27 2009-03-05 Nec Corporation 半導体素子及びその製造方法
KR20090059504A (ko) * 2007-12-06 2009-06-11 삼성전자주식회사 반도체 장치 및 그 제조방법들
US7800239B2 (en) * 2007-12-14 2010-09-21 Semiconductor Components Industries, Llc Thick metal interconnect with metal pad caps at selective sites and process for making the same
US8304909B2 (en) * 2007-12-19 2012-11-06 Intel Corporation IC solder reflow method and materials
JP5228479B2 (ja) * 2007-12-28 2013-07-03 富士通株式会社 電子装置の製造方法
US20090246911A1 (en) * 2008-03-27 2009-10-01 Ibiden, Co., Ltd. Substrate for mounting electronic components and its method of manufacture
US8344522B2 (en) * 2008-03-31 2013-01-01 Sanyo Electric Co., Ltd. Solder structure, method for forming the solder structure, and semiconductor module including the solder structure
WO2009122867A1 (ja) * 2008-03-31 2009-10-08 日本電気株式会社 半導体装置、複合回路装置及びそれらの製造方法
US8497578B2 (en) * 2008-05-14 2013-07-30 PAC Tech—Packaging Technologies GmbH Terminal face contact structure and method of making same
US7855137B2 (en) * 2008-08-12 2010-12-21 International Business Machines Corporation Method of making a sidewall-protected metallic pillar on a semiconductor substrate
DE102008042107A1 (de) * 2008-09-15 2010-03-18 Robert Bosch Gmbh Elektronisches Bauteil sowie Verfahren zu seiner Herstellung
JP4360446B1 (ja) * 2008-10-16 2009-11-11 住友ベークライト株式会社 半導体装置の製造方法及び半導体装置
US7982311B2 (en) * 2008-12-19 2011-07-19 Intel Corporation Solder limiting layer for integrated circuit die copper bumps
DE102008063401A1 (de) * 2008-12-31 2010-07-08 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit einem kosteneffizienten Chipgehäuse, das auf der Grundlage von Metallsäuren angeschlossen ist
JP2010161136A (ja) * 2009-01-07 2010-07-22 Panasonic Corp 半導体装置及びその製造方法
TWI394253B (zh) * 2009-03-25 2013-04-21 Advanced Semiconductor Eng 具有凸塊之晶片及具有凸塊之晶片之封裝結構
US8536458B1 (en) 2009-03-30 2013-09-17 Amkor Technology, Inc. Fine pitch copper pillar package and method
US20100300743A1 (en) * 2009-06-02 2010-12-02 Qualcomm Incorporated Modified Pillar Design for Improved Flip Chip Packaging
US8709870B2 (en) 2009-08-06 2014-04-29 Maxim Integrated Products, Inc. Method of forming solderable side-surface terminals of quad no-lead frame (QFN) integrated circuit packages
US8324738B2 (en) * 2009-09-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned protection layer for copper post structure
US8093106B2 (en) 2009-09-23 2012-01-10 Chipmos Technologies Inc. Method for manufacturing packaging structure
KR20110036450A (ko) * 2009-10-01 2011-04-07 삼성전기주식회사 플립칩용 기판의 제조방법 및 이를 이용하여 제조한 플립칩용 기판
TWI445147B (zh) * 2009-10-14 2014-07-11 Advanced Semiconductor Eng 半導體元件
TW201113962A (en) * 2009-10-14 2011-04-16 Advanced Semiconductor Eng Chip having metal pillar structure
US20110186989A1 (en) 2010-02-04 2011-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Bump Formation Process
US8637392B2 (en) * 2010-02-05 2014-01-28 International Business Machines Corporation Solder interconnect with non-wettable sidewall pillars and methods of manufacture
TWI416641B (zh) * 2010-02-22 2013-11-21 Chipmos Technologies Inc 製造一半導體結構之方法
CN102194707B (zh) * 2010-03-01 2013-03-27 南茂科技股份有限公司 制造半导体结构的方法
TWI419284B (zh) * 2010-05-26 2013-12-11 Chipmos Technologies Inc 晶片之凸塊結構及凸塊結構之製造方法
US9018758B2 (en) * 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
US8823166B2 (en) 2010-08-30 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar bumps and process for making same
JP5433543B2 (ja) * 2010-09-27 2014-03-05 ローム株式会社 半導体装置
TWI478303B (zh) 2010-09-27 2015-03-21 Advanced Semiconductor Eng 具有金屬柱之晶片及具有金屬柱之晶片之封裝結構
TWI451546B (zh) 2010-10-29 2014-09-01 Advanced Semiconductor Eng 堆疊式封裝結構、其封裝結構及封裝結構之製造方法
US9202715B2 (en) * 2010-11-16 2015-12-01 Stats Chippac Ltd. Integrated circuit packaging system with connection structure and method of manufacture thereof
JP5559023B2 (ja) 2010-12-15 2014-07-23 日本特殊陶業株式会社 配線基板及びその製造方法
US8901431B2 (en) * 2010-12-16 2014-12-02 Ibiden Co., Ltd. Printed wiring board and method for manufacturing printed wiring board
JP5861133B2 (ja) * 2011-01-17 2016-02-16 株式会社アドバンストシステムズジャパン 常温低周波ボンディング装置
US8399265B2 (en) * 2011-03-14 2013-03-19 Infineon Technologies Ag Device for releasably receiving a semiconductor chip
JP5853214B2 (ja) * 2011-03-28 2016-02-09 パナソニックIpマネジメント株式会社 半導体素子の実装方法
WO2012131817A1 (ja) * 2011-03-28 2012-10-04 パナソニック株式会社 半導体素子の実装方法
JP5853213B2 (ja) * 2011-03-28 2016-02-09 パナソニックIpマネジメント株式会社 発光素子搭載基板の製造方法
KR101782503B1 (ko) * 2011-05-18 2017-09-28 삼성전자 주식회사 솔더 범프 붕괴를 억제하는 반도체 소자의 범프 형성방법
US8664760B2 (en) * 2011-05-30 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Connector design for packaging integrated circuits
US8624392B2 (en) 2011-06-03 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
JPWO2012176392A1 (ja) * 2011-06-24 2015-02-23 パナソニック株式会社 半導体装置及びその製造方法
JP6035714B2 (ja) * 2011-08-17 2016-11-30 ソニー株式会社 半導体装置、半導体装置の製造方法、及び、電子機器
US8518818B2 (en) 2011-09-16 2013-08-27 Taiwan Semiconductor Manufacturing Co., Ltd. Reverse damascene process
FR2980952A1 (fr) * 2011-10-03 2013-04-05 St Microelectronics Grenoble 2 Procede d'assemblage de deux dispositifs electroniques et structure comprenant ces dispositifs
US8912668B2 (en) 2012-03-01 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connections for chip scale packaging
US9548281B2 (en) 2011-10-07 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
KR101932665B1 (ko) 2011-10-10 2018-12-27 삼성전자 주식회사 반도체 패키지
JP5778557B2 (ja) * 2011-11-28 2015-09-16 新光電気工業株式会社 半導体装置の製造方法、半導体装置、及び半導体素子
US8912651B2 (en) * 2011-11-30 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure including stud bulbs and method
WO2013099360A1 (ja) * 2011-12-26 2013-07-04 株式会社村田製作所 モジュールおよびこれを備えるモジュール搭載部品
WO2013101243A1 (en) * 2011-12-31 2013-07-04 Intel Corporation High density package interconnects
US9257276B2 (en) 2011-12-31 2016-02-09 Intel Corporation Organic thin film passivation of metal interconnections
US9123700B2 (en) * 2012-01-06 2015-09-01 Micron Technology, Inc. Integrated circuit constructions having through substrate vias and methods of forming integrated circuit constructions having through substrate vias
CN102543766A (zh) * 2012-01-17 2012-07-04 南通富士通微电子股份有限公司 一种柱状凸点封装工艺
US20130234317A1 (en) * 2012-03-09 2013-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Packaged Semiconductor Devices
US9263412B2 (en) 2012-03-09 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and packaged semiconductor devices
US8970034B2 (en) 2012-05-09 2015-03-03 Micron Technology, Inc. Semiconductor assemblies and structures
US8884443B2 (en) 2012-07-05 2014-11-11 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing
US9196573B2 (en) 2012-07-31 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Bump on pad (BOP) bonding structure
US9673161B2 (en) 2012-08-17 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US8829673B2 (en) * 2012-08-17 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US8686568B2 (en) 2012-09-27 2014-04-01 Advanced Semiconductor Engineering, Inc. Semiconductor package substrates having layered circuit segments, and related methods
US9053990B2 (en) * 2012-10-25 2015-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. Bump interconnection techniques
KR20140100144A (ko) 2013-02-05 2014-08-14 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US8896118B2 (en) * 2013-03-13 2014-11-25 Texas Instruments Incorporated Electronic assembly with copper pillar attach substrate
JP6282454B2 (ja) * 2013-12-10 2018-02-21 新光電気工業株式会社 半導体パッケージの製造方法
JP2015173215A (ja) * 2014-03-12 2015-10-01 株式会社東芝 半導体装置及びその製造方法
US9735123B2 (en) * 2014-03-13 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure and manufacturing method
JP6373716B2 (ja) * 2014-04-21 2018-08-15 新光電気工業株式会社 配線基板及びその製造方法
US9177928B1 (en) * 2014-04-24 2015-11-03 Globalfoundries Contact and solder ball interconnect
JP2015213103A (ja) * 2014-05-01 2015-11-26 三菱電機株式会社 半導体装置およびその実装構造
CN106133660B (zh) * 2014-05-16 2019-03-22 富士胶片株式会社 触摸面板及其制造方法
WO2015198839A1 (ja) * 2014-06-27 2015-12-30 ソニー株式会社 半導体装置およびその製造方法
CN105684138B (zh) * 2014-07-29 2019-09-06 松下知识产权经营株式会社 半导体部件和半导体安装品的制造方法
JP2016048728A (ja) * 2014-08-27 2016-04-07 株式会社村田製作所 導電性ポスト、及び、導電性ポストを用いた積層基板の製造方法
JP6578900B2 (ja) 2014-12-10 2019-09-25 株式会社デンソー 半導体装置及びその製造方法
EP3037810B1 (fr) * 2014-12-23 2017-10-25 EM Microelectronic-Marin SA Capteur d'humidite ameliore
WO2016189692A1 (ja) * 2015-05-27 2016-12-01 オリンパス株式会社 基板、半導体装置、および基板の製造方法
EP3113219B1 (de) * 2015-06-30 2020-03-11 SEMIKRON Elektronik GmbH & Co. KG Halbleiterbauelement und verfahren zu dessen herstellung
FR3041625B1 (fr) * 2015-09-29 2021-07-30 Tronics Microsystems Dispositif de fixation de deux elements tels qu'une puce, un interposeur et un support
US9875979B2 (en) 2015-11-16 2018-01-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive external connector structure and method of forming
KR102624624B1 (ko) * 2016-06-15 2024-01-12 삼성디스플레이 주식회사 집적 회로 및 그 제조 방법
US10297563B2 (en) * 2016-09-15 2019-05-21 Intel Corporation Copper seed layer and nickel-tin microbump structures
KR102534735B1 (ko) 2016-09-29 2023-05-19 삼성전자 주식회사 필름형 반도체 패키지 및 그 제조 방법
US10160066B2 (en) * 2016-11-01 2018-12-25 GM Global Technology Operations LLC Methods and systems for reinforced adhesive bonding using solder elements and flux
CN109559995A (zh) * 2017-09-27 2019-04-02 东莞新科技术研究开发有限公司 金属焊点表面的刻蚀方法
KR20190036776A (ko) * 2017-09-28 2019-04-05 삼성전자주식회사 범프 구조물, 범프 구조물을 포함하는 반도체 패키지, 및 범프 구조물의 형성 방법
DE102017128457A1 (de) 2017-11-30 2019-06-06 Osram Opto Semiconductors Gmbh Herstellung optoelektronischer bauelemente
JP7430481B2 (ja) * 2018-05-31 2024-02-13 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
CN109119346B (zh) * 2018-08-16 2021-07-23 嘉盛半导体(苏州)有限公司 晶圆级芯片的封装方法及结构
JP7251951B2 (ja) * 2018-11-13 2023-04-04 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
CN109729639B (zh) * 2018-12-24 2020-11-20 奥特斯科技(重庆)有限公司 在无芯基板上包括柱体的部件承载件

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5380438A (en) 1976-12-25 1978-07-15 Sumitomo Electric Ind Ltd Manufacture of laminated bus bars
JPS6267826A (ja) 1985-09-20 1987-03-27 Fujitsu Ltd 半導体装置の製造方法
JP2781560B2 (ja) 1988-01-22 1998-07-30 日本電気株式会社 半導体装置及びその製造方法
JPH02253626A (ja) 1989-03-27 1990-10-12 Shimadzu Corp 半導体チップの実装方法
JP2785338B2 (ja) 1989-06-19 1998-08-13 日本電気株式会社 半導体装置の製造方法
JP3189799B2 (ja) 1991-08-23 2001-07-16 ソニー株式会社 半導体装置の製造方法
JP3078646B2 (ja) 1992-05-29 2000-08-21 株式会社東芝 インジウムバンプの製造方法
US5503286A (en) * 1994-06-28 1996-04-02 International Business Machines Corporation Electroplated solder terminal
JPH08102467A (ja) 1994-09-30 1996-04-16 Tanaka Kikinzoku Kogyo Kk 導電用バンプ、導電用バンプ構造及びそれらの製造方法
US5656858A (en) * 1994-10-19 1997-08-12 Nippondenso Co., Ltd. Semiconductor device with bump structure
JP3217624B2 (ja) 1994-11-12 2001-10-09 東芝マイクロエレクトロニクス株式会社 半導体装置
US5864178A (en) * 1995-01-12 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor device with improved encapsulating resin
JPH10125685A (ja) * 1996-10-16 1998-05-15 Casio Comput Co Ltd 突起電極およびその形成方法
JP3516592B2 (ja) * 1998-08-18 2004-04-05 沖電気工業株式会社 半導体装置およびその製造方法
JP2000208547A (ja) 1998-11-12 2000-07-28 Nec Corp 半導体装置におけるバンプ補強構造およびその形成方法
KR100687548B1 (ko) * 1999-01-27 2007-02-27 신꼬오덴기 고교 가부시키가이샤 반도체 웨이퍼 제조 방법, 반도체 장치 제조 방법 및 칩 사이즈의 반도체 웨이퍼 패키지 제조 방법
JP3346320B2 (ja) * 1999-02-03 2002-11-18 カシオ計算機株式会社 半導体装置及びその製造方法
JP2000228417A (ja) 1999-02-04 2000-08-15 Sony Corp 半導体装置、電子モジュール及び電子機器、並びに半導体装置の製造方法
JP2000299339A (ja) 1999-04-14 2000-10-24 Shinko Electric Ind Co Ltd 半導体装置の製造方法
JP2000315706A (ja) 1999-04-28 2000-11-14 Shinko Electric Ind Co Ltd 回路基板の製造方法並びに回路基板
JP2000323510A (ja) 1999-05-11 2000-11-24 Shinko Electric Ind Co Ltd 柱状電極付き半導体ウエハ及びその製造方法並びに半導体装置
JP4526651B2 (ja) * 1999-08-12 2010-08-18 富士通セミコンダクター株式会社 半導体装置
JP3223283B2 (ja) * 1999-09-14 2001-10-29 カシオ計算機株式会社 半導体装置の製造方法
JP2001156097A (ja) 1999-11-30 2001-06-08 Hitachi Ltd 電子回路およびlsiチップ実装構造体並びに半導体装置の製造方法
JP3409759B2 (ja) * 1999-12-09 2003-05-26 カシオ計算機株式会社 半導体装置の製造方法
JP3502800B2 (ja) * 1999-12-15 2004-03-02 新光電気工業株式会社 半導体装置の製造方法
JP2001284382A (ja) 2000-03-28 2001-10-12 Nec Corp はんだバンプ形成方法、フリップチップ実装方法及び実装構造体
JP2001298342A (ja) 2000-04-12 2001-10-26 Matsushita Electric Ind Co Ltd 弾性表面波デバイスとその製造方法
JP2001319940A (ja) 2000-05-09 2001-11-16 Citizen Watch Co Ltd 半導体装置とその製造方法
JP2001338947A (ja) 2000-05-26 2001-12-07 Nec Corp フリップチップ型半導体装置及びその製造方法
SG99939A1 (en) * 2000-08-11 2003-11-27 Casio Computer Co Ltd Semiconductor device
US6596618B1 (en) * 2000-12-08 2003-07-22 Altera Corporation Increased solder-bump height for improved flip-chip bonding and reliability
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
JP3767398B2 (ja) * 2001-03-19 2006-04-19 カシオ計算機株式会社 半導体装置およびその製造方法
JP3939504B2 (ja) * 2001-04-17 2007-07-04 カシオ計算機株式会社 半導体装置並びにその製造方法および実装構造
US6683375B2 (en) * 2001-06-15 2004-01-27 Fairchild Semiconductor Corporation Semiconductor die including conductive columns
KR100426897B1 (ko) * 2001-08-21 2004-04-30 주식회사 네패스 솔더 터미널 및 그 제조방법
US6567588B2 (en) * 2001-08-28 2003-05-20 Photronics, Inc. Method for fabricating chirped fiber bragg gratings
US6541366B1 (en) * 2002-01-08 2003-04-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method for improving a solder bump adhesion bond to a UBM contact layer
US6974659B2 (en) * 2002-01-16 2005-12-13 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a solder ball using a thermally stable resinous protective layer
JP3829325B2 (ja) * 2002-02-07 2006-10-04 日本電気株式会社 半導体素子およびその製造方法並びに半導体装置の製造方法
JP4126389B2 (ja) * 2002-09-20 2008-07-30 カシオ計算機株式会社 半導体パッケージの製造方法

Cited By (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100399561C (zh) * 2004-06-28 2008-07-02 株式会社东芝 半导体器件及其制造方法
CN1988143B (zh) * 2005-12-20 2011-07-27 富士通半导体股份有限公司 半导体器件及其制造方法
US8420522B2 (en) 2005-12-20 2013-04-16 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method of the same
CN101681853B (zh) * 2007-04-05 2013-02-06 丘费尔资产股份有限公司 对电连接中具有高迁移率的组分的束缚
CN103050420A (zh) * 2008-06-05 2013-04-17 丘费尔资产股份有限公司 对电连接中具有高迁移率的组分的束缚
CN102054810B (zh) * 2009-10-30 2015-04-29 日月光半导体制造股份有限公司 具有金属柱结构的芯片
CN102157479A (zh) * 2010-01-20 2011-08-17 台湾积体电路制造股份有限公司 半导体装置及其制造方法
US8659170B2 (en) 2010-01-20 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having conductive pads and a method of manufacturing the same
US9129818B2 (en) 2010-01-20 2015-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having conductive pads and a method of manufacturing the same
CN105390473B (zh) * 2010-03-24 2018-12-14 台湾积体电路制造股份有限公司 集成电路装置及封装组件
CN105390473A (zh) * 2010-03-24 2016-03-09 台湾积体电路制造股份有限公司 集成电路装置及封装组件
US11257714B2 (en) 2010-03-24 2022-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a pillar structure having a non-metal sidewall protection structure and integrated circuit including the same
CN102222642A (zh) * 2010-03-26 2011-10-19 星科金朋有限公司 具应力再分布层的集成电路系统
CN102376665A (zh) * 2010-08-25 2012-03-14 瑞鼎科技股份有限公司 半导体结构及其制造方法
CN102593068B (zh) * 2011-01-11 2015-08-19 颀邦科技股份有限公司 斜锥状凸块结构
CN102593068A (zh) * 2011-01-11 2012-07-18 颀邦科技股份有限公司 斜锥状凸块结构
CN102760664A (zh) * 2011-04-29 2012-10-31 英飞凌科技股份有限公司 半导体装置和制造半导体装置的方法
CN102800599A (zh) * 2011-05-25 2012-11-28 颀邦科技股份有限公司 凸块工艺及其结构
CN102800599B (zh) * 2011-05-25 2015-03-25 颀邦科技股份有限公司 凸块工艺及其结构
CN102867758A (zh) * 2011-07-08 2013-01-09 颀邦科技股份有限公司 凸块制造工艺及其结构
CN103765566B (zh) * 2011-11-24 2016-10-19 松下知识产权经营株式会社 倒装片接合装置
CN102915981A (zh) * 2012-11-08 2013-02-06 南通富士通微电子股份有限公司 半导体器件及其封装方法
CN102915981B (zh) * 2012-11-08 2016-02-03 南通富士通微电子股份有限公司 半导体器件及其封装方法
CN103928433A (zh) * 2013-01-15 2014-07-16 矽品精密工业股份有限公司 半导体装置及其制法
TWI483351B (zh) * 2013-01-15 2015-05-01 矽品精密工業股份有限公司 半導體裝置及其製法
CN104064550B (zh) * 2013-03-18 2017-05-03 富士通株式会社 半导体器件及其制造方法
CN107086213A (zh) * 2013-07-19 2017-08-22 日月光半导体制造股份有限公司 封装基板、覆晶式封装及其制造方法
CN106486444B (zh) * 2015-08-31 2019-10-01 中芯长电半导体(江阴)有限公司 凸块结构、封装组件及其形成方法
CN106486444A (zh) * 2015-08-31 2017-03-08 中芯长电半导体(江阴)有限公司 凸块结构、封装组件及其形成方法
CN108847396A (zh) * 2018-06-14 2018-11-20 通富微电子股份有限公司 倒装方法
CN110610870A (zh) * 2018-06-14 2019-12-24 通富微电子股份有限公司 倒装方法
CN110610914A (zh) * 2018-06-14 2019-12-24 通富微电子股份有限公司 封装结构
CN110610916A (zh) * 2018-06-14 2019-12-24 通富微电子股份有限公司 封装结构
CN110610915A (zh) * 2018-06-14 2019-12-24 通富微电子股份有限公司 倒装方法
CN108847396B (zh) * 2018-06-14 2021-04-27 通富微电子股份有限公司 倒装方法
CN110610916B (zh) * 2018-06-14 2021-12-24 通富微电子股份有限公司 封装结构
CN110610915B (zh) * 2018-06-14 2022-01-25 通富微电子股份有限公司 倒装方法

Also Published As

Publication number Publication date
CN1873939A (zh) 2006-12-06
US7749888B2 (en) 2010-07-06
US20030151140A1 (en) 2003-08-14
US20060065978A1 (en) 2006-03-30
US7268438B2 (en) 2007-09-11
TWI223361B (en) 2004-11-01
US7135770B2 (en) 2006-11-14
CN100511658C (zh) 2009-07-08
US20070020912A1 (en) 2007-01-25
US7449406B2 (en) 2008-11-11
JP2003234367A (ja) 2003-08-22
KR100545008B1 (ko) 2006-01-24
JP3829325B2 (ja) 2006-10-04
KR20030067590A (ko) 2003-08-14
US20090035893A1 (en) 2009-02-05
TW200303058A (en) 2003-08-16

Similar Documents

Publication Publication Date Title
CN1437256A (zh) 半导体元件及其制造方法,和半导体器件及其制造方法
CN1294635C (zh) 凸起的形成方法、半导体器件的制造方法
CN1237595C (zh) 具有树脂部件作为加固件的焊料球的形成
CN1220250C (zh) 半导体器件的制造方法
CN1295783C (zh) 电子装置
CN1216419C (zh) 布线基板、具有布线基板的半导体装置及其制造和安装方法
CN1110063C (zh) 用于装配电子部件的带有焊接合金的衬底
CN1182573C (zh) 一种制备连接结构的方法
CN1210792C (zh) 半导体器件及其制造方法
CN1076998C (zh) 软钎料及使用该软钎料的电子器件
CN1443625A (zh) 焊料
CN1311547C (zh) 半导体器件及其制造方法、电路基板和电子装置
CN1227721C (zh) 电子部件和半导体装置、其制造方法和装配方法、电路基板与电子设备
CN1697148A (zh) 半导体器件及制造该半导体器件的方法
CN101049057A (zh) 多层印刷电路板及多层印刷电路板的制造方法
CN1244139C (zh) 半导体器件和半导体组件
CN1482956A (zh) 焊锡箔、半导体器件及电子器件
CN1949500A (zh) 配线板、半导体器件及制造配线板和半导体器件的方法
CN1625805A (zh) 半导体芯片安装用基板及其制造方法和半导体模块
CN1893051A (zh) 半导体器件
CN1836325A (zh) 用于封装集成电路器件的方法和设备
CN1825578A (zh) 半导体器件及其制造方法
CN101076884A (zh) 半导体器件及其制造方法、线路板及其制造方法、半导体封装件和电子装置
CN1750244A (zh) 线路板、其制造方法以及半导体器件
CN1677657A (zh) 半导体器件及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: INTELLECTUAL PROPERTY BRIDGE NO. 1 CO., LTD.

Free format text: FORMER OWNER: NEC CORP.

Effective date: 20150311

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20150311

Address after: Tokyo, Japan

Patentee after: GODO KAISHA IP BRIDGE 1

Address before: Tokyo, Japan

Patentee before: NEC Corp.

CX01 Expiry of patent term

Granted publication date: 20090708

CX01 Expiry of patent term