CN1453841A - 改进的存储器封装 - Google Patents

改进的存储器封装 Download PDF

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Publication number
CN1453841A
CN1453841A CN03108381A CN03108381A CN1453841A CN 1453841 A CN1453841 A CN 1453841A CN 03108381 A CN03108381 A CN 03108381A CN 03108381 A CN03108381 A CN 03108381A CN 1453841 A CN1453841 A CN 1453841A
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China
Prior art keywords
memory
circuit board
package
small pieces
controller circuitry
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Granted
Application number
CN03108381A
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CN100342508C (zh
Inventor
罗伯特·F·沃雷斯
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Creative Memory Systems Inc
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SanDisk Corp
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    • G—PHYSICS
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    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G06K19/07747—Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
    • G—PHYSICS
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Abstract

一种存储器芯片封装，该存储器芯片封装在印制电路板的一面具有控制器，并且在电路板的另一面具有存储器。存储器芯片封装被集成到微处理器控制设备中，或者可选地，被集成到便携存储器卡中。

Description

改进的存储器封装
技术领域
本发明涉及半导体存储器芯片封装，尤其涉及堆叠的多个存储器芯片封装。
背景技术
由于印制电路板(PCB)的尺寸限制，只有有限数量的封装芯片可以被放到PCB上。随着应用复杂度的增加，PCB上需要大量芯片以实现必要的功能，这需要大尺寸的PCB。然而还期望降低PCB和包含PCB的设备的尺寸。一个达到这两个目的的方法是提高封装中的芯片数量，例如通过堆叠芯片，这种方式不会增加封装的平面面积。堆叠芯片可以使总体封装占用面积较小。然而，直接在彼此上面堆叠芯片的方式具有其自身的缺点。当芯片被堆叠在基芯片上时，基芯片会在加工过程中受到损伤。会出现许多不同类型的损伤，其中包含对引线的损伤。此外，虽然可以减少占用面积，然而堆叠芯片增加了高度或纵横比。
发明内容
因此，需要能够解决这些问题的半导体芯片封装和封装方法。本发明的一个方面是存储器封装，该存储器封装在印制电路板的一面具有控制器电路小片(die)，并且在其另一面具有存储器电路小片。另一个方面涉及将存储器封装集成到具有可选附加存储器的存储器卡中。另一个方面是集成存储器封装的微处理器控制设备，所述存储器封装在印制电路板的一面具有控制器电路小片，并且在另一面具有存储器电路小片。
附图说明
图1是制造之前的多个芯片封装的透视图。
图2a-2c是芯片封装100在制程的各个阶段的剖视图。
图3是芯片封装300的剖视图。
图4是芯片封装400的剖视图。
图5是诸如芯片封装100、300或400的芯片封装的示意图。
图6是集成诸如芯片封装100、300或400的芯片封装的设备的示意图。
图7a是通过本发明另一个实施例的存储器芯片封装构成的存储器卡500的第一面的顶视图。
图7b是图7a示出的存储器卡500的第二面的顶视图。
图7c是图7a和7b示出的存储器卡500的剖视图。
图7d是图7a和7b示出的存储器卡500的剖视图。
图7e是图7a和7b示出的存储器卡500的剖视图。
图8是通过本发明另一个实施例的存储器芯片封装构成的存储器卡600的顶视图。
具体实施方式
包含控制器的存储器芯片封装可用于许多不同的应用。在所有应用中，空间是宝贵的，并且长期可靠性是必要的。封装可以被集成到诸如蜂窝电话的复杂嵌入式系统或任何微处理器控制的设备中，并且封装也可以被用来制造存储器卡。本发明的存储器封装通常包括存储器电路小片和控制器电路小片，控制器电路小片用于组织与外部设备的通信，并且控制针对存储器电路小片的存储器位置的数据读取和写入。于是，控制器简化了存储器单元的数据读取和写入，使得集成封装的设备只需通过简单命令与控制器通信，并且不需通过复杂得多的信号直接访问存储器单元。以后会参照图5和6更详细地讨论控制器电路小片和存储器电路小片的功能。
每个电路小片的存储器容量正在迅速增加。一个电路小片可以具有从几千字节到几兆字节的容量。某些嵌入式应用可能不需要高容量，而数字音频和图象的存储器需要尽可能高的密度。本发明的封装可以被配置成适于许多不同应用的许多不同容量。存储器可以是只读存储器(ROM)、随机访问存储器(RAM)或快闪型RAM。当前，单个闪速存储器电路小片的最大容量大约为64兆字节。在本申请提出时，总体封装尺寸为13×17mm并且厚度小于1mm的电路小片估计会容纳256兆字节的快闪存储器。
在存储器电路小片上面背载控制器电路小片的方法是已知的。然而这种布局会导致损坏所述电路小片中的一个或全部。在印制电路板的相对侧装配存储器电路小片避免了这种潜在的损伤，于是减少了测试之后必须废弃的封装的数量，并且提高了那些通过最初的测试考验(burn)但在产品的生命周期内可能出现故障的封装的长期可靠性。
图1图解了形成存储器封装组的初始步骤。在组件被锯切(saw cut)成单个封装之前，2个印制电路板110和112被层叠在一起。可以锯切或剪切出单个封装。在图1中标记出这样的2个封装100a和100b。各个PCB内具有若干导电层，所述导电层被用来连接PCB上安装的各个部件，以构成许多电路。印制电路板(PCB)112具有一组在其内部形成的矩形或正方形孔118。可以通过任何方式在PCB 112中机械加工出这些孔，也可以在PCB 112中预先形成这些孔。
图2a-2c图解了制造期间单个封装100，例如图1的100a或100b的各个阶段的剖视图。如图2a所示，控制器电路小片120被安装到PCB 110上，并且位于PCB 112的矩形孔内。可选地，一个PCB可被用来取代2个PCB 110和112。在这种情况下，PCB 110的厚度会近似等于PCB 110和112的厚度，并且在PCB 110内形成用于控制器的中央凹座。可以通过诸如研磨的工艺机械加工出这种中央凹座，也可以通过有选择地层叠具有预先形成的剪切部分的层来形成中央凹座。
图2b示出了穿过PCB 110和PCB 112以连接封装100的上侧和底侧上的部件的通孔128。焊接线124将控制器电路小片120连接到通孔128。在形成焊接线之后，使用密封层132封装控制器电路小片120。密封层132可以是任何本领域众所周知的物质，例如合成树脂、苯酚、环氧或热定形复合物。
在图2c中，存储器电路小片144被安装到PCB 110的顶侧。焊接线148连接存储器电路小片144的焊盘和通孔128，其中一些通孔128被拘连(intern connected)到焊球156。焊球156被连接到通孔128，以便以后将封装100装配到另一个电路板上。接着使用任何众所周知的材料封装存储器电路小片144和焊接线148，以形成密封层152。由于密封层152是从电路板切割出的多个封装中的一个，所以密封层152具有平坦上表面和正方形边缘。然而，可以单独形成封装，在这种情况下密封层152会逐渐缩减到封装100边缘附近的PCB 110。存储器封装100的厚度在没有焊球156的情况下大约为0.7mm，在有焊球156的情况下略微小于1mm。PCB 110的电路走线(circuit traces)可以通过附加通孔和焊接线(未示出)将存储器电路小片144连接到控制器电路小片120，或者可以连接到存储器电路小片144和控制器电路小片120的相对侧或电路板侧的齐平式(flush mount)接点。
作为在单独步骤中封装上侧和底侧(存储器电路小片144和控制器电路小片120)的方式的替代方式，可以在安装电路小片之后同时转模(transfer mold)整个封装。
图3图解了根据本发明第二实施例的存储器封装的剖视图。存储器封装300类似于如上所述的存储器封装100，不同之处在于，存储器电路小片144是接合到PCB 110的上面的倒装片，于是省去了将存储器电路小片连接到电路板的焊接线，从而与封装100相比，减少了封装300的高度。存储器电路小片144的焊盘或端子通过通孔和PCB 110和112的导电层被导电连接到控制器电路小片120。图中封装300在PCB 110和存储器电路小片144的上侧没有任何密封层，然而可以涂敷密封层。
图4图解了根据本发明第三实施例的存储器封装的剖视图。存储器封装400类似于存储器封装300，但是存储器电路小片144和控制器电路小片120均是接合到PCB 110的倒装片。于是，PCB 110的导电层被用来互连控制器电路小片120和存储器电路小片144。由于不存在焊接线，封装400具有极低的纵横比，这对于今天的便携设备而言是一个非常重要的特性。
图5是迄今为止描述的任何芯片封装，例如芯片封装100的控制器电路小片120和存储器电路小片144的电气示意图。存储器控制器100包含与计算机系统总线15接口的适当系统接口电路43，控制器微处理器45，暂时存储针对存储器写入或读取的数据的易失缓冲存储器47，和控制逻辑电路49。这些电路单元被互连并且受微处理器45的控制。存储器电路小片144内的EEPROM组通过包含数据线51、地址线53和控制和状态线55的电路被连接到控制器逻辑49。有关图5图解的系统的详细资料可以参见授权给Lofgren等人、标题为″Wear LevelingTechniques for Flash EEPROM Systems″的美国专利6,081,447，和授权给Sandisk公司、标题为″Flash EEPROM System with SimultaneousMultiple Data Sector Programming and Storage of Physical BlockCharacteristics in Other Designated Blocks″的PCT专利WO 01/61703A2，这里完整地参考引用了上述两个专利。授权给Wallace等人、标题为″Computer Memory Cards Using Flash EEPROM IntegratedCircuit Chips and Memory-Controller Systems″的美国专利5,663,901更详细地描述了控制器的功能，这里完整参考引用了该专利。
存储器电路小片144中的EEPROM单元可以具有″或非″或″与非″结构。有关″与非″结构和构造的进一步信息，请参见授权给Takeuchi等人、标题为″Semiconductor Device and Memory System″的美国专利6,046,935，这里完整参考引用了该专利。
根据是使用″与非″结构还是使用″或非″结构，行和列的阵列会不同，并且数据线51、地址线53和控制和状态线55会具有不同构造。然而通常情况下，会通过数据线51传送针对具体存储器单元读取或写入的数据。会通过地址线53传送那些具体存储器单元的地址，并且通过控制和状态线55传送具体地址的单元的状态。例如，通过控制和状态线55可以检查写入(编程)操作之后的存储器单元的状态。这些线路51、53、和55对应于图2a-c中图解的芯片封装100的焊接线124和通孔128，或者对应于图3和4中图解的倒装片封装300和400的焊接线124、通孔128和电路走线130。系统接口电路包含焊球156和焊接线144，并且也可以包含其它焊接线和互连。
任何如上所述的存储器封装均可以作为部件被集成到任何类型的需要薄存储器封装的设备64中。图6示出了可以集成本发明的存储器芯片封装的典型嵌入式应用的示意图。例如，图中通过电气总线将存储器芯片封装100连接到输入-输出设备60，RAM存储器62和微处理器64。设备64可以是任何智能设备，例如个人计算机、便携管理器或音乐播放器、蜂窝电话或任何其他需要存储数据的存储器的设备。
封装也可以被使用在存储器卡中。图7a图解了通过存储器封装510和PCB 505上安装的可选无源器件520构成的存储器卡500的第一面。PCB 505是多层电路板，并且在PCB 505的导电层(未示出)中形成电路走线，以便将存储器封装510和任何其他电子部件互连到接点525。例如，无源器件是电荷泵浦电容器，该电荷泵浦电容器被用来将供电电压转换成修改存储器封装510的快闪存储器，或任何其他可以集成到卡500中的存储器所需的较大电压。如果无源器件520被集成到存储器封装510中，则它们不能作为存储器卡500的单独部件存在。如果是这样，存储器封装510会包含存储器卡500中除了电路走线之外的所有电路部件，其中一部分可以被用作测试接点，和图7b示出的存储器卡500的背面的接点525。图7c是存储器卡500的剖视图，其中示出了PCB 505上的存储器封装510和无源器件520。图7d是图解塑料盖535的剖视图，塑料盖535在具有封装510和可选无源器件520的存储器卡的面和边上延伸。图7e图解了存储器卡500的实施例，其中盖子535延伸到存储器卡的所有周边。在这种情况下，盖子535包含剪切部分或空隙，在剪切部分或空隙中接点525位于PCB 505的背面。
有关存储器卡和封装的进一步信息，参见Robert F.Wallace于2000年3月21日提交、标题为″Semiconductor Package Using TerminalsFormed on a Conductive Layer of a Circuit Board″的美国专利6,040,622，这里完整参考引用了该专利。
图8图解了存储器卡600的第一面，存储器卡600包括安装到电路板上的存储器封装510和附加存储器电路小片530。存储器电路小片530可以是任何类型的存储器，并且为存储器卡600提供附加的存储容量。存储器封装510中出现的控制器会被用来访问附加存储器电路小片530中的信息。
虽然前面示出和描述了本发明的具体实施例及其优点，然而应当理解，在不偏离本发明如所附权利要求书限定的宗旨和范围的前提下，可以进行各个改变、替换和变化。

Claims (31)

1.一种存储器封装，包括：
具有2个面的第一电路板，第一电路板包括电路板的第一面上的存储器电路小片和第二面上的控制器电路小片；
具有2个面和开口的第二电路板，第二电路板的第一面与第一电路板的第二面附着在一起，使得控制器电路小片位于开口内；和
通孔，所述通孔将存储器电路小片连接到第二电路板的第二面，并且将存储器电路小片连接到控制器电路小片。
2.如权利要求1所述的存储器封装，还包括第二电路板的第二面上的焊球，焊球附着到通孔。
3.如权利要求1所述的存储器封装，还包括覆盖存储器电路小片和一部分第一电路板的第一密封层。
4.如权利要求1所述的存储器封装，还包括覆盖控制器电路小片的第二密封层。
5.如权利要求1所述的存储器封装，其中封装的厚度大约为0.7毫米。
6.如权利要求2所述的存储器封装，其中包含焊球的封装的厚度大约为1.0毫米。
7.如权利要求1所述的存储器封装，还包括焊接线，焊接线将存储器电路小片和控制器电路小片连接到通孔，或第一电路板的连接到通孔的导电层。
8.如权利要求1所述的存储器封装，其中在不使用焊接线的情况下将存储器电路小片导电附着到第一电路板的导电层。
9.如权利要求1所述的存储器封装，其中在不使用焊接线的情况下将控制器电路小片导电附着到第一电路板的导电层。
10.如权利要求1所述的存储器封装，其中存储器是快闪型存储器。
11.如权利要求1所述的存储器封装，还包括第一或第二电路板上的一组接点，所述接点组被暴露出来。
12.一种存储器封装，包括：
电路板，具有第一和第二面，第二面具有凹座；
附着到电路板的第一面的存储器电路小片，存储器电路小片位于凹座上方；
附着到电路板的第二面的凹座并且位于该凹座内的控制器电路小片，电路板的第二面构成封装的第二面；和
通孔，将存储器电路小片连接到电路板的第二面。
13.如权利要求12所述的存储器封装，还包括焊接线，焊接线将存储器电路小片和控制器电路小片连接到通孔，或电路板的连接到通孔的导电层。
14.如权利要求12所述的存储器封装，其中在不使用焊接线的情况下将存储器电路小片导电附着到电路板的导电层。
15.如权利要求12所述的存储器封装，其中在不使用焊接线的情况下将控制器电路小片导电附着到电路板的导电层。
16.如权利要求12所述的存储器封装，其中存储器是快闪型存储器。
17.如权利要求12所述的存储器封装，还包括位于电路板的面上的一组接点。
18.如权利要求17所述的存储器封装，其中接点位于电路板的第二面上。
19.如权利要求17所述的存储器封装，还包括位于封装的第一面和边缘周围的密封层。
20.如权利要求18所述的存储器封装，还包括覆盖封装的第一、第二面和边缘的塑料盖。
21.制造存储器封装的方法，包括：
将多个存储器电路小片附接到第一电路板的第一面；
将多个控制器电路小片附接到第一电路板的第二面，各个控制器电路小片位于存储器电路小片的下方；
将第一电路板的第二面层叠到具有多个凹座的第二电路板的第一面，使得多个控制器电路小片安装在多个凹座内；
在第一和第二电路板中构成通孔，通孔将存储器电路小片下方的控制器电路小片连接到存储器电路小片，以构成多个存储器封装；和
在多个存储器封装之间切割第一和第二电路板，以构成单个存储器封装。
22.一种存储器卡，包括：
具有第一和第二面的第一电路板；
存储器封装，包括第二电路板，附着到第二电路板的第一面的控制器电路小片，和附着到第二电路板的第二面的存储器电路小片，其中存储器封装被附着于第一电路板的第一面；和
一组接点，位于第一电路板的第二面上。
23.如权利要求22所述的存储器卡，还包括第一电路板内的一组电路走线，被连接到存储器电路小片、控制器电路小片和接点组。
24.如权利要求23所述的存储器卡，其中电路走线通过通孔被连接到存储器电路小片、控制器电路小片和接点组。
25.如权利要求22所述的存储器卡，还包括在电路板的第一面和边缘延伸的盖子。
26.如权利要求25所述的存储器卡，其中盖子还在电路板的第二面上延伸，盖子具有针对接点组的开口。
27.微处理器控制的设备，包括：
存储器芯片封装，包括具有第一和第二面的第一电路板，附着到第一面的控制器电路小片和附着到第二面的存储器电路小片；
一或多个输入-输出设备；
随机访问存储器；和
微处理器。
28.一种存储器芯片封装，包括：
具有第一和第二相对面的电路板；
具有存储器单元的快闪EEPROM，EEPROM附着到电路板的第一面；
具有控制逻辑的控制器，控制器附着到电路板的第二面，并且被构造成针对第一面上的存储器单元读写数据；和
数据线，将控制器电路小片连接到EEPROM，并且可以针对存储器单元传送数据。
29.如权利要求28所述的存储器芯片封装，其中控制器还包括：
微处理器；
存储器缓冲区；和
系统接口。
30.如权利要求28所述的存储器芯片封装，还包括：
将第一面上的存储器单元连接到第二面上的控制器的地址线，地址线可以寻址一或多个存储器单元以便读取和写入数据。
31.如权利要求30所述的存储器芯片封装，还包括：
将第一面上的存储器单元连接到第二面上的控制器的控制和状态线，控制和状态线可以监视控制和状态线上的存储器单元的状态。
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US6639309B2 (en) 2003-10-28

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