CN1463043A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN1463043A
CN1463043A CN03138174A CN03138174A CN1463043A CN 1463043 A CN1463043 A CN 1463043A CN 03138174 A CN03138174 A CN 03138174A CN 03138174 A CN03138174 A CN 03138174A CN 1463043 A CN1463043 A CN 1463043A
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China
Prior art keywords
semiconductor element
semiconductor device
resin bed
semiconductor
substrate
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CN03138174A
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CN100435334C (zh
Inventor
藤沢哲也
松木浩久
井川治
爱场喜孝
生云雅光
佐藤光孝
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Socionext Inc
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Fujitsu Ltd
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Priority claimed from JP2002316076A external-priority patent/JP4408015B2/ja
Priority claimed from JP2003127344A external-priority patent/JP3938759B2/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of CN1463043A publication Critical patent/CN1463043A/zh
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Publication of CN100435334C publication Critical patent/CN100435334C/zh
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Abstract

本申请公开了一种半导体器件及其制造方法。在该半导体器件中，当半导体芯片并列地排列时，多个半导体芯片的每一个的电路形成面可以容易地置于齐平的平面上，由此简化了形成重排布线的工艺。半导体芯片借助粘结剂层以两维布局安装在基板上。树脂层形成在基板上并位于半导体元件周围，树脂层的厚度基本上与半导体元件的厚度相同。有机绝缘层形成在树脂层表面以及半导体元件的电路形成面上。重排布线层形成在有机绝缘层以及半导体芯片的电极上。外部连接端子通过重排布线层中的布线电连接到半导体元件的电路形成面。

Description

半导体器件及其制造方法
对相关申请的引用
本发明要求日本专利申请No.2002-158997(申请日2002年5月31日)、No.2002-316076(申请日2002年10月30日)和No.2003-127344(申请日2003年5月2日)的优先权，其全部内容在此引为参考。
技术领域
本发明总体上涉及半导体器件，特别涉及构成为可表面安装的半导体器件及其制造方法。
背景技术
近些年来，高密度的半导体芯片进步非常显著，半导体芯片的尺寸已减小。与此相关，高密度和功能高度集中的半导体器件不断进步，现已开发了将多个半导体芯片集成到一个半导体器件内的技术。例如，存在一种其中有多个不同种类和功能的半导体芯片相互连接并且提供外部连接电极的半导体器件。
虽然例如有一种在一个封装中容纳多个半导体芯片的多芯片组件(MCM)，但常规的MCM不具有与具有最近开发的精细结构的半导体芯片相同的精细结构。
日本特许公开申请No.2001-217381公开了在一个封装中容纳多个半导体芯片的技术。采用该专利文件中公开的技术，多个半导体芯片设置在安装夹具上，铜端子形成在每个半导体芯片的电极上。然后，使用传递模塑通过密封树脂密封半导体芯片和铜端子，研磨密封树脂的表面以露出铜端子。在露出铜端子的密封树脂表面上形成布线(重排布线)之后，外部连接电极形成在重排布线(rearrangement wiring)上。
日本特许公开申请No.2001-332643公开了一种类似于以上提到的专利文件中公开的技术。该专利文件公开了在每个半导体芯片的背面上形成保护膜。
此外，日本特许公开申请No.7-86502公开了一种技术，其中多个半导体芯片容纳在基板内形成的凹槽中并且重排布线形成在半导体芯片上，之后外部连接端形成在重排布线上。采用该技术，凹槽的深度形成得使每个半导体芯片的电路形成面与基板的表面对准。
此外，日本特许公开申请No.2002-110714公开了一种技术，其中设置多个半导体芯片，电路形成面朝下，树脂填充在半导体芯片之间，同时通过覆盖半导体芯片的背面和侧面使半导体芯片的电路形成面成为平坦的表面。之后，重排布线形成在电路形成面的侧面上，以形成外部连接端子。
此外，日本特许公开申请No.5-206368公开了一种技术，其中多个半导体芯片安装在导热基板上，绝缘树脂填充在芯片之间，用铝在电路形成面上形成重排布线。
虽然以上提到的常规技术以并列安装多个半导体芯片的方式构成，但现已开发了许多种其中叠置多个半导体芯片的叠置型半导体器件。
作为公开了叠置型半导体器件的文件的例子，有日本特许公开申请No.2001-298149和No.2001-320015。
采用日本特许公开申请No.2001-298149中公开的技术，上半导体芯片安装在其上叠置上半导体芯片的下半导体芯片的焊盘区域(排列在周边的电极)内。此外，采用日本特许公开申请No.2001-320015中公开的技术，导电柱(柱形金属部件)设置在每个叠置半导体芯片的布线层上。
采用以上提到的日本特许公开申请No.2001-217381和No.2001-332643中公开的技术，使用传递模塑通过密封树脂密封半导体芯片，由此，传递模塑期间施加的压力对半导体芯片具有负面影响。此外，模塑之后研磨密封树脂表面时，较大的力施加在半导体芯片上。此外，当叠置半导体芯片时，由于在安装基板(硅晶片)上固化密封树脂时的收缩而可能发生翘曲。当叠置半导体芯片时，这种翘曲会具有负面影响。
在公开专利申请No.7-86502中，当形成容纳半导体芯片的凹槽时，凹槽的深度需要高精确度。特别是，如果半导体芯片变薄，那么凹槽的深度需要较高的精确度，这很难实现。
此外，采用日本特许公开申请N0.2002-110714中公开的技术，树脂提供在半导体芯片的背面，产生半导体芯片散热特性差的问题。此外，由于树脂固化在半导体芯片的背面上，因此在半导体器件中可能发生翘曲。
此外，根据日本特许公开申请No.2002-110714和No.5-206368中公开的技术，将半导体芯片设置在预定位置之后，树脂填充在半导体芯片之间，由此存在安装半导体芯片或填充树脂时，半导体芯片发生位移的情况。采用该技术，不可能除去位移的芯片。
此外，对于叠置型半导体器件，在日本特许公开申请No.2001-298149中公开的技术中，上半导体芯片安装在其上叠置上半导体芯片的下半导体芯片的焊盘区域(排列在周边的电极)内，不能叠置具有相同尺寸的半导体芯片。此外，采用日本特许公开申请No.2001-320015中公开的技术，由于形成导电柱，半导体器件的制造成本增加。
同时，通过叠置半导体芯片形成的半导体器件通常通过覆盖半导体芯片的周边将半导体芯片牢固地固定到基板上。此外，在多个半导体芯片安装在基板例如多芯片组件上的情况中，如日本特许公开申请No.2002-110714所公开的，树脂填充在半导体芯片之间。采用这种填充的树脂层，每个半导体芯片可以牢固地固定到基板，半导体芯片相互绝缘。
可以在将半导体芯片安装到基板上之前预先形成填充的树脂层，或者将半导体芯片安装到基板上之后填充树脂。
当安装半导体芯片之前形成以上提到的填充树脂层时，除去形成在基板上的部分填充树脂层，以形成露出基板表面的开口，通过将半导体芯片放置在开口内而安装该芯片。因此，形成的开口具有稍大于半导体芯片外形的尺寸。
此外，有一种在安装半导体芯片之后形成填充树脂层的方法，其中树脂施加到基板上之后固化，在基板上安装和掩蔽有半导体芯片。同样在这种情况中，很难使填充的树脂层与半导体芯片的侧面紧密接触，间隙会形成在填充的树脂层和半导体芯片的侧面之间。
如果在填充的树脂层和半导体芯片的侧面之间形成有间隙，那么通过填充的树脂层不能获得对半导体芯片的充分固定效果。此外，这种间隙会妨碍在半导体芯片和树脂填充层上形成布线。当绝缘树脂层形成在半导体芯片和树脂填充层上时，绝缘树脂进入间隙，在形成绝缘树脂层的步骤中间隙被绝缘树脂填充。然而，绝缘树脂没有填充整个间隙。
发明内容
本发明的一般目的是提供一种改进和有效的半导体器件，其中消除了以上提到的问题。
本发明的更具体的目的是提供一种半导体器件及其制造方法，其中即使半导体芯片并列地排列，多个半导体芯片的每一个的电路形成面可以容易地定位于平坦的面(even level)上，由此简化了形成重排布线的工艺。
本发明的另一目的是提供一种半导体器件及其制造方法，其中可以容易地叠置具有相同尺寸的半导体芯片，同时在其间形成薄布线层。
本发明的又一目的是提供一种半导体器件及其制造方法，其中填充树脂层紧密地接触半导体芯片的侧面。
为了实现以上提到的目的，根据本发明的一个方案提供一种半导体器件，包括：多个半导体元件，以两维布局借助粘结剂层安装在基板上；形成在基板上并位于所述半导体元件周围的树脂层，树脂层的厚度基本上与半导体元件的厚度相同；形成在树脂层表面以及半导体元件的电路形成面上的有机绝缘层；形成在有机绝缘层以及半导体芯片的电极上的重排布线层；以及通过重排布线层中的布线电连接到半导体元件的电路形成面的外部连接端子。
根据本发明的另一方案，提供一种封装多个半导体元件的半导体器件的制造方法，包括以下步骤：形成厚度与要安装的半导体元件的厚度相同的树脂层；通过部分除去树脂层在树脂层中形成开口；分别在开口中放置半导体元件，电路形成面朝上；在树脂层的表面和半导体元件的电路形成面上形成有机绝缘层；在有机绝缘层以及半导体元件的电极上形成重排布线层；以及在重排布线层上形成外部连接端子，外部连接端子通过重排布线层中的布线连接到半导体元件的电极。
根据以上提到的发明，由于半导体元件周围的树脂层的厚度基本上等于半导体元件的厚度，因此半导体元件的电路形成面和树脂层的表面基本上位于同一平面中(基本上在相同的水平上)。由此，重排布线层能容易地形成在半导体元件上。
此外，根据本发明的又一方案，提供一种叠置半导体器件，包括多个相互叠置的层结构，每个层结构包括：借助粘结剂层排列在基板上的半导体元件；形成在基板上以及半导体元件周围的树脂层，树脂层的厚度基本上等于半导体元件的厚度；形成在树脂层表面以及半导体元件的电路形成面上的有机绝缘层；以及形成在半导体元件及半导体元件电极上的重排布线层。
此外，根据本发明的再一方案，提供一种叠置半导体器件的制造方法，包括以下步骤：在基板上形成第一树脂层，第一树脂层的厚度基本上等于要安装的第一半导体元件的厚度，第一树脂层环绕第一半导体元件；在第一树脂层中形成第一开口，以便第一半导体元件置于第一开口中；将第一半导体元件置于第一开口中；在第一树脂层的表面上以及第一半导体元件的电路形成面上形成第一有机绝缘层；在第一有机绝缘层和第一半导体元件的电极上形成第一重排布线层；在第一重排布线层上形成第二树脂层，第二树脂层的厚度基本上与要安装的第二半导体元件的厚度相同，第二树脂层环绕第二半导体元件；在第二树脂层中形成第二开口，以便第二半导体元件置于第二开口中；将第二半导体元件置于第二开口中；在第二树脂层的表面以及第二半导体元件的电路形成面上形成第二有机绝缘层；在第二有机绝缘层上形成第二重排布线层；通过形成延伸穿过第一重排布线层和第二重排布线层之间的第二树脂层的导电连接部分，将第一重排布线层电连接到第二重排布线层。
根据以上提到的发明，由于环绕半导体元件的树脂层的厚度基本上等于半导体元件的厚度，因此半导体元件的电路形成面与树脂层的表面基本上位于同一平面中(基本上在同一水平)。由此，重排布线层能容易地形成在半导体元件上。此外，由于重排布线层延伸到树脂层的表面，因此通过如通路的导电连接部分比如通孔可以容易地实现重排布线层之间的电连接。
此外，根据本发明的另一方案提供一种半导体器件，包括：基板；安装在基板上的半导体元件；以及提供在半导体元件周围并具有与半导体元件的上表面基本上处于相同水平面的上表面的树脂层，其中该树脂层为可半固化的树脂，具有在半固化状态加热时变软并流体化的特性，该树脂层与半导体元件的侧表面紧密接触，两者之间没有间隙。
此外，根据本发明的又一方案提供一种半导体器件的制造方法，包括以下步骤：在基板上形成半固化状态的树脂层，使半导体元件位于该树脂层中，该树脂层由可半固化的树脂制成；通过加热使半固化状态的填充树脂层(filing resin layer)流体化；通过在间隙中填充流体化的填充树脂层，消除半导体元件和填充树脂层之间的间隙；以及通过加热完全固化该树脂层。
根据以上提到的发明，通过使用可半固化的树脂作为所述树脂层的材料，通过软化和流体化的树脂层可以填充半导体元件和所述树脂层之间的间隙。由此，可以容易地制造在半导体元件和树脂层之间没有间隙的半导体器件。
此外，根据本发明的再一方案提供一种半导体器件的制造方法，包括以下步骤：在基板上形成具有开口的树脂层并制备带有可半固化的树脂形成的粘结剂的半导体元件；将半导体元件置于所述开口中；在通过加热使半固化状态的粘结剂流体化的同时，隔着粘结剂将半导体元件按压到基板上；在将半导体元件保持在半导体元件的上表面与填充树脂层的上表面基本上处于相同平面的位置的同时通过加热固化粘结剂。
此外，根据本发明的还一方案提供一种半导体器件的制造方法，包括以下步骤：在基板上形成具有开口的树脂层并制备带有粘结剂的半导体元件；通过用焊头(bonding tool)的下表面支撑半导体元件的上表面，将半导体元件置于开口中；在焊头的下表面接触该树脂层上表面的状态下固化粘结剂。
根据以上提到的发明，通过粘结剂可以填充半导体元件和所述树脂层之间的间隙，半导体元件的上表面与填充树脂层的上表面可以精确地设置在基本上同一平面中。此外，由于施加了适量的粘结剂，粘结剂被半导体元件按压而填充间隙。由此，粘结剂紧密接触基板，并且可以防止粘结剂的不充分润湿或上爬现象。
结合附图阅读下面的详细说明时，本发明的其它目的、特点和优点将变得更清楚。
附图简介
图1为根据本发明第一实施例的半导体器件的剖面图；
图2示出了一个半导体器件的剖面图，为图1所示半导体器件的变型；
图3示出了一个半导体器件的剖面图，为图1所示半导体器件的另一变型；
图4示出了具有虚芯片的半导体器件的剖面图；
图5示出了虚芯片和相邻半导体芯片的平面图；
图6示出了具有形成在重排布线层中的电容器的半导体器件的部分剖面图；
图7A示出了具有形成在重排布线层中的电感器的半导体器件的剖面图；
图7B示出了图7A所示电感器的平面图；
图8示出了具有形成在树脂层中的电容器的半导体器件的部分剖面图；
图9示出了具有形成在基板和半导体芯片之间的电容器的半导体器件的部分剖面图；
图10示出了半导体芯片的安装工艺。
图11为表示具有不同厚度的半导体芯片的安装工艺的半导体器件剖面图；
图12示出了具有用于定位半导体芯片的对准图形(alignmentpattern)的半导体芯片的剖面图；
图13示出了形成在基板上具有用于识别切割线的对准图形的半导体器件的剖面图；
图14示出了根据本发明的第二实施例的半导体器件的剖面图；
图15示出了一个半导体器件的剖面图，为图14所示半导体器件的变型；
图16示出了一个半导体器件的剖面图，为图14所示半导体器件的另一变型；
图17示出了根据本发明的第三实施例的半导体器件的剖面图；
图18是将图1所示的半导体器件封装起来的半导体器件的剖面图；
图19A示出了根据本发明的第四实施例在制造过程的中间的半导体器件的剖面图；
图19B为图19A所示的半导体器件在通过使树脂层流体化而填充了间隙的状态下的剖面图；
图20A和20B示出了用于说明填充树脂层的形成的一个例子的剖面图；
图21A和21B示出了用于说明填充树脂层的形成的另一个例子的剖面图；
图22示出了说明填充树脂层和半导体元件厚度之间关系的剖面图；
图23A到23D示出了根据本发明的第五实施例的半导体器件的制造工艺的剖面图；
图24示出了根据本发明第六实施例的半导体器件的剖面图；
图25A和25B示出了根据本发明的第七实施例的半导体器件的制造工艺的剖面图；
图26A到26C示出了将粘结剂施加到半导体元件上并将粘结剂设置在半固化状态的工艺；
图27A和27B示出了用于说明将树脂层的上表面和半导体元件的上表面设置到基本上同一平面中的方法的剖面图。
优选实施例的详细说明
下面介绍本发明的第一实施例
图1示出了根据本发明的第一实施例的半导体器件10的剖面图。半导体器件10具有结构11，其中多个半导体芯片(或者半导体元件)安装在基板如硅晶片上，输入/输出端子(外部连接端子)形成在半导体芯片上的布线上。
基板11不限于硅晶片，也可以使用由具有良好导热性的材料形成，可作为散热板的基板，以促进半导体芯片的散热。
虽然安装在基板11上的半导体芯片包括图1所示例子中的逻辑芯片12和存储芯片13，但是具有各种功能的任意数量的半导体芯片可以安装在基板11上。然而，要安装的半导体芯片优选为具有50μm或更小厚度的薄半导体芯片。
逻辑芯片12和存储芯片13(下文简称为半导体芯片12和13)通过粘结剂层15安装在基板11上，同时位于树脂层14中。这里，在本实施例中，通过将逻辑芯片12和存储芯片13置于形成树脂层之后在树脂层14中形成的开口中，将逻辑芯片12和存储芯片13安装在树脂层14中。
即，粘结剂层15首先形成在基板11上，然后，树脂层14形成在粘结剂层15上。树脂层14形成的厚度与要安装的半导体芯片12和13的厚度相同。树脂层14由光敏树脂形成，使用光蚀刻技术形成容纳半导体芯片12和13的开口14a。开口14a具有穿透树脂层14的深度，在开口14a的下面露出粘结剂层15的表面。此外，每个开口14a的尺寸形成得正好适合半导体芯片12和13的每一个。
半导体芯片12和13设置在树脂层14中如此形成的开口14a中，同时电路形成面朝上。半导体芯片12和13置于开口14a中之后，半导体芯片12和13的背面粘结到粘结剂层15上，使半导体芯片12和13固定到开口14a中。在此状态下，半导体芯片12和13的电路形成面处于与树脂层14的表面对准的状态。即，半导体芯片12和13的电路形成面与树脂层14的表面齐平。
在本实施例中，每个半导体芯片12和13的厚度设置为50μm或更小。虽然半导体芯片的厚度通常含有约10％的容许公差，但由于50μm的10％仅为5μm，这种不平整度(即平面度)不会影响在随后的工艺中形成重排布线层。因此，在本发明中，重要的是使要安装的半导体芯片较薄。
安装半导体芯片12和13之后，在齐平的电路形成面和树脂层14表面上，形成有机绝缘膜16如聚酰亚胺或环氧树脂，重排布线层17形成于其上。通过交替叠置导电层和绝缘层并通过通孔等连接导电层，形成重排布线层17，重排布线层也可以使用本领域中公知的技术形成，因此省略了介绍。
由此，通过用重排布线层17连接逻辑芯片12和存储芯片13，构成了具有完整功能的半导体器件，使得，例如，逻辑芯片12能够使用存储芯片13的数据进行计算，结果存储在存储芯片13中。在重排布线层17表面上形成输入/输出端子18作为外部连接端子之后，就完成了图1所示的半导体器件。
在根据本实施例的半导体器件10中，由于薄半导体器件设置在与半导体芯片厚度相同的树脂层14中，因此不需要进行单独的使电路形成面和树脂层表面取平的工艺，仅将半导体芯片12和13置于树脂层14的开口14a中就可以获得形成重排布线层17所需要的平坦度。
此外，由于通过光蚀刻处理树脂层14以形成开口14a，因此可以高精确度地控制开口的位置和尺寸。因此可以以足够的精度设置半导体芯片12和13。此外，由于在安装半导体芯片12和13之前形成树脂14层，因此在安装之后，半导体芯片12和13的位置不会由于固化树脂时树脂的收缩而偏移。
当在作为根据本实施例的半导体器件10的基板10的硅晶片上形成多个半导体器件10时，半导体器件形成在硅晶片上之后，通过切割硅晶片而得到单个的半导体器件10。在这种情况下，切割带(dicingtape)作用于硅晶片的背面，从硅晶片的正面进行切割。
由此，在本实施例中，不必预先形成或除去从粘结剂层15到树脂层14的上部分中对应于切割线的部分，即划片机(dicing saw)所经过的部分，从而，所需要的仅是用划片机切割硅晶片。此外，顺序叠置在粘结剂层15上而形成的树脂层14、有机绝缘层16以及重排布线层17的每一个的边缘都位于紧邻的下一层边缘的内部(图1的半导体器件10的左边和右边台阶状地向内偏移，以便这些层不接触划片机。由此，可以进行有效的切割。
图2示出了半导体器件20的剖面图，为图1所示半导体器件10的变型。虽然半导体器件20具有与半导体器件10类似的结构，但除去了基板11和粘结剂层15，在输入/输出端子18上形成焊球21作为外部连接端子。
除去基板11时，可通过研磨变薄以及通过腐蚀等溶解基板11和粘结剂层15而有效地除去基板11。应该注意除去基板11之后，可在半导体芯片12和13的背面设置散热板。
图3示出了半导体器件30的剖面图，为图1所示半导体器件10的变型。虽然半导体器件30具有与半导体器件10类似的结构，但使用半导体芯片(LSI)31代替基板11。
也就是，在LSI31上形成绝缘层32，粘结剂层15形成在绝缘层32上。此后，与上述半导体器件10相同的方式形成。此外，半导体芯片12和13的电路形成面上的电极与LSI31的电极通过通孔33相互电连接，通孔33穿过树脂层14和粘结剂层15。
根据半导体器件30，多个半导体芯片可以较高密度安装到半导体器件上，可以获得具有较高功能的半导体器件。
在以上提到的实施例中，当半导体芯片之间的间隔较大时，半导体芯片(12和13)之间的树脂层14的长度也大。此时，由于树脂层和半导体芯片以及基板11之间的热膨胀系数不同，因此往往在半导体器件中产生应力。然后，在这种情况下，通过在半导体芯片之间较大的空间中排列虚芯片35，减少树脂层14的长度，以减轻应力。
此外，通过在虚芯片中提供布线也可以简化重排布线层17的布线结构，如图5所示。在图5所示的例子中，相邻的线36A和36B通过虚芯片35中的线35a相互交叉。
在本发明中，无源元件如电容器或电感器可以形成在重排布线层17中。图6示出了电容器形成在重排布线层17中的一个例子的剖面图。图7A示出了电容器形成在重排布线层17中的一个例子的剖面图，图7B为电容器的平面图。
如图6所示，通过在重排布线层17中的导电层之间提供介电层38可以形成电容器37。此外，如图7B所示，通过将重排布线层17中的导电层制成螺旋形可以形成电感器39。由此，通过在重排布线层17中提供电容器和电感器，可以抑制进入半导体器件内部的噪声。
此外，在本发明中，如图8所示，电容器27可以提供在树脂层14中。此时，介电部件38填充在树脂层14中形成的开口内，导电层40形成在重排布线层17的每一侧上。
此外，如图9所示，电容器也可以形成在基板11与半导体芯片12和13之间。此时，绝缘层首先形成在基板11上，导电层41形成在绝缘层40上形成电容器27的位置处。然后，介电层42形成在导电层41上，导电层41和介电层42被埋入绝缘层43内。接下来，导电层44形成在介电层42上，导电层44被埋入绝缘层45内。由此，介电层42夹在导电层41和导电层44之间，形成了电容器27。此后，粘结剂层45形成在绝缘层45上，与以上提到的半导体器件10相同的方式安装半导体芯片12和13，形成重排布线层17。
下面参考图10介绍半导体芯片12和13的安装工艺。图10示出了半导体芯片12和13的安装工艺。
首先，粘结剂层15形成在例如硅晶片的基板11上。粘结剂层15由树脂形成，它的表面上具有粘附性。接下来，树脂层14形成在粘结剂层15上。树脂层14由光敏树脂形成，并形成在粘结剂层15的几乎整个表面上。然而，如上所述，将树脂层14形成得使它的边缘位于设置在其下的粘结剂层的边缘内。此外，设置树脂层的厚度，使之基本上等于半导体芯片的厚度。
此后，通过光蚀刻树脂层14在树脂层中形成开口14a。然后，在开口14a中排列半导体芯片12和13。由此，半导体芯片12和13安装在基板11上，同时半导体芯片12和13的电路形成面与树脂层14的表面处于相同水平面。
这里，当半导体芯片12和半导体芯片13的厚度差异较大时，具有对应于该厚度差异的厚度的树脂层14A首先形成在基板11上，然后，粘结剂层15A施加于其上。之后，树脂层14B进一步形成在粘结剂层15A上。此后，形成在其中布置具有较大厚度的半导体芯片的开口14a，以便露出基板11，并形成在其中布置具有较小厚度的半导体芯片的开口14a，以便露出粘结剂层15A。此外，粘结剂层15B形成在布置较大厚度半导体芯片的开口14a中。由此，具有不同厚度的半导体芯片可以安装在基板11上，以便电路形成面基本上处于相同水平。
在本实施例中，需要以足够的精度将半导体芯片12和13设置在树脂层14的开口14a中。为了便于定位，如图12所示，优选形成对准图形50用于将半导体芯片定位在基板11上。
可通过溅射法在基板11上淀积形成与硅具有良好粘附性的钛(Ti)或铬(Cr)形成对准图形50。根据对准图形50确定树脂层14的开口14a的位置。然后，在基板11上安装半导体芯片12和13时，通过对准图形50的图像识别可以精确地检测开口14的位置并将半导体芯片12和13设置在检测到的位置处。
此外，如图13所示，除了用于定位半导体芯片的对准图形之外，最好形成用于切割的对准图形51。即，通过与对准图形50相同的方式沿切割线形成对准图形51，进行切割时识别对准图形51的图像，以确定切割线。此外，也可以根据对准图形51进行包括在基板11上形成的树脂层14或重排布线层17在内的每一层的定位和处理。
下面参考图14介绍本发明的第二实施例。图14示出了根据本发明第二实施例的半导体器件60的剖面图。图14所示的半导体器件60为所谓的叠置型半导体器件，在该器件中通过叠置安装有多个半导体芯片。
首先，树脂层61A形成在基板11如硅晶片上，开口形成在树脂层61A中。树脂层61A由与以上提到的第一实施例的树脂层14相同的材料形成，同样以与上述开口14a相同的方式形成开口。形成开口之后，绝缘粘结剂层62A形成在开口62A中，将半导体芯片63A布置到开口中。
在该状态中，通过绝缘的粘结剂层62A固定半导体芯片63A，半导体芯片63A的电路形成面与树脂层的表面对准61A。与以上提到的第一实施例类似，半导体芯片63A的厚度优选为50μm。接下来，有机绝缘膜(层)64A形成在半导体芯片的电路形成面以及树脂层61A的表面上，然后，导电层65A形成在有机绝缘层64A上。导电层65A作为重排布线层，形成为将半导体芯片63A的电极引到半导体芯片63A的外部。
接下来，树脂层61B形成在导电层65A和树脂层61A上。树脂层61B也由与以上提到的树脂层14相同的材料形成，并类似地形成开口。由于半导体芯片63A上的导电层65A在开口中露出，因此绝缘粘结剂层62B形成在开口中。然后，将半导体芯片63B布置到树脂层61B的开口中。通过绝缘粘结剂层62B固定半导体芯片63B，半导体芯片63B和树脂层61B几乎处于相同的水平面。
接下来，有机绝缘层64B形成在半导体芯片的电路形成面以及树脂层61B的表面中，导电层65B形成在有机绝缘层64B中。导电层65B作为重排布线层，形成为将半导体芯片63B的电极引到半导体芯片63B的外部。此外，通孔可以形成在树脂层61B中，当形成导电层65时，导电层也形成在通孔内(形成所谓的“vias”)以将导电层65B电连接到导电层65A。
与上面提到的方法类似，形成树脂层61C和绝缘粘结剂层62C，将半导体芯片63C布置到开口中，有机绝缘层64C和导电层65C形成在半导体芯片63C上，导电层65C电连接到导电层65B的预定部分。
此外，在以相同的方式形成树脂层61D和在开口中形成绝缘粘结剂层62D之后，半导体芯片63D以叠置状态安装。这里，在图14所示的例子中，半导体芯片63A、63B和63C具有相同的尺寸，半导体芯片63D小于半导体芯片63A、63B和63C。半导体芯片63A-63D的每一个的厚度优选50μm或更小。
有机绝缘层64D和导电层65D形成在半导体芯片63D上，在导电层65D上形成输入/输出端子作为外部连接端子。突点如焊球可以形成在输入/输出端子上，或者输入/输出端子可以通过接合线连接到外部电路。
在具有上述结构的半导体器件60中，半导体芯片63A-63D隔着有机绝缘层64A-64D、导电层65A-65D以及绝缘粘结剂层62A-62D叠置起来。在该结构中，不必在半导体芯片之间形成柱形导电部件比如金属导柱，半导体芯片之间的距离可以制得很小。因此，可以容易地形成具有小厚度的叠置型半导体器件。此外，由于半导体芯片上的电极通过导电层65A-65D被引到半导体芯片的外部，并且导电层通过通孔电连接，因此半导体芯片可以叠置在排列电极的区域上。也就是，具有相同尺寸的半导体芯片可以相互叠置。
虽然，在图14所示的例子中，相同尺寸的半导体芯片63A、63B和63C与较小的半导体芯片63D相互叠置，但要叠置的半导体芯片的数量不限于此，可以叠置任意数量的半导体芯片。此外，对半导体芯片的尺寸没有特别的限制，半导体芯片可以叠置，无论它们是否具有相同的尺寸或不同的尺寸。
图15示出了半导体器件70的剖面图，为图14所示半导体器件60的变型。在图15中，与图14所示相同的部分采用了相同的附图标记，省略了介绍。虽然图15所示的半导体器件70具有与半导体器件60基本相同的结构，但是基板11可以由半导体芯片71代替。
也就是，有机绝缘膜(层)72形成在半导体芯片71上，上树脂层61A形成在有机绝缘膜72上，以在其上叠置半导体芯片63A。半导体芯片71的尺寸比半导体芯片63A的尺寸大，半导体芯片63D布置在半导体芯片71的电极排列区域内。然后，形成在半导体芯片63A上的导电层65A与半导体芯片71上的电极通过树脂层61A以及延伸穿过有机绝缘膜72的通孔电连接。
如上所述，根据图15所示的半导体器件70，可以比半导体器件60更高密度地安装半导体芯片。
图16示出了半导体器件80的剖面图，为图14所示半导体器件60的变型。在图16中，虽然半导体器件80具有与半导体器件60基本相同的结构，但不同之处在于半导体芯片63B以面朝下的状态连接到半导体芯片63A。根据半导体器件80，可以省略重排布线层中的一层，此外可以安装相同尺寸的芯片。
下面结合图17说明本发明第三实施例的半导体器件。图17是本发明第三实施例的剖面图。示于图17中的半导体器件80是一个所谓的叠层型半导体器件，其中叠置安装了多个半导体芯片，其中，较下层的半导体芯片81A和81B并排安装在基板11上，上层的半导体芯片82叠置在半导体芯片81A和81B上。
也就是，在该半导体器件中，类似于图10所示的半导体器件10，半导体芯片81A和81B通过粘结剂层15安装到基板11上，并围绕半导体芯片81A和81B提供基于苯酚酚醛树脂(phenol novolac)的树脂层14。在半导体器件81A和81B的电路形成面和树脂层14的上表面上提供基于苯酚酚醛树脂(phenol lovolac)的有机绝缘膜(有机绝缘层)83。在有机绝缘膜83上形成一个导电层84，该导电层形成连接到半导体芯片81A和81B的图案线路(pattern wirings)。
所述半导体芯片82通过粘结剂层85安装到所述导电层和有机绝缘膜上，围绕该半导体芯片82提供基于苯酚酚醛树脂(phenolnovolak)的树脂层86。然后，在半导体芯片82的电路形成面和所述树脂层86的上表面上提供基于苯酚酚醛树脂的有机绝缘层87，在该有机绝缘层87上形成一个重排布线层17。该重排布线层17和所述导电层84通过延伸穿过树脂层86的通孔88电连接。此外，可如图2所示在形成在重排布线层17上的输入/输出端子18上形成焊球，以形成球栅阵列(BGA)型半导体器件。尽管在本实施例中使用的是基于苯酚酚醛树脂的树脂和有机绝缘膜，但本发明不限于使用基于苯酚酚醛树脂的材料，也可以使用例如基于环氧树脂或者聚酰亚胺的材料。
应注意，根据上述第一到第三实施例之一的半导体装置可以视为一个半导体芯片以结合到一个封装组件中。图18是通过将类似于图1所示半导体器件10的结构结合到一个封装组件中而形成的半导体器件90的剖面图。
在图18中，半导体器件110的输入/输出端子18安排在半导体器件110的上表面的周边。该半导体器件110通过粘结剂层15安装在一个基板91上，该半导体器件110的输入端子18和基板91的端子(图中未示出)由焊线92电连接起来。半导体器件110和焊线92由密封树脂92密封在基板91上。在基板91的背侧提供焊球作为外部连接端子。
在上述第一到第三实施例中，形成在半导体芯片的电路形成面上的绝缘层是有机绝缘膜16、64A-64D、72、83、87。使用有机绝缘膜而不使用无机绝缘膜的好处如下：
1)有机绝缘层的表面容易平坦化。
如果在电路形成面上形成无机绝缘层，由于无机绝缘层是用气相淀积方法形成的，绝缘膜各向同性生长，图案线路的存在而导致的不平坦就反映到无机绝缘层的表面中。因此，使用无机绝缘层难以获得平坦表面。另一方面，由于有机绝缘层不是通过在电路形成面上进行材料生长形成的，因此容易形成具有平坦表面的有机绝缘层。
2)可减少工序数目。
无机绝缘膜的形成需要进行蚀刻工艺以进行构图。如果使用光敏有机绝缘膜，利用光刻法进行构图，则可以省略这样的蚀刻工艺。
3)有机绝缘膜具有应力松弛功能。
由于无机绝缘膜通常是脆性的，如果用无机绝缘膜形成叠置型半导体器件，不能获得应力松弛效应。相反，有机绝缘膜一般具有某种程度的挠性，因而，在有机绝缘膜夹在半导体芯片之间的状态下，有机绝缘膜提供了应力松弛的效应。
下面描述将半导体芯片的高度设置得与环绕该半导体芯片的树脂层的高度基本相同的具体方法。
下面参考图19A和19B介绍本发明的第四实施例。
图19A和19B示出了根据本发明第四实施例的半导体器件的制造工艺。图19A的剖面图示出了制造过程的中间状态，其中在树脂层和半导体元件之间形成有间隙。图19B示出了通过流体化所述树脂层而填充了间隙的半导体器件的剖面图。
如图19B所示，根据本发明第三实施例的半导体器件具有半导体元件102安装在基板101上的结构。半导体元件102通过粘结剂103固定到基板101。树脂层104形成在半导体元件102周围。树脂层104紧密接触半导体元件102的侧面，两者之间没有形成间隙。
在形成了树脂层104并且半导体元件102安装到了基板101上的状态中，如图19A所示，在树脂层104和半导体元件102的侧面之间形成有间隙。为了填充间隙，在本实施例中，所谓的B阶段树脂(B-stage resin)用做形成树脂层104的树脂。B阶段树脂通常为环氧树脂，树脂的固化可以停止在从流体化的树脂状态到完全固化状态的过程中间。B阶段树脂称做可半固化的树脂，在过程中间固化停止的状态称做半固化状态。半固化状态的固化率约50％。
虽然B阶段树脂为半固化状态的固态，但通过加热可以变软并显示出流动性。即，B阶段树脂具有通过在半固化状态加热而变软并增加流动性的特性。此外，在半固化状态加热以增加流动性并进一步加热之后，通过进一步加热可以完全固化B阶段树脂。
在本实施例中，以上提到的B阶段树脂用做形成树脂层104的材料。在处于半固化状态的树脂层104形成在基板101上并且半导体元件102安装在基板101的状态中(图19A所示状态)，通过加热并流体化树脂层104，树脂层104流入半导体元件102的侧面102a和树脂层104之间的间隙内，由此填充间隙，如图19B所示。然后，通过进一步加热树脂层104完全固化树脂层104。因此，树脂层104紧密接触半导体元件102的侧面，从侧面支撑半导体元件102，并使半导体元件102的固定更可靠。
这里，如图20A和20B所示，树脂层104安装在基板101上后，树脂层104可以形成半固化状态，或者如图所示树脂层104预先以半固化状态形成在基板101上，通过将半导体元件102置入开口104a中将半导体元件102安装在基板101上，如图21A和21B所示。此外，可以使用公知的印刷方法将半固化状态的填充树脂层104转移到基板101上。
虽然通过加热可以增加半固化状态的树脂层104的流动性，但是树脂层104不会象液体一样自由地流动。由此，如果间隙(G)的宽度增加得大于半导体元件102的厚度(芯片厚度Tc)，即使流体化树脂层104，间隙也不会被完全填充。为了流体化半固化状态的树脂层104以完全消除半导体元件102之间的间隙，如图22所示，半导体元件102的厚度(芯片厚度Tc)最好大于间隙(G)的宽度，即Tc＞G。
对于形成树脂层104的B阶段树脂，在半固化状态出现流动性的温度(软化温度)优选为60℃或更高。这是由于如果软化温度低于60℃，那么存在树脂层104在室温或制造工艺期间的温度下流动的可能性。
考虑到提供在基板之间以固定半导体元件102的粘结剂103的厚度并且为了使完全固化之后树脂层104的高度与半导体元件102的高度基本上处于相同水平面，半固化状态的树脂层104的厚度优选比半导体元件102的厚度大5μm到20μm。
虽然在以上提到的实施例中B阶段环氧树脂用做树脂层104，但是如果显示出相同的特性，也可以使用例如酚醛清漆树脂(novolakresin)或酚树脂(phenol resin)等。
下面参考图23A到23D介绍根据本发明第四实施例的半导体器件。图23A到23D示出了根据本发明第五实施例的半导体器件的制造工艺的剖面图。在根据本发明第五实施例的半导体器件中，树脂层104的上表面104b和半导体元件102的上表面102b基本处于相同平面。
首先，类似于以上提到的第三实施例，半固化状态的树脂层104形成在基板101上，半导体元件102安装在基板101上。这里，在随后工艺中使用的通孔104c形成在半固化状态的树脂层104中。接下来，如图23A所示，光敏膜105涂覆在树脂层104和半导体元件102上。在本实施例中，为了在树脂层104中形成通孔104c，在形成有通孔104c的部分中树脂层104最好不流动。由此，如图23B所示，覆盖通孔104c的光敏膜105的一部分曝光并被除去。即，使不需要流体化的那部分树脂层104不被光敏膜105覆盖。
然后，加热半固化状态的树脂层104以使之流体化，如图21C所示。因此，被光敏膜105覆盖的间隙被流体化的树脂层104填充，消除了间隙。另一方面，没有被光敏膜105覆盖的那部分通孔104c中，树脂层104几乎不流动，通孔104c，比如如图14所示连接导电层65B和65C的通孔，没有被封闭。即，通过用带或膜覆盖树脂层104可以促进树脂层104的流体化。
此后，如图23D所示，树脂层104完全固化，通过剥离除去光敏膜105。在该状态中，半导体元件102和树脂层104之间没有间隙，半导体元件102的上表面102b和树脂层104的上表面104b处于相同的平面中。此外，在半固化状态的树脂层104中形成的通孔104c保持不变。
应该指出通过实验现已发现填充树脂层104不会在没有被光敏膜105覆盖的部分中流动，该现象的具体原因还不清楚。然而，该现象可以充分地再现，能几乎没有任何问题地实现。
此外，虽然在上述实施例中使用了光敏膜105以便在与填充树脂层不必流体化的部分相应的位置(通孔104c)处产生开口，如果说不是必须，也可以使用除光敏膜之外的膜或带。例如，可以用切割带(dicing tape)覆于树脂层104上。
下面参考图24介绍本发明的第六实施例的半导体器件。图24为根据本发明的第四实施例的半导体器件的剖面图。
根据本发明的第六实施例的半导体器件为多芯片组件，具有多个半导体元件(两个半导体元件102A和102B显示在图24中)。每个半导体元件102A和102B通过粘结剂103安装在基板101上，同时电路形成面朝上。
树脂层104提供在半导体元件102A和102B的之间和周围，树脂层104的上表面与每个半导体元件102A和102B的上表面(电路形成面)基本上位于相同的平面中。树脂层104由与以上提到的第三实施例中介绍的相同材料形成，并紧密接触每个半导体元件102A和102B的侧表面。此外，通过叠置绝缘层和导电层形成的布线层106形成在半导体元件102A和102B的电路形成面以及树脂层104的上表面上，作为外部连接端子的焊球107提供在布线层106的上表面。提供在每个半导体元件102A和102B的电路形成面上的电极通过布线层106中的布线电连接到对应的焊球107。应该指出可以使用公知的半导体制造技术形成布线层，这里省略其介绍。
半导体元件102A和102B的厚度约50μm，粘结剂3的厚度约5μm到约201μm。因此，通过使树脂层104具有501μm+(5到20)μm的厚度，半导体元件102A和102B的上表面(电路形成面)与树脂层104的上表面基本上处于相同的平面中。由于粘结剂103的厚度与半导体元件的厚度无关，因此通过将树脂层104的厚度设置为(半导体元件的厚度)+(5到20μm)，半导体元件的上表面(电路形成面)与树脂层104的上表面可以基本上处于同一平面(基本在同一水平)中。
应该指出在以上提到的实施例中，提供粘结剂以固定半导体元件102A和102B的背面，而电路形成面上不施加粘结剂。由此，粘结剂103不需要具有特别的特性，可以由与树脂层104相同的材料制成。在这种情况下，在树脂层104的流体化工艺中，粘结剂103也可以流体化，这进一步促进了粘结剂103和树脂层104的紧密接触。
下面参考图25A和25B介绍本发明的第七实施例的半导体器件。根据本发明的第七实施例的半导体器件使用具有与以上提到的第五实施例类似的半固化特性的树脂作为将半导体元件固定到基板上的粘结剂。
首先，如图25A所示，在形成在基板101上的树脂层108中形成开口108a，半导体元件102位于开口108a中。与以上提到的实施例不同，树脂层108处于完全固化状态。与以上提到的树脂层104材料相同的的粘结剂103A预先施加到半导体元件102的背面，并处于半固化状态。
接下来，焊头(bonding tool)110向下移动，同时通过加热使粘结剂103A流体化，如图23B所示。在这种环境下，粘结剂103A被半导体元件102按压并流动，进入半导体元件102和树脂层108的侧面108b之间。由于流体化的树脂层108与基板101的粘附性增加，因此半导体元件102可以粘接到基板101。然后，焊头110的向下移动停止在焊头110的下表面接触树脂层108上表面108c的位置处，在该状态中在200℃或更高温度下加热粘结剂103A以几乎完全固化(90％或更多)粘结剂103A。
根据以上提到的方法，半导体元件102和树脂层108之间的间隙可以被粘结剂103A填充，半导体元件102的上表面与树脂层108的上表面精确地位于基本上同一平面中。
此外，由于焊头110的下表面通过接触树脂层108的上表面按压树脂层108，因此可以防止半导体元件102由于粘结剂103A固化时的收缩而变形。此外，施加粘结剂103A的量为间隙可以完全被填充的量，并通过半导体元件102的按压力填充间隙，因此粘结剂103A可以紧密接触基板101，防止了粘结剂的不充分润湿或粘结剂的上爬现象。
下面参考图26A到26C介绍图25A和53B所示的将粘结剂103A施加到半导体元件102并将粘结剂设置在半固化状态的工艺。
首先，如图26A所示，电路形成在晶片109上，在晶片109上形成多个半导体元件。接下来，如图26B所示，粘结剂103A施加到晶片109的与电路形成面相反的背面，在低于100℃的温度下固化粘结剂103A，以将粘结剂设置在半固化状态。通过在低于100℃的温度下固化粘结剂103A，本实施例的方法也可以应用到使用厚度约50μm的薄晶片的半导体元件。然后，如图24C所示，晶片109被个体化(individualize)，分离成在背面具有粘结剂103A的半导体元件102。该状态对应于图23A所示焊头110支撑的半导体元件102。
应该注意，即使不是半固化状态的粘结剂，在如上所述使焊头110的下表面接触树脂层108的上表面108c的同时固化粘结剂的方法也适用。即，即使将半导体元件102固定到基板101的粘结剂不是B阶段树脂，而是常规的树脂，也可以得到半导体元件102的上表面与树脂层108的上表面108c精确地位于基本上同一平面的效果。
首先，在形成在基板101上的树脂层108中形成开口108a，将半导体元件102布置在开口108a中。树脂层108处于完全固化状态。常规的粘结剂103B预先施加到半导体元件102的背面。接下来，如图27A所示，焊头110向下移动，并停止在焊头110的下表面接触树脂层108的上表面108c的位置处。在该状态中，加热粘结剂103B以使之完全固化。当粘结剂103B固化之后，焊头110与树脂层108的上表面108c分开，如图25B所示，树脂层108的上表面108c与半导体元件102的上表面精确地位于基本上同一平面(基本上同一水平)。
本发明不限于具体公开的实施例，可以在本发明的范围内进行修改和变型。

Claims (61)

1.一种半导体器件，具有借助粘结剂层以两维布局安装在基板上的多个半导体元件，
特征在于：
形成在所述基板上并位于半导体元件周围的树脂层，树脂层的厚度与半导体元件厚度基本相同；
形成在树脂层表面以及半导体元件的电路形成面上的有机绝缘层；
形成在有机绝缘层以及所述半导体芯片的电极上的重排布线层；以及
通过重排层中的布线电连接到所述半导体元件的电路形成面的外部连接端子。
2.根据权利要求1的半导体器件，其中所述半导体元件的厚度为50μm或更小。
3.根据权利要求1的半导体器件，其中所述树脂层由光敏树脂材料形成。
4.根据权利要求1的半导体器件，其中在所述外部连接端子上形成焊球。
5.根据权利要求1的半导体器件，其中除去所述基板和所述粘结剂层，以露出所述半导体元件的背面。
6.根据权利要求1的半导体器件，其中除去所述基板和所述粘结剂层，在所述半导体芯片的背面上提供散热板。
7.根据权利要求1的半导体器件，其中所述基板由用做基板的半导体元件代替，所述多个半导体元件通过有机绝缘层安装在用做基板的所述半导体元件的电路形成面上。
8.根据权利要求1的半导体器件，其中，一虚芯片位于所述多个半导体元件的相邻半导体元件之间，虚芯片的厚度基本上与所述半导体元件的相同，并由与所述半导体元件相同的材料形成。
9.根据权利要求8的半导体器件，其中所述虚芯片其中具有布线，所述重排布线层中的部分布线连接到所述虚芯片中的布线。
10.根据权利要求1的半导体器件，其中至少一个无源元件形成在所述重排布线层中。
11.根据权利要求10的半导体器件，其中所述无源元件为电容器或电感器中的一个。
12.根据权利要求1的半导体器件，其中，一个电容器形成在所述树脂层中。
13.根据权利要求1的半导体器件，其中，一个电容器形成在所述基板和一个所述半导体芯片之间。
14.根据权利要求1的半导体器件，其中在所述基板上形成用于位置识别的对准图形。
15.根据权利要求1的半导体器件，其中所述基板通过对晶片个体化(individualize)而形成，叠置在所述基板上的每层的边缘依次从所述基板的侧表面向内偏移。
16.根据权利要求1的半导体器件，其中所述多个半导体元件包括具有不同厚度的半导体元件；具有最大厚度的一个半导体元件位于所述粘结剂层上；借助厚度对应于所述每个半导体元件与所述具有最大厚度的半导体元件之间的厚度差的树脂层，除所述具有最大厚度的半导体元件之外的每个半导体元件被安装在所述基板上。
17.一种封装多个半导体元件的半导体器件的制造方法，
特征在于以下步骤：
形成厚度等于要安装的半导体元件厚度的树脂层；
通过部分除去所述树脂层在所述树脂层中形成开口；
将半导体元件分别置于开口内，使电路形成面朝上；
在所述树脂层的表面和所述半导体元件的电路形成面上形成有机绝缘层；
在所述有机绝缘层和所述半导体元件的电极上形成重排布线层；以及
在所述重排布线层上形成外部连接端子，外部连接端子通过所述重排布线层中的布线连接到所述半导体元件的电极。
18.根据权利要求17的半导体器件的制造方法，其中所述半导体元件的厚度设置为50μm或更小。
19.根据权利要求17的半导体器件的制造方法，其中所述基板为硅晶片，多个半导体器件形成在硅晶片上，沿所述硅晶片的切割线除去部分所述硅晶片。
20.根据权利要求17的半导体器件的制造方法，其中所述树脂层由光敏树脂形成，使用光蚀刻技术形成所述开口。
21.根据权利要求17的半导体器件的制造方法，其中，形成所述重排布线层之后，通过除去所述基板露出所述半导体元件的背面。
22.根据权利要求17的半导体器件的制造方法，还包括以下步骤：
在所述基板上形成对准图形用于定位所述半导体元件；以及
根据对准图形的图像识别的结果在所述树脂层中形成所述开口，以将所述半导体元件分别置于所述开口中。
23.根据权利要求17的半导体器件的制造方法，还包括在所述重排布线层中形成至少一个无源元件的步骤。
24.根据权利要求23的半导体器件的制造方法，其中所述无源元件包括电容器或电感器中的一个。
25.根据权利要求17的半导体器件的制造方法，还包括在所述树脂层中形成电容器的步骤。
26.根据权利要求17的半导体器件的制造方法，还包括在所述基板和一个所述半导体元件之间形成电容器的步骤。
27.一种叠置半导体器件，包括多个相互叠置的层结构，每个层结构的特征在于：
借助粘结剂层布置在基板上的半导体元件；
形成在所述基板上并位于半导体元件周围的树脂层，树脂层的厚度与所述半导体元件厚度基本相同；
形成在所述树脂层表面以及所述半导体元件的电路形成面上的有机绝缘层；
形成在所述半导体元件以及所述半导体元件的电极上的重排布线层。
28.根据权利要求27的叠置半导体器件，其中所述半导体元件的厚度为50μm或更小。
29.根据权利要求27的叠置半导体器件，其中至少一个无源元件形成在所述重排布线层中。
30.根据权利要求29的叠置半导体器件，其中所述无源元件包括电容器或电感器中的一个。
31.根据权利要求27的叠置半导体器件，其中，一个电容器形成在所述树脂层中。
32.根据权利要求27的叠置半导体器件，其中，一个电容器形成在所述基板和所述半导体芯片之间。
33.根据权利要求27的叠置半导体器件，其中，在所述基板上形成用于位置识别的对准图形。
34.根据权利要求27的叠置半导体器件，其中所述基板通过对晶片个体化而形成，叠置在所述基板上的每层的边缘依次从所述基板的侧表面向内偏移。
35.根据权利要求27的叠置半导体器件，其中，所述基板由用作基板的半导体元件取代，所述用作基板的半导体元件的电路形成面上的电极通过穿过所述树脂层的导电连接部分电连接到所述重排布线层。
36.一种叠置半导体器件的制造方法，
特征在于以下步骤：
在基板上形成第一树脂层，第一树脂层的厚度基本上等于要安装的第一半导体元件的厚度，第一树脂层环绕第一半导体元件；
在所述第一树脂层中形成第一开口，以便将所述第一半导体元件置于所述第一开口中；
将所述第一半导体元件置于所述第一开口中；
在所述第一树脂层的表面上以及所述第一半导体元件的电路形成面上形成第一有机绝缘层；
在第一有机绝缘层和所述第一半导体元件的电极上形成第一重排布线层；
在所述第一重排布线层上形成第二树脂层，第二树脂层的厚度基本上与要安装的第二半导体元件的厚度相同，第二树脂层环绕第二半导体元件；
在所述第二树脂层中形成第二开口，以便将所述第二半导体元件置于所述第二开口中；
将所述第二半导体元件置于所述第二开口中；
在所述第二树脂层的表面以及所述第二半导体元件的电路形成面上形成第二有机绝缘层；
在第二有机绝缘层上形成第二重排布线层；
通过形成延伸穿过所述第一重排布线层和所述第二重排布线层之间的所述第二树脂层的导电连接部分，将所述第一重排布线层电连接到所述第二重排布线层。
37.根据权利要求36的叠置半导体器件的制造方法，还包括以下步骤：
以和所述第二半导体元件相同的方式叠置地安装任意数量的半导体元件；
以及
在最上部的重排布线层上形成外部连接电极。
38.根据权利要求36的叠置半导体器件的制造方法，其中所述基板由第三半导体元件代替，制造方法还包括以下步骤：
在电路形成面上形成有机绝缘层；
在所述绝缘层上形成所述第一树脂层；
通过延伸穿过所述第一树脂层的导电连接部分，将所述第三半导体元件的电路形成面上的电极电连接到所述第一重排布线层。
39.一种半导体器件，包括：
基板；
安装在基板上的半导体元件；以及
在半导体元件周围提供的树脂层，其上表面与半导体元件的上表面处于同一水平，
其中，所述树脂层为可半固化树脂，具有当在半固化状态下加热时变软并流体化的特性，所述树脂层与所述半导体元件的侧表面紧密接触，两者之间没有间隙。
40.根据权利要求39的半导体器件，其中形成所述半固化状态树脂层的可半固化树脂的软化点等于或大于60℃。
41.根据权利要求39的半导体器件，其中形成所述树脂层的可半固化树脂为B阶段环氧树脂。
42.根据权利要求39的半导体器件，其中通过由所述可半固化树脂形成的粘结剂将所述半导体元件固定到所述基板上。
43.根据权利要求39的半导体器件，其中所述半导体元件的厚度等于或小于50μm。
44.根据权利要求39的半导体器件，其中多个半导体元件安装在所述基板上，在半导体元件之间提供所述树脂层。
45.一种半导体器件的制造方法，特征在于以下步骤：
在基板上形成半固化状态的树脂层，以便将半导体元件设置到该树脂层中，该树脂层由可半固化树脂组成；
通过加热使半固化状态的填充树脂层流体化；
通过在间隙中填充流体化的填充树脂层，消除半导体元件和所述填充树脂层之间的间隙；以及
通过加热完全固化所述树脂层。
46.根据权利要求45的半导体器件的制造方法，其中，将所述半导体元件安装在所述基板上之后，在所述半导体元件周围形成半固化状态的所述树脂层。
47.根据权利要求45的半导体器件的制造方法，其中，在所述基板上安装所述半导体元件之前，在所述基板上形成具有用于放置所述半导体元件的开口的半固化状态的所述树脂层。
48.根据权利要求45的半导体器件的制造方法，其中，使用印刷法将半固化状态的所述树脂层转移到所述基板上。
49.根据权利要求45的半导体器件的制造方法，其中在所述基板上形成半固化状态的所述树脂层，使所述填充树脂层的侧面和所述半导体元件的侧面之间的距离小于所述半导体元件的厚度。
50.根据权利要求45的半导体器件的制造方法，其中，通过加热使半固化状态的所述树脂层流体化之前，在所述填充树脂层和所述半导体元件上覆盖一层膜。
51.根据权利要求50的半导体器件的制造方法，其中，在所述流体化步骤之前，除去所述膜的一部分，该部分对应于所述树脂层的不需要流体化的部分。
52.根据权利要求51的半导体器件的制造方法，其中所述膜是光敏膜，通过将所述膜的所述部分曝光而除去所述膜的该部分。
53.根据权利要求45的半导体器件的制造方法，其中，通过在等于或高于100℃的温度下加热使半固化状态的所述树脂层流体化。
54.根据权利要求45的半导体器件的制造方法，其中，将半固化状态的所述填充树脂层形成得使半固化状态的所述树脂层的厚度大于所述半导体元件的厚度。
55.根据权利要求45的半导体器件的制造方法，其中，所述粘结剂施加到厚度为5μm到20μm的所述半导体元件上，以通过粘结剂将所述半导体元件固定到所述基板上。
56.根据权利要求55的半导体器件的制造方法，其中，所述可半固化树脂用做所述粘结剂。
57.根据权利要求56的半导体器件的制造方法，其中，通过在等于或低于100℃的温度下加热所述粘结剂将所述粘结剂设置在半固化状态。
58.根据权利要求45的半导体器件的制造方法，其中所述半导体元件的厚度等于或小于50μm。
59.一种半导体器件的制造方法，特征在于以下步骤：
在基板上形成具有开口的树脂层，并制备带有可半固化树脂形成的粘结剂的半导体元件；
将所述半导体元件置于所述开口中；
通过加热使半固化状态的所述粘结剂流体化，并隔着所述粘结剂将所述半导体元件按压到所述基板上；
将所述半导体元件保持在使所述半导体元件的上表面与所述填充树脂层的上表面处于相同平面的位置，同时通过加热固化所述粘结剂。
60.根据权利要求59的半导体器件的制造方法，其中所述半导体元件的上表面由焊头的下表面支撑，所述粘结剂固化在使焊头的下表面接触所述树脂层上表面的状态。
61.一种半导体器件的制造方法，特征在于以下步骤：
在基板上形成具有开口的树脂层，并制备带有粘结剂的半导体元件；
通过用焊头的下表面支撑半导体元件的上表面，将所述半导体元件置于所述开口中；以及
在所述焊头的下表面接触所述填充树脂层上表面的状态下，固化所述粘结剂。
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100426496C (zh) * 2004-05-26 2008-10-15 松下电器产业株式会社 半导体器件及其制造方法
CN1949506B (zh) * 2005-10-11 2010-05-26 索尼株式会社 混合模块和其制造方法
CN101930958A (zh) * 2010-07-08 2010-12-29 日月光半导体制造股份有限公司 半导体封装件及其制造方法
CN102142405A (zh) * 2010-10-27 2011-08-03 日月光半导体制造股份有限公司 半导体封装结构及其制作方法
US8008760B2 (en) 2008-02-14 2011-08-30 Kabushiki Kaisha Toshiba Integrated semiconductor device
CN102439719A (zh) * 2009-05-14 2012-05-02 米辑电子股份有限公司 系统级封装
CN110010597A (zh) * 2019-03-29 2019-07-12 上海中航光电子有限公司 芯片封装结构及其封装方法
CN110462825A (zh) * 2017-03-29 2019-11-15 日本电产株式会社 半导体封装装置及其制造方法
CN110517964A (zh) * 2014-09-11 2019-11-29 株式会社吉帝伟士 半导体装置及其制造方法
CN112739054A (zh) * 2020-12-11 2021-04-30 昆山丘钛光电科技有限公司 一种smt元件贴片方法及电路板
CN112786460A (zh) * 2019-11-08 2021-05-11 珠海格力电器股份有限公司 芯片的封装方法及芯片封装模块

Families Citing this family (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6964881B2 (en) * 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
JP2004140037A (ja) * 2002-10-15 2004-05-13 Oki Electric Ind Co Ltd 半導体装置、及びその製造方法
DE10304777B4 (de) * 2003-02-05 2006-11-23 Infineon Technologies Ag Verfahren zur Herstellung eines Chipnutzens mittels eines Hitze- und Druckprozesses unter Verwendung eines thermoplastischen Materials und Vorrichtung zur Durchführung des Verfahrens
JP3940694B2 (ja) * 2003-04-18 2007-07-04 株式会社東芝 半導体装置及びその製造方法
US7514767B2 (en) * 2003-12-03 2009-04-07 Advanced Chip Engineering Technology Inc. Fan out type wafer level package structure and method of the same
US7459781B2 (en) * 2003-12-03 2008-12-02 Wen-Kun Yang Fan out type wafer level package structure and method of the same
US20050258533A1 (en) * 2004-05-21 2005-11-24 Matsushita Electric Industrial Co., Ltd. Semiconductor device mounting structure
JP4383274B2 (ja) * 2004-06-30 2009-12-16 Ｎｅｃエレクトロニクス株式会社 半導体装置および半導体ウエハの製造方法
JP2006019636A (ja) * 2004-07-05 2006-01-19 Renesas Technology Corp 半導体装置
TWI250596B (en) * 2004-07-23 2006-03-01 Ind Tech Res Inst Wafer-level chip scale packaging method
JP4252019B2 (ja) * 2004-09-01 2009-04-08 三洋電機株式会社 回路装置およびその製造方法
JP3976043B2 (ja) * 2004-10-25 2007-09-12 セイコーエプソン株式会社 半導体装置及びその製造方法
FI20041525A (fi) * 2004-11-26 2006-03-17 Imbera Electronics Oy Elektroniikkamoduuli ja menetelmä sen valmistamiseksi
JP4534062B2 (ja) 2005-04-19 2010-09-01 ルネサスエレクトロニクス株式会社 半導体装置
US9601474B2 (en) * 2005-07-22 2017-03-21 Invensas Corporation Electrically stackable semiconductor wafer and chip packages
US8335084B2 (en) * 2005-08-01 2012-12-18 Georgia Tech Research Corporation Embedded actives and discrete passives in a cavity within build-up layers
US20070126085A1 (en) * 2005-12-02 2007-06-07 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
US20070158804A1 (en) 2006-01-10 2007-07-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method of semiconductor device, and RFID tag
TWI308382B (en) * 2006-07-25 2009-04-01 Phoenix Prec Technology Corp Package structure having a chip embedded therein and method fabricating the same
US7598610B2 (en) * 2007-01-04 2009-10-06 Phoenix Precision Technology Corporation Plate structure having chip embedded therein and the manufacturing method of the same
JP2008198916A (ja) * 2007-02-15 2008-08-28 Spansion Llc 半導体装置及びその製造方法
US20080251908A1 (en) * 2007-04-11 2008-10-16 Advanced Chip Engineering Technology Inc. Semiconductor device package having multi-chips with side-by-side configuration and method of the same
TW200930173A (en) * 2007-12-31 2009-07-01 Phoenix Prec Technology Corp Package substrate having embedded semiconductor element and fabrication method thereof
KR101501739B1 (ko) * 2008-03-21 2015-03-11 삼성전자주식회사 반도체 패키지 제조 방법
JP4828559B2 (ja) * 2008-03-24 2011-11-30 新光電気工業株式会社 配線基板の製造方法及び電子装置の製造方法
JP5280079B2 (ja) * 2008-03-25 2013-09-04 新光電気工業株式会社 配線基板の製造方法
US8021907B2 (en) 2008-06-09 2011-09-20 Stats Chippac, Ltd. Method and apparatus for thermally enhanced semiconductor package
JP5140565B2 (ja) * 2008-11-28 2013-02-06 三洋電機株式会社 素子搭載用基板、半導体モジュール、および携帯機器
TWI501376B (zh) * 2009-10-07 2015-09-21 Xintec Inc 晶片封裝體及其製造方法
JP5401292B2 (ja) 2009-12-15 2014-01-29 ルネサスエレクトロニクス株式会社 半導体装置及び通信方法
US20110156283A1 (en) * 2009-12-28 2011-06-30 Shankar Ganapathysubramanian Use of die backside films to modulate EOL coplanarity of thin packages while providing thermal capability and laser markability of packages
US20110215465A1 (en) 2010-03-03 2011-09-08 Xilinx, Inc. Multi-chip integrated circuit
KR101088824B1 (ko) * 2010-06-16 2011-12-06 주식회사 하이닉스반도체 모듈 기판, 이를 갖는 메모리 모듈 및 메모리 모듈 형성방법
KR101140068B1 (ko) * 2010-08-23 2012-04-30 앰코 테크놀로지 코리아 주식회사 메모리 카드 및 그 제조 방법
US20120098114A1 (en) * 2010-10-21 2012-04-26 Nokia Corporation Device with mold cap and method thereof
US8624353B2 (en) 2010-12-22 2014-01-07 Stats Chippac, Ltd. Semiconductor device and method of forming integrated passive device over semiconductor die with conductive bridge and fan-out redistribution layer
US9117682B2 (en) 2011-10-11 2015-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of packaging semiconductor devices and structures thereof
JP2013214596A (ja) * 2012-04-02 2013-10-17 Sumitomo Electric Ind Ltd 半導体デバイス
US8963622B2 (en) * 2013-03-10 2015-02-24 Microchip Technology Incorporated Method and apparatus for generating regulated isolation supply voltage
US8822268B1 (en) * 2013-07-17 2014-09-02 Freescale Semiconductor, Inc. Redistributed chip packages containing multiple components and methods for the fabrication thereof
US9577025B2 (en) 2014-01-31 2017-02-21 Qualcomm Incorporated Metal-insulator-metal (MIM) capacitor in redistribution layer (RDL) of an integrated device
DE102014101366B3 (de) * 2014-02-04 2015-05-13 Infineon Technologies Ag Chip-Montage an über Chip hinausstehender Adhäsions- bzw. Dielektrikumsschicht auf Substrat
CN105280567B (zh) * 2014-06-19 2018-12-28 株式会社吉帝伟士 半导体封装件及其制造方法
KR101654433B1 (ko) 2014-12-03 2016-09-05 앰코 테크놀로지 코리아 주식회사 센서 패키지 및 그 제조 방법
JP6537815B2 (ja) * 2014-12-11 2019-07-03 株式会社ジェイデバイス 半導体パッケージ及びその製造方法
KR101665228B1 (ko) * 2015-01-16 2016-10-11 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9704836B2 (en) 2015-03-16 2017-07-11 Mediatek Inc. Semiconductor package assembly
US10217724B2 (en) * 2015-03-30 2019-02-26 Mediatek Inc. Semiconductor package assembly with embedded IPD
US9613931B2 (en) * 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
US20170040266A1 (en) 2015-05-05 2017-02-09 Mediatek Inc. Fan-out package structure including antenna
KR102431587B1 (ko) * 2015-08-12 2022-08-11 삼성전기주식회사 패키지 기판 및 그 제조방법
KR102434437B1 (ko) * 2015-09-17 2022-08-19 삼성전자주식회사 반도체 패키지
KR102473405B1 (ko) * 2015-10-30 2022-12-02 삼성전기주식회사 인쇄회로기판 및 그 제조방법
CN108780791B (zh) 2016-03-01 2023-01-10 索尼公司 半导体装置、电子模块、电子设备和用于生产半导体装置的方法
US10068853B2 (en) * 2016-05-05 2018-09-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
KR101982045B1 (ko) * 2016-08-11 2019-08-28 삼성전자주식회사 팬-아웃 반도체 패키지
KR102216172B1 (ko) 2017-07-14 2021-02-15 주식회사 엘지화학 절연층 제조방법 및 반도체 패키지 제조방법
US11901324B2 (en) 2019-03-29 2024-02-13 Shanghai Avic Opto Electronics Co., Ltd. Chip package method and chip package structure
CN110034028B (zh) * 2019-03-29 2021-04-30 上海中航光电子有限公司 芯片封装方法和芯片封装结构
US11495505B2 (en) 2019-06-03 2022-11-08 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and related methods
US11398455B2 (en) 2019-06-03 2022-07-26 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and related methods
US11189587B2 (en) * 2019-11-04 2021-11-30 Advanced Semiconductor Engineering, Inc. Semiconductor device package with organic reinforcement structure

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05206368A (ja) 1992-01-27 1993-08-13 Hitachi Ltd マルチチップモジュ−ル型半導体装置およびその製法
US5422513A (en) * 1992-10-16 1995-06-06 Martin Marietta Corporation Integrated circuit chip placement in a high density interconnect structure
JPH06260564A (ja) 1993-03-03 1994-09-16 Oki Electric Ind Co Ltd 半導体装置の製造方法
JP3196434B2 (ja) 1993-06-23 2001-08-06 オムロン株式会社 マルチチップｉｃの製造方法
DE4433845A1 (de) * 1994-09-22 1996-03-28 Fraunhofer Ges Forschung Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung
JPH09260581A (ja) 1996-03-19 1997-10-03 Hitachi Ltd 複合半導体装置の製造方法
US5841193A (en) * 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
JPH11233678A (ja) * 1998-02-16 1999-08-27 Sumitomo Metal Electronics Devices Inc Ｉｃパッケージの製造方法
US6348728B1 (en) 2000-01-28 2002-02-19 Fujitsu Limited Semiconductor device having a plurality of semiconductor elements interconnected by a redistribution layer
JP3629178B2 (ja) * 2000-02-21 2005-03-16 Ｎｅｃエレクトロニクス株式会社 フリップチップ型半導体装置及びその製造方法
JP4178715B2 (ja) 2000-04-14 2008-11-12 松下電器産業株式会社 半導体装置およびその製造方法
JP2001320015A (ja) 2000-05-12 2001-11-16 Sony Corp 半導体装置およびその製造方法
JP3455948B2 (ja) 2000-05-19 2003-10-14 カシオ計算機株式会社 半導体装置およびその製造方法
JP2002110714A (ja) 2000-10-02 2002-04-12 Sony Corp チップ集積ボード及びその製造方法、チップ状電子部品及びその製造方法、電子機器及びその製造方法
JP2002170714A (ja) 2000-12-01 2002-06-14 Tokin Corp 積層インダクタンス素子及びその製造方法

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100426496C (zh) * 2004-05-26 2008-10-15 松下电器产业株式会社 半导体器件及其制造方法
CN1949506B (zh) * 2005-10-11 2010-05-26 索尼株式会社 混合模块和其制造方法
US8008760B2 (en) 2008-02-14 2011-08-30 Kabushiki Kaisha Toshiba Integrated semiconductor device
CN102439719B (zh) * 2009-05-14 2015-06-24 高通股份有限公司 系统级封装
CN102439719A (zh) * 2009-05-14 2012-05-02 米辑电子股份有限公司 系统级封装
CN101930958A (zh) * 2010-07-08 2010-12-29 日月光半导体制造股份有限公司 半导体封装件及其制造方法
CN102142405A (zh) * 2010-10-27 2011-08-03 日月光半导体制造股份有限公司 半导体封装结构及其制作方法
CN110517964A (zh) * 2014-09-11 2019-11-29 株式会社吉帝伟士 半导体装置及其制造方法
CN110462825A (zh) * 2017-03-29 2019-11-15 日本电产株式会社 半导体封装装置及其制造方法
CN110462825B (zh) * 2017-03-29 2023-07-11 日本电产株式会社 半导体封装装置及其制造方法
CN110010597A (zh) * 2019-03-29 2019-07-12 上海中航光电子有限公司 芯片封装结构及其封装方法
US10790225B1 (en) 2019-03-29 2020-09-29 Shanghai Avic Opto Electronics Co., Ltd. Chip package structure and chip package method including bare chips with capacitor polar plate
CN112786460A (zh) * 2019-11-08 2021-05-11 珠海格力电器股份有限公司 芯片的封装方法及芯片封装模块
CN112739054A (zh) * 2020-12-11 2021-04-30 昆山丘钛光电科技有限公司 一种smt元件贴片方法及电路板

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