CN1470067A - 倒装片衬底设计 - Google Patents

倒装片衬底设计 Download PDF

Info

Publication number
CN1470067A
CN1470067A CNA018145981A CN01814598A CN1470067A CN 1470067 A CN1470067 A CN 1470067A CN A018145981 A CNA018145981 A CN A018145981A CN 01814598 A CN01814598 A CN 01814598A CN 1470067 A CN1470067 A CN 1470067A
Authority
CN
China
Prior art keywords
tube core
lead frame
cavity
chip device
connects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA018145981A
Other languages
English (en)
Other versions
CN1240129C (zh
Inventor
小H・T・格拉纳达
小H·T·格拉纳达
肿
R·乔希
C·坦浦兹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Publication of CN1470067A publication Critical patent/CN1470067A/zh
Application granted granted Critical
Publication of CN1240129C publication Critical patent/CN1240129C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/041—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction having no base used as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

一种芯片器件包括具有管芯连接空腔(11)的框(10)、位于该空腔内的管芯(13)和焊球(21，22)。

Description

倒装片衬底设计
                             发明背景
1.技术领域
本发明涉及芯片器件，特别是诸如MOSFET之类的离散电源元件，以及诸如包括引线框的存储电路之类的IC，该引线框包括用于接纳管芯的空腔。
2.现有技术的描述
芯片器件通常包括引线框和与之连接的凸形管芯。许多封装是多片的，而且依赖于作为管芯和封装之间互连的导线连接。另外，许多BGA(球栅阵列)衬底不具有接受被预先连接的焊球或在衬底上的被磨成空腔以有助于管芯连接的能力。
这些现有技术的封装限制了形成薄封装的能力。另外，这些器件的生产过程的效率也不高。
                             发明内容
本发明提供了一种芯片器件，它包括管芯和引线框。该引线框包括管芯连接空腔。该管芯连接空腔的厚度基本与管芯的相同。该管芯位于该空腔内并用标准的管芯连接工艺连接在其中。
根据本发明的一个方面，沿引线框的周围确定多个凹座以容纳焊球。
根据本发明的另一个方面，该引线框由铜合金构成。
根据本发明的还有一个方面，该引线框包括可焊接的涂层。
本发明还提供了一种制作存储器件的方法。该方法包括提供一管芯和提供一包括管芯连接空腔的引线框。该引线框包括多个沿引线框的周围确定的凹座。该管芯连接空腔具有的厚度与管芯基本相同。焊球被设置入该凹座内。该管芯被倒装入管芯连接空腔。
由于热量除了因为与引线框结构接触而从管芯底部散发，还从管芯的表面(热量产生的位置)散发，所以得到的芯片器件提高了热性能。存储器件还具有与当今小型化趋势的TSSOP支座可相比拟的较薄封装。通过删除诸如导线连接、铸模、成形和电镀之类的步骤，与常规组装过程相比，该生产过程被简化了。
本发明的其它特征和优点将在以下参考相同数字表示相同元件的附图中通过对较佳典型实施例的阅读和理解得到认识。
                           附图说明
图1是根据本发明的倒装片引线框架的立体图；
图2是在包括焊球和管芯的图1中所示的倒装片引线框架的立体图；以及
图3是凸形的管芯的侧视图。
                   对较佳典型实施例的详细描述
图1示出了根据本发明用于生产芯片器件的引线框架10。该引线框架包括限定于引线框架中的管芯连接空腔11。在较佳的实施例中，沿引线框架的周围确定多个凹座12。
如图2所示，在空腔内设置管芯13以完成芯片器件。管芯13较佳为单片产品，在本技术中通常被称为“凸形管芯”。如图3所示，凸形管芯包括管芯13、作为管芯顶层和焊块21之间中间层20的“下块材料”以及焊块本身。较佳地，下块材料是TiW、Cu、Au或等价物中的一种。在图3所示的例子中，下块材料被分成三层-镀铜层20a、铜溅射层20b和钛溅射层20d。
将管芯连接片区域蚀刻出来，以使空腔的深度与管芯的厚度相同。较佳地，引线框架由诸如铜基Eftec 3S之类的导热导电合金制成的材料构成。另外，在较佳的实施例中，对引线框架用诸如NiPd之类的可焊涂层进行涂层。
焊球22被置于凹座内。由于引线框架是导电的，所以这些焊球起到连接漏极区的作用。焊块21起到连接源区和栅区的作用。
在引线框生产厂家或在IC封装的组装中，可用产品代码和其它的生产代码来标记引线框的反向侧。
作为该结构的结果，凸形管芯可以是通过常规管芯连接工艺连接入引线框空腔内的管芯。凸形管芯上的焊球(在空腔和凹座内的)形成了源和栅到PCB的连接，在引线框上的焊球形成了漏极连接。
从而，本发明提供了一种改进的芯片器件，诸如MOSFET BGA，该器件的热性能得到了改进。热性能的改进是由于热量既从管芯的表面(热量产生的位置)散发又因为与引线框结构接触而从管芯的底部散发。另外，本发明提供了一种芯片器件，由该器件得到了与TSSOP支座可比拟的较薄封装(通常小于1毫米)，这是当今用于小型化的趋势。由于已去除了引线框引线的焊球连接，并排除了诸如导线连接、铸模、成形和电镀之类常规的组装加工步骤，生成过程也得到了简化。
虽然已参考特定的典型实施例描述了本发明，但可以理解的是，该描述是旨在覆盖所有在所附权利要求范围之内的修改及其等效文件。

Claims (10)

1.一种芯片器件，包括：
a.一管芯；以及
b.一包括管芯连接空腔的引线框，该管芯连接空腔的厚度与管芯的基本相同；
c.其中，该管芯位于该管芯连接空腔内并连接于其中。
2.根据权利要求1所述的芯片器件，其特征在于，还包括多个在在引线框边缘的周围确定的凹座，用以容纳焊球。
3.根据权利要求1所述的芯片器件，其特征在于，该引线框由铜合金组成。
4.根据权利要求3所述的芯片器件，其特征在于，该引线框包括可焊接的涂层。
5.根据权利要求1所述的芯片器件，其特征在于，该管芯为凸形管芯。
6.一种芯片器件，包括：
a.一凸形管芯；
b.一引线框，包括管芯连接空腔和多个沿引线框的周围确定的凹座，该管芯连接空腔具有的厚度与管芯的基本相同；以及
c.多个置于该凹座内的焊球；
其中，该管芯位于该空腔内并连接于其中。
7.根据权利要求6所述的芯片器件，其特征在于，该引线框由铜合金构成。
8.根据权利要求7所述的芯片器件，其特征在于，该引线框包括可焊接的涂层。
9.一种制造芯片器件的方法，该方法包括：
提供一管芯；
提供一包括管芯连接空腔和多个沿其周围确定的凹座的引线框，该管芯连接空腔具有的厚度与管芯的基本相同；
将焊球置于该凹座内；以及将该管芯倒装入该管芯连接空腔并将其连接在其中。
10.根据权利要求9所述的方法，其特征在于，该提供的管芯为凸形管芯。
CNB018145981A 2000-07-19 2001-07-18 倒装片衬底设计 Expired - Fee Related CN1240129C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/619,115 US6661082B1 (en) 2000-07-19 2000-07-19 Flip chip substrate design
US09/619,115 2000-07-19

Publications (2)

Publication Number Publication Date
CN1470067A true CN1470067A (zh) 2004-01-21
CN1240129C CN1240129C (zh) 2006-02-01

Family

ID=24480517

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB018145981A Expired - Fee Related CN1240129C (zh) 2000-07-19 2001-07-18 倒装片衬底设计

Country Status (6)

Country Link
US (2) US6661082B1 (zh)
JP (1) JP2004504724A (zh)
CN (1) CN1240129C (zh)
AU (1) AU2001277013A1 (zh)
DE (1) DE10196439T1 (zh)
WO (1) WO2002007217A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103878462A (zh) * 2012-12-20 2014-06-25 浙江大学 使用小焊块取代焊锡片的焊接方式
CN106098568A (zh) * 2015-05-01 2016-11-09 颀邦科技股份有限公司 具有中空腔室的半导体封装制造过程
CN103094238B (zh) * 2011-10-31 2017-07-14 索尼公司 引线框架和半导体器件

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6720642B1 (en) * 1999-12-16 2004-04-13 Fairchild Semiconductor Corporation Flip chip in leaded molded package and method of manufacture thereof
US6989588B2 (en) * 2000-04-13 2006-01-24 Fairchild Semiconductor Corporation Semiconductor device including molded wireless exposed drain packaging
US6870254B1 (en) * 2000-04-13 2005-03-22 Fairchild Semiconductor Corporation Flip clip attach and copper clip attach on MOSFET device
US6661082B1 (en) * 2000-07-19 2003-12-09 Fairchild Semiconductor Corporation Flip chip substrate design
US6753605B2 (en) * 2000-12-04 2004-06-22 Fairchild Semiconductor Corporation Passivation scheme for bumped wafers
US6798044B2 (en) * 2000-12-04 2004-09-28 Fairchild Semiconductor Corporation Flip chip in leaded molded package with two dies
US6469384B2 (en) * 2001-02-01 2002-10-22 Fairchild Semiconductor Corporation Unmolded package for a semiconductor device
US6777786B2 (en) * 2001-03-12 2004-08-17 Fairchild Semiconductor Corporation Semiconductor device including stacked dies mounted on a leadframe
US6645791B2 (en) * 2001-04-23 2003-11-11 Fairchild Semiconductor Semiconductor die package including carrier with mask
US7061077B2 (en) 2002-08-30 2006-06-13 Fairchild Semiconductor Corporation Substrate based unmolded package including lead frame structure and semiconductor die
US20040084508A1 (en) * 2002-10-30 2004-05-06 Advanpack Solutions Pte. Ltd. Method for constraining the spread of solder during reflow for preplated high wettability lead frame flip chip assembly
US6762495B1 (en) * 2003-01-30 2004-07-13 Qualcomm Incorporated Area array package with non-electrically connected solder balls
US7217594B2 (en) * 2003-02-11 2007-05-15 Fairchild Semiconductor Corporation Alternative flip chip in leaded molded package design and method for manufacture
US7196313B2 (en) * 2004-04-02 2007-03-27 Fairchild Semiconductor Corporation Surface mount multi-channel optocoupler
US7256479B2 (en) * 2005-01-13 2007-08-14 Fairchild Semiconductor Corporation Method to manufacture a universal footprint for a package with exposed chip
KR101297645B1 (ko) 2005-06-30 2013-08-20 페어차일드 세미컨덕터 코포레이션 반도체 다이 패키지 및 그의 제조 방법
US7504733B2 (en) 2005-08-17 2009-03-17 Ciclon Semiconductor Device Corp. Semiconductor die package
US7560808B2 (en) * 2005-10-19 2009-07-14 Texas Instruments Incorporated Chip scale power LDMOS device
US7285849B2 (en) * 2005-11-18 2007-10-23 Fairchild Semiconductor Corporation Semiconductor die package using leadframe and clip and method of manufacturing
US7446375B2 (en) * 2006-03-14 2008-11-04 Ciclon Semiconductor Device Corp. Quasi-vertical LDMOS device having closed cell layout
US7768075B2 (en) 2006-04-06 2010-08-03 Fairchild Semiconductor Corporation Semiconductor die packages using thin dies and metal substrates
US7618896B2 (en) 2006-04-24 2009-11-17 Fairchild Semiconductor Corporation Semiconductor die package including multiple dies and a common node structure
US20080036078A1 (en) * 2006-08-14 2008-02-14 Ciclon Semiconductor Device Corp. Wirebond-less semiconductor package
US7768105B2 (en) 2007-01-24 2010-08-03 Fairchild Semiconductor Corporation Pre-molded clip structure
US20090166826A1 (en) * 2007-12-27 2009-07-02 Janducayan Omar A Lead frame die attach paddles with sloped walls and backside grooves suitable for leadless packages
US20090194856A1 (en) * 2008-02-06 2009-08-06 Gomez Jocel P Molded package assembly
US20090261462A1 (en) * 2008-04-16 2009-10-22 Jocel Gomez Semiconductor package with stacked die assembly
US7855439B2 (en) * 2008-08-28 2010-12-21 Fairchild Semiconductor Corporation Molded ultra thin semiconductor die packages, systems using the same, and methods of making the same
US7829988B2 (en) * 2008-09-22 2010-11-09 Fairchild Semiconductor Corporation Stacking quad pre-molded component packages, systems using the same, and methods of making the same
US8314499B2 (en) * 2008-11-14 2012-11-20 Fairchild Semiconductor Corporation Flexible and stackable semiconductor die packages having thin patterned conductive layers
US8049312B2 (en) * 2009-01-12 2011-11-01 Texas Instruments Incorporated Semiconductor device package and method of assembly thereof
US7973393B2 (en) 2009-02-04 2011-07-05 Fairchild Semiconductor Corporation Stacked micro optocouplers and methods of making the same
US20100289129A1 (en) * 2009-05-14 2010-11-18 Satya Chinnusamy Copper plate bonding for high performance semiconductor packaging
US11209598B2 (en) 2019-02-28 2021-12-28 International Business Machines Corporation Photonics package with face-to-face bonding

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3972062A (en) * 1973-10-04 1976-07-27 Motorola, Inc. Mounting assemblies for a plurality of transistor integrated circuit chips
US5834339A (en) * 1996-03-07 1998-11-10 Tessera, Inc. Methods for providing void-free layers for semiconductor assemblies
US5629835A (en) * 1994-07-19 1997-05-13 Olin Corporation Metal ball grid array package with improved thermal conductivity
US5789809A (en) * 1995-08-22 1998-08-04 National Semiconductor Corporation Thermally enhanced micro-ball grid array package
US5637916A (en) * 1996-02-02 1997-06-10 National Semiconductor Corporation Carrier based IC packaging arrangement
US5814884C1 (en) * 1996-10-24 2002-01-29 Int Rectifier Corp Commonly housed diverse semiconductor die
KR100234719B1 (ko) * 1997-03-14 1999-12-15 김영환 에리어 어레이 패키지 및 그 제조방법
US6423623B1 (en) * 1998-06-09 2002-07-23 Fairchild Semiconductor Corporation Low Resistance package for semiconductor devices
US6133634A (en) * 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
US6329713B1 (en) * 1998-10-21 2001-12-11 International Business Machines Corporation Integrated circuit chip carrier assembly comprising a stiffener attached to a dielectric substrate
US6720642B1 (en) * 1999-12-16 2004-04-13 Fairchild Semiconductor Corporation Flip chip in leaded molded package and method of manufacture thereof
US6624522B2 (en) * 2000-04-04 2003-09-23 International Rectifier Corporation Chip scale surface mounted device and process of manufacture
US6661082B1 (en) * 2000-07-19 2003-12-09 Fairchild Semiconductor Corporation Flip chip substrate design
US6753605B2 (en) * 2000-12-04 2004-06-22 Fairchild Semiconductor Corporation Passivation scheme for bumped wafers
US6798044B2 (en) * 2000-12-04 2004-09-28 Fairchild Semiconductor Corporation Flip chip in leaded molded package with two dies
US6469384B2 (en) * 2001-02-01 2002-10-22 Fairchild Semiconductor Corporation Unmolded package for a semiconductor device
US6683375B2 (en) * 2001-06-15 2004-01-27 Fairchild Semiconductor Corporation Semiconductor die including conductive columns
US6633030B2 (en) * 2001-08-31 2003-10-14 Fiarchild Semiconductor Surface mountable optocoupler package
US6566749B1 (en) * 2002-01-15 2003-05-20 Fairchild Semiconductor Corporation Semiconductor die package with improved thermal and electrical performance
WO2003079407A2 (en) * 2002-03-12 2003-09-25 Fairchild Semiconductor Corporation Wafer-level coated copper stud bumps
US6836023B2 (en) * 2002-04-17 2004-12-28 Fairchild Semiconductor Corporation Structure of integrated trace of chip package
US6806580B2 (en) * 2002-12-26 2004-10-19 Fairchild Semiconductor Corporation Multichip module including substrate with an array of interconnect structures

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103094238B (zh) * 2011-10-31 2017-07-14 索尼公司 引线框架和半导体器件
CN103878462A (zh) * 2012-12-20 2014-06-25 浙江大学 使用小焊块取代焊锡片的焊接方式
CN106098568A (zh) * 2015-05-01 2016-11-09 颀邦科技股份有限公司 具有中空腔室的半导体封装制造过程

Also Published As

Publication number Publication date
AU2001277013A1 (en) 2002-01-30
US6661082B1 (en) 2003-12-09
WO2002007217A1 (en) 2002-01-24
CN1240129C (zh) 2006-02-01
DE10196439T1 (de) 2003-11-13
US20050051878A1 (en) 2005-03-10
JP2004504724A (ja) 2004-02-12
US7101734B2 (en) 2006-09-05

Similar Documents

Publication Publication Date Title
CN1240129C (zh) 倒装片衬底设计
JP4850184B2 (ja) 標準占有面積を含む半導体ダイパッケージ及びその製造方法
USRE45931E1 (en) Method of manufacturing a semiconductor device
US7160759B2 (en) Semiconductor device and method of manufacturing the same
US7816769B2 (en) Stackable packages for three-dimensional packaging of semiconductor dice
US5650667A (en) Process of forming conductive bumps on the electrodes of semiconductor chips using lapping and the bumps thereby created
US6022759A (en) Method for producing a semiconductor device, base member for semiconductor device and semiconductor device unit
US6358778B1 (en) Semiconductor package comprising lead frame with punched parts for terminals
US7425755B2 (en) Semiconductor package, method for manufacturing the same and lead frame for use in the same
CN101060087A (zh) 电极及其制造方法,以及具有该电极的半导体器件
JPH1167809A (ja) 半導体装置
US20030003627A1 (en) Method for manufacturing a resin-sealed semiconductor device
KR100804341B1 (ko) 반도체장치 및 그 제조방법
US20020003308A1 (en) Semiconductor chip package and method for fabricating the same
CN1855450A (zh) 高散热性的半导体封装件及其制法
JP2006527924A (ja) 積層可能な集積回路パッケージおよびその方法
EP0210371A1 (en) Semiconductor device having a plurality of leads
US20030124775A1 (en) Semiconductor device, semiconductor device manufacturing method, circuit board, and electronic device
US6428908B1 (en) Contact and method for producing a contact
US20040119146A1 (en) Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
JP4084984B2 (ja) 半導体装置の製造方法
KR200179419Y1 (ko) 반도체패키지
JPH0645497A (ja) 半導体装置およびその製造方法
JPH03105961A (ja) 樹脂封止型半導体装置
CN1374693A (zh) 具有散热结构的半导体封装件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20060201

Termination date: 20160718