CN1498423A - 混合模拟和数字集成电路 - Google Patents

混合模拟和数字集成电路 Download PDF

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Publication number
CN1498423A
CN1498423A CNA028058496A CN02805849A CN1498423A CN 1498423 A CN1498423 A CN 1498423A CN A028058496 A CNA028058496 A CN A028058496A CN 02805849 A CN02805849 A CN 02805849A CN 1498423 A CN1498423 A CN 1498423A
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Prior art keywords
die
circuit
digital
integrated circuit
analog
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CN100355071C (zh
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S
S·巴扎贾尼
张海涛
Q·周
S·杰哈
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Qualcomm Inc
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Qualcomm Inc
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Abstract

一种在分立管心上制造模拟和数字电路，并将所述管心堆积和集成在单个封装内以形成混合信号IC的技术提供许多益处。在一方面，使用适合于这些不同类型电路的可能不同IC处理，在两种分立管心上实现所述模拟和数字电路。其后，将模拟和数字管心集成(堆积)并密封在该单个封装内。提供焊盘以互连管心并将管心连接到外部引脚上。焊盘可以位于并按提供所需的连通性的方式排列，同时使实现焊盘所需管心面积减少到最小。在另一方面，可以连同串行总线接口一起测试管心至管心的连通性。

Description

混合模拟和数字集成电路
                            发明背景
发明领域
本发明一般涉及电路，而更特殊地涉及用于在分立管心上制造模拟和数字电路，以及将管心堆积和集成到单个封装内的技术。
发明背景
许多应用需要模拟和数字两种信号处理。一种这样的应用是无线通信领域，在该领域中，在发射和接收端都需要混合的模拟和数据信号处理。在接收端，调制的模拟信号(通常为射频)经过接收，调节(例如放大和滤波)，下变频，正交解调，及数字化以提供样本。然后对样本进行数字信号处理，恢复发射的数据。而在发射端，数据经处理(例如，编码，交替和扩展)，并然后转换为一个或多个模拟信号。该模拟信号再经调节，调制，及上变频以提供适合于无线电线路内发射的调制信号。混合信号电路也可以用于无线通信的其他方面，并包含声音/音频编码器/解码器，通用模拟-数字转换器(ADC)，以各种信号数字化，例如电池电压和温度，以及其他电路。对于例如连网，计算机及其他的许多其他应用也需要混合信号处理。
按照惯例，用经ADC和数字-模拟转换器(DAC)实现的两片IC之间的接口，经分立模拟和数字集成电路(IC)实现模拟和数字信号处理。数字电路趋向于产生大量开关噪声。相反，模拟电路通常含有各种敏感电路(例如，振荡器，放大器等等)，这些电路更喜欢，或需要在相当的环境(quite environment)中运行。在分立IC内实现模拟和数字电路允许对这些电路进行隔离，并能工作在最佳的环境中。而且，模拟和数字电路的最佳处理技术通常也不同。数字电路经常用标准的CMOS处理来实现，然而模拟电路可能利用线性电容和电阻，这些元件需要在标准的CMOS处理上，再增加额外处理步骤。
为了减少生产成本和生产工艺复杂性，在一片混合信号IC内的共衬底上可以制造模拟和数字两种电路。该混合信号IC提供了许多益处，例如减少成本，更少的元件数量，较小的所需印刷板面积，简化测试，及可能的其他益处。
然而，在共衬底上制造模拟和数字电路也有一些缺点。首先，由数字电路产生的噪声经耦合穿过该衬底降低了模拟电路的性能。第二，模拟电路可能需要线性电容和电阻，这些元件满足特殊IC处理的需要，例如模拟CMOS。这样，虽然模拟电路可能仅占该管心的一小部分，由于为模拟电路所选的IC处理，增加了数字电路成本。第三，数字电路通常受益于工艺缩放比例(technologyscaling)(例如减少晶体管大小，降低工作电压)，但是模拟电路可能要遭受电压缩放比例之损害。及第四，混合信号IC的设计周期可能持续很长，因为模拟电路的设计周期通常比数字电路更长。
如能看到的，需要一种制造和集成模拟和数字电路的技术工艺，以能获得混合信号IC的益处，同时能使共衬底上制造传统混合信号IC的缺点减少到最小。
发明摘要
本发明的几个方面提供在分立管心上制造模拟和数字电路及将管心堆积和集成在单个封装内的技术，以形成能提供上述许多益处的混合信号IC。一方面，可能使用适合于那些不同类型电路的不同IC处理，在两个分立管心上实现模拟和数字电路。其后，将模拟和数字管心集成(堆积)和密封在单个封装内。提供焊盘，以互连接这两种管心，并将管心连接到外部引脚上。可以按提供所需连接性方式定位和排列这些焊盘，同时使实现这些焊盘所需的管心区域数量减少到最小。另一方面，管心与管心的连接性可以连同串行总线接口一起进行测试。又在另一方面，在等待模式期间，可以崩溃供给模拟管心内的某部分或所有电路的电源(及可能提供给数字管心的某些或全部电路的电源)(例如，电压降到0伏)，以延长运行时间。
本发明进一步提供实现本发明的各方面，实施例及特征的集成电路，方法，和元件，如下面进一步详细描述的。
附图简述
从下面连同附图阐明的详细描述中将更明白本发明的功能，特性，和优点。其中：
图1是展示按照本发明实施例的混合信号IC的顶视图；
图2是展示所述混合信号IC的侧视图，该IC密封在特殊IC封装内；
图3A到3C是展示该混合信号IC各层间互连接的侧视图；及
图4A和4B是展示模拟和数字管心间互连接的顶视图。
发明详述
本发明的几个方面提供用于在分立管心上制造模拟和数字电路及堆积管心以安装在单个封装内的技术。本发明的混合信号IC提供混合信号IC的许多益处，同时使在共衬底上制造的传统混合信号IC的缺点减少到最小。在一方面，用适合于这些电路的IC处理在两个分立管心上实现模拟和数字电路。例如，用先进的低压数字CMOS技术可以实现数字电路，以节省成本，功耗和硅片面积。依据所需的性能，可以用低成本，成熟的模拟CMOS技术设计和实现模拟电路，以节省功耗，或可以用高性能技术进行设计。此后，将模拟和数字管心集成(堆积)和密封在单个封装内，如下面进一步详述的。
图1是展示按照本发明实施例混合信号IC 100的顶视图。混合信号IC 100包括模拟管心130堆积在数字管心120的顶部，数字管心120又堆积在封装衬底110的顶部。对于许多应用，模拟管心的大小仅为数字管心尺寸的一小部分(例如，通常为1/8到1/4)。例如，模拟管心130的大小为1.5毫米乘2毫米，而数字管心120的大小为6毫米乘6毫米。这样，较小的模拟管心可以堆积在数字管心顶部，以节省空间并允许使用较小的封装。
模拟和数字管心可以为任何形状和大小。对于某些电路和IC处理，更喜欢用某一种纵横比的管心。例如，因为容易制造和其他的益处，更喜欢用正方形管心。
如图1所示，在封装衬底110四边提供有许多焊盘112。这些焊盘112可以用于提供模拟和数字管心的输入/输出(I/O)。数字管心120也包含许多焊盘122，焊盘122经焊接线123可以互连接到封装衬底110上相应的焊盘112。相似地，模拟管心130含有许多焊盘132，可经过焊接线133互连接到封装衬底110上相应的焊盘112。模拟管心130进一步包含许多焊盘134，经过焊接线135可以互连接到数字管心120上相应的焊盘124。
在选择数字管心120的特定区域以放置模拟管心130时，可能要考虑各种因素。如果将模拟管心130放置在数字管心120上相当大(more quite)的区域时，可以改善性能。模拟管心130也可以较佳地放置在数字管心120的几部分上(over sections of)，所需的调试很可能较少。例如，数字管心120可以包含一部分存储电路(例如RAM和/或ROM)，存储电路更倾向于电路故障并很可能需要更多的存取，以调试这些电路。如果那样的话，模拟管心130可以放置在数字管心120的另一个区域，该区域很可能只需较少的存取。模拟管心130也可以放置在数字管心120的边缘或拐角上。这样可以使模拟管心130上的焊盘132和封装衬底110上相应焊盘112之间的互连接(即，焊接线)更短。也可以依据模拟管心和整个封装的外部引脚放置模拟管心130。各种其他因素也可以加以考虑并都在本发明范畴内。
图2是展示混合信号IC 100的侧视图，该IC 100密封在特殊的IC封装内。如图2所示，一层管心附着剂140扩散在封装衬底110顶部，然后将数字管心120放置在管心附着剂层上面。然后将第二层管心附着剂140扩散在数字管心120的顶部，并将模拟管心130放置在第二层管心附着剂层顶部。管心附着层用于将管心和封装衬底附着(即，粘合)在一起。模压混合物150可以用于填充由模拟和数字管心留下的空隙。
混合信号IC 100可以用各种类型的封装进行封装。可以依据各种因素，例如所需的引脚数，较佳的引脚排列，可制造性等等，选择特定封装。在图2所示的例子中，混合信号IC 100是按商用的，标准精密球珊阵列(F-BGA)封装进行封装的，F-BGA含有技术上已知的尺寸和大小。
在实施例中，为了将混合信号IC 100密封在具有确定高度尺寸的标准封装内，可能要将模拟管心130和/或数字管心120的厚度控制在特殊限度尺寸内。通过“背研”用于制造管心的晶片可以减少模拟和数字管心的厚度。在实施例中，将晶片背研到200微米，虽然也可使用某些其他厚度值。通过减少模拟和数字管心的厚度，可以使堆积管心具有：(1)类似于通常密封在那种封装内的单片管心的外形，或(2)符合该封装规格的外形。
图3A到3C是展示混合信号IC100各层间互连接的侧视图。图3A展示数字管心120和封装衬底110间的互连接。这种互连接是通过焊盘112和122及焊接线123实现的，这两个焊盘分别位于封装衬底和数字管心上。可以按通常用于那种封装的方式实现这种互连接。
图3B示出模拟管心130和封装衬底110间的互连接。这种互连接是通过焊盘112和132及焊接线133实现的，这两个焊盘分别位于封装衬底和模拟管心上。也可以按标准方式实现这种互连接。
图3C示出模拟管心130和数字管心120间的互连接，这种互连接是通过焊盘134和124及焊接线135实现的，这两个焊盘分别位于模拟和数字管心上。也可以按标准方式实现这种互连接。
图4A和4B是展示模拟管心和数字管心间互连接的顶视图。在图4A中，模拟管心130上提供第一组焊盘132，用于与封装衬底110互连接，并提供第二组焊盘134，用于与数字管心120互连接。类似地，数字管心120上提供第一组焊盘122，用于与封装衬底110互连接，并提供第二组焊盘124，用于与模拟管心130互连接。
在一方面，数字管心120上的焊盘122和124是“数字化间的(inter-digitized)”，那里有可能这样，焊盘122和124交替地位于(沿着直线)数字管心上。用数字化间的焊盘排列，需要最小的附加管心区(即便要)，以实现数字管心120上附加焊盘124以连接到模拟管心130。按这种方式，将模拟管心130堆积在数字管心120顶部不会引起性能损失。替代地，可以将一组数字管心120上的管心到管心焊盘放置在该数字管心上的一组外部引脚之间。这种排列也不会引起性能损失。
在实施例中，模拟管心130的焊盘132和134位于该模拟管心边缘附近，并接近于数字管心120和封装衬底110的边缘，最后这些焊盘耦合到此。这种焊盘布局便于模拟管心130和数字管心120及封装衬底110之间的互连接(例如实现数字化间连接)。这也导致使模拟管心130的焊接线更短，这可以改善性能。在实施例中，数字管心120的焊盘122和124也可以位于该数字管心边缘附近。数字管心120焊盘的这种放置避免侵入数字电路区域。在数字管心的中心区焊盘放置可能妨碍(即，阻塞)信号线的通路。
图4B示出模拟和数字管心之间的互连接，使用远离于数字管心120边缘的焊盘126。对于某些特定设计，这可能有利于互连接到远离数字管心边缘的数字电路。例如为了使模拟电路和数字电路之间的互连接更短，或者为了在模拟管心上提供更多的I/O焊盘，可能会需要这种连接。在这种情况，可以在数字管心120上提供焊盘126，以互连接到模拟管心130上相应的焊盘136。
这里描述的堆积模拟和数字管心提供许多优点。首先，通过使模拟和数字电路分为两个管心，可以为每种电路选择最佳的加工技术。可以为模拟和数字电路选择不同的技术。第二，可以消除经硅共衬底耦合的噪声。第三，能够按不同方案研制模拟和数字电路，以使一种电路类型(例如，模拟)不会阻挡其他电路类型的设计。而且，可以设计和修改每一种电路类型，并不会影响其他电路类型的设计。也可以用这里描述的堆积模拟和数字管心设计，实现其他益处。
本发明另一方面提供测试这种堆积模拟和数字管心的技术。每种管心可以单独测试(例如，在晶片级)以保证在管心上制造的电路具有适当功能。在模拟和数字管心经过堆积，互连接，并密封在封装后，可以进行附加测试，以保证经焊接线的互连接是有效的(即，保证连通性)。然而，因为管心到管心的互连接不能直接经过外部引脚可存取，这里提供测试这些互连接的技术。
在实施例中，管心到管心互连接性测试是连同标准串行总线接口(SBI)实现的，该测试是按技术上已知的方式操作。这了实现这种接口，可以设计数字管心，并将该数字管心操作为“主”驱动器，控制该测试功能(例如，断电，方式选择，等等)，而将模拟管心操作为“从”驱动器，实现由数字管心提供的控制。含有控制值序列的测试向量可以从数字管心发送到模拟管心，以执行管心到管心的测试。
在实施例中，在模拟管心上为每路待测试的管心到管心的互连接提供多路复用器。该多路复用器含有用于正常运行的第一个输入端，用于测试的第二个输入端，运行耦合到管心至管心焊盘的输出端，和控制输入端。为了测试从模拟管心读取数值，第二个输入端和控制输入端分别从模拟管心上的从驱动器接收测试值和控制信号，它能够命令多路复用器将特殊测试值经多路复用器提供给管心至管心焊盘。在数字管心，接收来自模拟管心的测试值并可以传送给外部输出焊盘(例如，经过另一个多路复用器)。然后测试值进行检测并与经串行总线接口提供给从驱动器的数值进行比较。
为了测试将数值写到模拟管心，可以将测试值从外部输出焊盘发送到数字管心上的管心至管心焊盘(例如经过一个多路复用器)。然后，由模拟管心上的另一个多路复用器接收该测试值。由从动驱动器可以控制模拟管心上的这个多路复用器，将所接收的测试值传送给从驱动器，然后在串行总线接口上提供该数值。对经数字管心提供的测试值和来自串行总线接口的检测值进行比较，以保证适当的连接性。
这样，串行总线接口可以用于测试对模拟管心的读和写。串行总线接口用于控制模拟管心上的多路复用器，测试管心至管心的互连接性。串行总线接口也用于经过数字管心，将测试值提供给模拟管心(用于写)并取回由模拟管心经过管心至管心互连接所接收的测试值(用于读)。
本发明的另一方面提供技术，以控制模拟管心及或许数字管心上的电路和/或电源，为了在等待模式期间转换电源。可以激活无线通信系统中的远地端，并在某个时间段全速运行，而在其他时间段关掉电源或进入等待模式，以保存电源并延长在电池重新充电之间的工作寿命。在等待模式，希望尽可能地使更多电路关掉电源，以减少电源消耗。然而，关掉电源的电路还会导致漏电流，漏电流能使远地端的工作寿命变短。可通过使供给这些电路的电源“崩溃”(例如，降低到0伏)，可以消除这种漏电流。
对于按上述方式实现的混合信号IC，希望在等待模式时，尽可能地将模拟管心内更多的电路断电和/或使电源崩溃。当提供所需性能激活时，在模拟管心上的模拟电路可能消耗(相对地)大量的电流。模拟电路也可按与数字电路不同的电压工作。例如，模拟电路工作的电源电压为3.3伏，而数字电路工作的电源电压为1.8伏。可以从外部电源(例如，电源管理装置)经外部引脚给模拟管心供电。
在实施例中，串行总线接口用于控制某些或全部模拟电路的运行，并在等待模式期间崩溃电源。模拟管心上的从驱动器可以设计成基于数字式电源工作，在整个等待模式周期维持运行。在模拟管心上提供电平偏移电路，将来自从驱动器的数字控制信号转换为所需的信号电平，该信号电平是控制模拟管心上各种类型的模拟电路(例如振荡器，相锁环电路，前端接收机电路，等等)所需的。从动驱动器从数字管心经过串行总线接口接收命令，以控制模拟管心上的电路运行。在响应时，从驱动器产生控制信号，命令模拟管心上的模拟电路按规定方式运行。从驱动器能够维持电路的设置，因为既使在等待模式，从驱动器还通电。
在等待模式，串行总线接口用于命令电源管理装置崩溃模拟管心内所选电路(所有电路或子电路)的电压。这消除了漏电流，并延长了工作寿命。当不在等待模式时，串行总线接口用于命令电源管理装置给模拟管心提供电压。
这里描述的电压“可伸缩”技术也可以应用于其他的混合信号设计中，在这些设计中，模拟和数字管心不是堆积的，并可以进一步封装在分立封装内。在所述电压可伸缩技术中，等待模式时崩溃模拟管心内某些或所有电路上的电压(例如，到0伏)。电压可伸缩技术也可应用于数字管心的各种(选择的)模块。
提供所公开实施例的先前描述，使技术熟练的任何人员能够制作或使用本发明。技术熟练的人员容易明白对这些实施例的各种修改，并且，这里所定义的一般原理可以应用到其他实施例，并没有背离本发明的精神和范畴。这样，本发明不倾向限制于这里所示的实施例，但符合与这里所描述的原理和新颖功能相一致的广泛范畴。

Claims (19)

1、一种混合信号集成电路，其特征在于，包括：
封装衬底，含有许多焊盘；
第一颗管心，含有许多焊盘，放置在所述封装衬底的顶部表面，其中，在所述第一颗管心上制造主要的数字电路；及
第二颗管心，含有许多焊盘，放置在所述第一颗管心顶部表面，其中，在所述第二颗管心上制造主要的模拟电路。
2、按照权利要求1的所述集成电路，其特征在于，所述第一颗和第二颗管心的每一颗的所述许多焊盘位于所述管心边缘附近。
3、按照权利要求1的所述集成电路，其特征在于，所述第一颗管心包括
第一组焊盘，用于与所述第二颗管心上相关焊盘互连接，及
第二组焊盘，用于与所述封装衬底上相关焊盘互连接。
4、按照权利要求3的所述集成电路，其特征在于，所述第一和第二组的焊盘是数字化间的。
5、按照权利要求3的所述集成电路，其特征在于，所述第一和第二组的焊盘交替地沿直线排列。
6、按照权利要求1的所述集成电路，其特征在于，所述第一颗管心包括远离所述第一颗管心边缘的一组焊盘。
7、按照权利要求1的所述集成电路，其特征在于，将所述封装衬底和第一及第二颗管心密封在单个封装内。
8、按照权利要求1的所述集成电路，其特征在于，所述封装衬底和所述第一及第二颗管心尺寸具有符合标准封装规格的外形。
9、按照权利要求8的所述集成电路，其特征在于，所述标准封装是一种球珊阵列。
10、按照权利要求1的所述集成电路，其特征在于，所述第一颗和第二颗管心的每一颗来自晶片，所述晶片已经过处理达到特定的厚度。
11、按照权利要求10的所述集成电路，其特征在于，所述特定厚度是通过对所述晶片进行背研(back grinding)获得的。
12、按照权利要求1的所述集成电路，其特征在于，所述第一颗和第二颗管心是用两种不同集成电路加工技术制造的。
13、按照权利要求1的所述集成电路，其特征在于，所述第一颗管心是用CMOS加工技术制造的。
14、一种混合信号集成电路，其特征在于，包括：
封装衬底，含有许多焊盘；
第一颗管心，含有许多焊盘，并且放置在所述封装衬底的顶部，其中，主要数字电路制造在所述第一颗管心上；
第二颗管心，含有许多焊盘，并且放置在一部分所述第一颗管心的顶部，其中，主要模拟电路制造在所述第二颗管心上；及
封装，密封所述封装衬底和所述第一颗及第二颗管心；及
其中，用两种不同集成电路(IC)加工技术制造所述第一颗和第二颗管心。
15、一种混合信号集成电路，其特征在于，包括：
第一颗管心，含有制造的主要数字电路；及
第二颗管心，含有制造的主要模拟电路，所述第二颗管心进一步包括耦合到接口的控制单元和一个或多个焊盘，用于接收供给所述模拟电路的一个或多个信号，其中将所述控制单元配置成控制所述第二颗管心上所选部分模拟电路的运行模式，及其中，在等待运行模式期间，能够减少所选择的一个供给信号的电压。
16、按照权利要求15所述的集成电路，其特征在于，在所述等待运行模式期间，将所选择的供给信号的电压崩溃到零。
17、按照权利要求15所述的集成电路，其特征在于，在所述等待运行模式期间，将所述控制单元维持通电。
18、一种用于测试密封在单个封装内的第一颗和第二颗管心之间的接口的方法，其特征在于，所述方法包括：
给串行总线接口提供第一个控制值，其中，所述第一个控制值直接将第一个待发送的测试值从所述第一颗管心传送到所述第二颗管心；
经过互连导线将所述第一个测试值从所述第一颗管心发送到所述第二颗管心，以响应所述第一个控制值；
在所述第二颗管心上接收所述第一个测试值；及
将所述第一个控制值与所述接收的第一个测试值进行比较，以检验所述互连导线的连接性。
19、按照权利要求18所述的方法，其特征在于，进一步包括：
经过所述互连导线将第二个测试数值从所述第二颗管心发送给所述第一颗管心；
检测所述第一颗管心上的所述第二个测试数值；
提供所述检测的第二个测试值，作为所述串行总线接口上的第二个控制值；及
将所述第二个控制值与所述第二个测试值进行比较，以检验所述互连导线的连接性。
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