CN1505833A - 使用虚拟元件来抛光集成电路器件的方法 - Google Patents
使用虚拟元件来抛光集成电路器件的方法 Download PDFInfo
- Publication number
- CN1505833A CN1505833A CNA028092643A CN02809264A CN1505833A CN 1505833 A CN1505833 A CN 1505833A CN A028092643 A CNA028092643 A CN A028092643A CN 02809264 A CN02809264 A CN 02809264A CN 1505833 A CN1505833 A CN 1505833A
- Authority
- CN
- China
- Prior art keywords
- virtual component
- active element
- integrated circuit
- available area
- polishing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000007517 polishing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 33
- 238000005498 polishing Methods 0.000 claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 30
- 239000011800 void material Substances 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 16
- 150000004767 nitrides Chemical class 0.000 description 12
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 230000007613 environmental effect Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000013043 chemical agent Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000007717 exclusion Effects 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
Abstract
Description
Claims (10)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/873,810 US6611045B2 (en) | 2001-06-04 | 2001-06-04 | Method of forming an integrated circuit device using dummy features and structure thereof |
US09/873,810 | 2001-06-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1505833A true CN1505833A (zh) | 2004-06-16 |
CN100407383C CN100407383C (zh) | 2008-07-30 |
Family
ID=25362371
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN028092643A Expired - Fee Related CN100407383C (zh) | 2001-06-04 | 2002-05-02 | 使用虚拟元件来抛光集成电路器件的方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US6611045B2 (zh) |
EP (1) | EP1397829A1 (zh) |
JP (1) | JP2004529504A (zh) |
KR (1) | KR20040004690A (zh) |
CN (1) | CN100407383C (zh) |
TW (1) | TWI226696B (zh) |
WO (1) | WO2002099865A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022061825A1 (zh) * | 2020-09-27 | 2022-03-31 | 华为技术有限公司 | 硅通孔结构的制备方法和硅通孔结构 |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6921947B2 (en) * | 2000-12-15 | 2005-07-26 | Renesas Technology Corp. | Semiconductor device having recessed isolation insulation film |
KR100418581B1 (ko) * | 2001-06-12 | 2004-02-11 | 주식회사 하이닉스반도체 | 메모리 소자의 제조방법 |
JP2003115540A (ja) * | 2001-10-04 | 2003-04-18 | Fujitsu Ltd | 半導体集積回路および半導体集積回路の製造方法 |
US6803295B2 (en) * | 2001-12-28 | 2004-10-12 | Texas Instruments Incorporated | Versatile system for limiting mobile charge ingress in SOI semiconductor structures |
US7363099B2 (en) * | 2002-06-07 | 2008-04-22 | Cadence Design Systems, Inc. | Integrated circuit metrology |
US7152215B2 (en) * | 2002-06-07 | 2006-12-19 | Praesagus, Inc. | Dummy fill for integrated circuits |
EP1532670A4 (en) * | 2002-06-07 | 2007-09-12 | Praesagus Inc | CHARACTERIZATION AND REDUCTION OF VARIATION FOR INTEGRATED CIRCUITS |
US7712056B2 (en) * | 2002-06-07 | 2010-05-04 | Cadence Design Systems, Inc. | Characterization and verification for integrated circuit designs |
US20030229875A1 (en) * | 2002-06-07 | 2003-12-11 | Smith Taber H. | Use of models in integrated circuit fabrication |
US7774726B2 (en) * | 2002-06-07 | 2010-08-10 | Cadence Design Systems, Inc. | Dummy fill for integrated circuits |
US7853904B2 (en) * | 2002-06-07 | 2010-12-14 | Cadence Design Systems, Inc. | Method and system for handling process related variations for integrated circuits based upon reflections |
US7393755B2 (en) * | 2002-06-07 | 2008-07-01 | Cadence Design Systems, Inc. | Dummy fill for integrated circuits |
US7124386B2 (en) * | 2002-06-07 | 2006-10-17 | Praesagus, Inc. | Dummy fill for integrated circuits |
US6812069B2 (en) * | 2002-12-17 | 2004-11-02 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for improving semiconductor process wafer CMP uniformity while avoiding fracture |
US6933523B2 (en) * | 2003-03-28 | 2005-08-23 | Freescale Semiconductor, Inc. | Semiconductor alignment aid |
US6905967B1 (en) * | 2003-03-31 | 2005-06-14 | Amd, Inc. | Method for improving planarity of shallow trench isolation using multiple simultaneous tiling systems |
US7071074B2 (en) | 2003-09-24 | 2006-07-04 | Infineon Technologies Ag | Structure and method for placement, sizing and shaping of dummy structures |
US7269803B2 (en) * | 2003-12-18 | 2007-09-11 | Lsi Corporation | System and method for mapping logical components to physical locations in an integrated circuit design environment |
US7305642B2 (en) * | 2005-04-05 | 2007-12-04 | Freescale Semiconductor, Inc. | Method of tiling analog circuits |
US7305643B2 (en) * | 2005-05-12 | 2007-12-04 | Freescale Semiconductor, Inc. | Method of tiling analog circuits that include resistors and capacitors |
US7767570B2 (en) * | 2006-03-22 | 2010-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy vias for damascene process |
US8003539B2 (en) | 2007-01-04 | 2011-08-23 | Freescale Semiconductor, Inc. | Integrated assist features for epitaxial growth |
US7565639B2 (en) * | 2007-01-04 | 2009-07-21 | Freescale Semiconductor, Inc. | Integrated assist features for epitaxial growth bulk tiles with compensation |
US8741743B2 (en) * | 2007-01-05 | 2014-06-03 | Freescale Semiconductor, Inc. | Integrated assist features for epitaxial growth |
US7470624B2 (en) * | 2007-01-08 | 2008-12-30 | Freescale Semiconductor, Inc. | Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation |
KR101100934B1 (ko) * | 2009-06-02 | 2012-01-02 | 주식회사 동부하이텍 | 반도체소자 및 그 제조방법 |
US8466560B2 (en) | 2010-12-30 | 2013-06-18 | Stmicroelectronics, Inc. | Dummy structures having a golden ratio and method for forming the same |
US8765607B2 (en) | 2011-06-01 | 2014-07-01 | Freescale Semiconductor, Inc. | Active tiling placement for improved latch-up immunity |
US8739078B2 (en) | 2012-01-18 | 2014-05-27 | International Business Machines Corporation | Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections for semiconductor applications |
USD729808S1 (en) * | 2013-03-13 | 2015-05-19 | Nagrastar Llc | Smart card interface |
USD780763S1 (en) * | 2015-03-20 | 2017-03-07 | Nagrastar Llc | Smart card interface |
US10811255B2 (en) * | 2018-10-30 | 2020-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming semiconductor devices |
Family Cites Families (24)
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US594873A (en) * | 1897-12-07 | Douglas stanley hewitt | ||
JPS59186342A (ja) | 1983-04-06 | 1984-10-23 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
US5285017A (en) | 1991-12-31 | 1994-02-08 | Intel Corporation | Embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias |
US5278105A (en) | 1992-08-19 | 1994-01-11 | Intel Corporation | Semiconductor device with dummy features in active layers |
TW272310B (en) | 1994-11-09 | 1996-03-11 | At & T Corp | Process for producing multi-level metallization in an integrated circuit |
TW299458B (zh) | 1994-11-10 | 1997-03-01 | Intel Corp | |
JP3366471B2 (ja) * | 1994-12-26 | 2003-01-14 | 富士通株式会社 | 半導体装置及びその製造方法 |
US5665633A (en) | 1995-04-06 | 1997-09-09 | Motorola, Inc. | Process for forming a semiconductor device having field isolation |
KR0155874B1 (ko) | 1995-08-31 | 1998-12-01 | 김광호 | 반도체장치의 평탄화방법 및 이를 이용한 소자분리방법 |
US5747380A (en) | 1996-02-26 | 1998-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Robust end-point detection for contact and via etching |
TW341721B (en) * | 1996-03-14 | 1998-10-01 | Matsushita Electric Ind Co Ltd | Formation of flat pattern, flat pattern forming apparatus, and semiconductor integrated circuit device |
US5885856A (en) | 1996-08-21 | 1999-03-23 | Motorola, Inc. | Integrated circuit having a dummy structure and method of making |
JPH10144635A (ja) | 1996-11-11 | 1998-05-29 | Sony Corp | 平坦化研磨における研磨後の段差予測方法およびダミーパターン配置方法 |
US5923563A (en) | 1996-12-20 | 1999-07-13 | International Business Machines Corporation | Variable density fill shape generation |
JP3743120B2 (ja) | 1997-02-21 | 2006-02-08 | ソニー株式会社 | 露光用マスクのマスクパターン設計方法、並びに半導体集積回路の作製方法 |
JP3299486B2 (ja) | 1997-10-08 | 2002-07-08 | 松下電器産業株式会社 | 半導体装置およびその製造方法 |
JP3488606B2 (ja) | 1997-10-22 | 2004-01-19 | 株式会社東芝 | 半導体装置の設計方法 |
US6281049B1 (en) * | 1998-01-14 | 2001-08-28 | Hyundai Electronics Industries Co., Ltd. | Semiconductor device mask and method for forming the same |
US6093631A (en) | 1998-01-15 | 2000-07-25 | International Business Machines Corporation | Dummy patterns for aluminum chemical polishing (CMP) |
US6087733A (en) | 1998-06-12 | 2000-07-11 | Intel Corporation | Sacrificial erosion control features for chemical-mechanical polishing process |
JP2000124305A (ja) | 1998-10-15 | 2000-04-28 | Mitsubishi Electric Corp | 半導体装置 |
US6232161B1 (en) * | 1998-12-15 | 2001-05-15 | United Microelectronics Corp. | Method for forming a dummy active pattern |
US6396158B1 (en) | 1999-06-29 | 2002-05-28 | Motorola Inc. | Semiconductor device and a process for designing a mask |
US6486066B2 (en) * | 2001-02-02 | 2002-11-26 | Matrix Semiconductor, Inc. | Method of generating integrated circuit feature layout for improved chemical mechanical polishing |
-
2001
- 2001-06-04 US US09/873,810 patent/US6611045B2/en not_active Expired - Lifetime
-
2002
- 2002-05-02 EP EP02746331A patent/EP1397829A1/en not_active Withdrawn
- 2002-05-02 JP JP2003502875A patent/JP2004529504A/ja active Pending
- 2002-05-02 WO PCT/US2002/013884 patent/WO2002099865A1/en active Application Filing
- 2002-05-02 KR KR10-2003-7015895A patent/KR20040004690A/ko not_active Application Discontinuation
- 2002-05-02 CN CN028092643A patent/CN100407383C/zh not_active Expired - Fee Related
- 2002-05-08 TW TW091109530A patent/TWI226696B/zh not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022061825A1 (zh) * | 2020-09-27 | 2022-03-31 | 华为技术有限公司 | 硅通孔结构的制备方法和硅通孔结构 |
Also Published As
Publication number | Publication date |
---|---|
US6611045B2 (en) | 2003-08-26 |
CN100407383C (zh) | 2008-07-30 |
JP2004529504A (ja) | 2004-09-24 |
EP1397829A1 (en) | 2004-03-17 |
WO2002099865A1 (en) | 2002-12-12 |
TWI226696B (en) | 2005-01-11 |
KR20040004690A (ko) | 2004-01-13 |
US20020179902A1 (en) | 2002-12-05 |
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Legal Events
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: FREESCALE SEMICONDUCTOR INC. Free format text: FORMER OWNER: MOTOROLA, INC. Effective date: 20041203 |
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C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20041203 Address after: texas Applicant after: Fisical Semiconductor Inc. Address before: Illinois Applicant before: Motorola Inc. |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CP01 | Change in the name or title of a patent holder | ||
CP01 | Change in the name or title of a patent holder |
Address after: texas Patentee after: NXP America Co Ltd Address before: texas Patentee before: Fisical Semiconductor Inc. |
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CF01 | Termination of patent right due to non-payment of annual fee | ||
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Granted publication date: 20080730 Termination date: 20190502 |