CN1518067A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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CN1518067A
CN1518067A CNA200410001554XA CN200410001554A CN1518067A CN 1518067 A CN1518067 A CN 1518067A CN A200410001554X A CNA200410001554X A CN A200410001554XA CN 200410001554 A CN200410001554 A CN 200410001554A CN 1518067 A CN1518067 A CN 1518067A
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conductive part
semiconductor substrate
recess
semiconductor device
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����һ
原一巳
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Seiko Epson Corp
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Abstract

本发明的目的在于形成高质量的穿透电极。在已形成集成电路12的半导体基板10上，从第一面20形成凹部22。在凹部22上设置导电部30。从相反于半导体基板10的第一面20的第二面38上凸出导电部30。磨削或研磨导电部30使其新生面露出为止。

Description

半导体装置的制造方法
技术领域
本发明涉及半导体装置的制造方法。
背景技术
人们正在开发三维安装形态的半导体装置。而且已经知道为了三维安装成为可能，在半导体芯片上形成穿透电极。穿透电极是从半导体芯片凸出形成的。在以往所知道的穿透电极的形成方法中，电连接时的特性优越地形成穿透电极的凸出部分是很困难的。
发明内容
本发明的目的是形成高质量的穿透电极。
(1)本发明涉及的半导体装置的制造方法，包括：(a)形成有集成电路的半导体基板上，从第一面形成凹部；(b)在上述凹部上设置导电部；(c)从相反于上述半导体基板的上述第一面的第二面，凸出上述导电部；以及(d)磨削或研磨上述导电部，使其新生面露出为止的工序。根据本发明，因为露出导电部的新生面，可以形成电连接时的特性优越的穿透电极。
(2)在该半导体装置的制造方法中，也可以在上述(a)工序后、(b)工序前，还包括上述凹部的底面和内壁面上设置绝缘层的工序，在上述(b)工序中，在上述绝缘层的内侧上设置导电部。
(3)在该半导体装置的制造方法中的上述的(c)工序中，也可以被上述绝缘层覆盖的状态，凸出上述导电部，在上述的(d)工序中，磨削或研磨上述绝缘层和上述导电部。
(4)在该半导体装置的制造方法的在上述的(c)工序中，也可以利用对上述半导体基板的蚀刻量多于对上述绝缘层的蚀刻量的蚀刻剂，蚀刻上述半导体基板的第二面的方法，使上述导电部凸出于上述第二面。
(5)在该半导体装置的制造方法中，也可以上述半导体基板是半导体集成电路基板，还包括形成多个上述集成电路，分别对应于上述集成电路，形成上述凹部之后切断上述半导体基板的工序。
(6)在该半导体装置的制造方法中，还包括迭加结束上述(a)～(d)工序的多个上述半导体基板，并通过上述导电部，谋求电连接的工序，也是可以的。
附图说明
图1A～图1D是说明本发明实施方式的半导体装置制造方法的图。
图2A～图2D是说明本发明实施方式的半导体装置制造方法的图。
图3A～图2C是说明本发明实施方式的半导体装置制造方法的图。
图4是说明本发明实施方式的半导体装置制造方法的图。
图5是说明本发明实施方式的半导体装置制造方法的图。
图6是说明本发明实施方式的半导体装置制造方法的图。
图7是说明本发明实施方式的半导体装置的图。
图8是说明本发明实施方式的电路基板的图。
图9是说明本发明实施方式的电子器械的图。
图10是说明本发明实施方式的电子器械的图。
发明的具体实施方式
下面，结合附图说明本发明的实施方式。
图1A～图3C是说明采用本发明的实施方式的半导体装置的制造方法的图。本实施方式中，使用半导体基板10。图1A所示的半导体基板10是半导体集成电路基板，也可以是半导体芯片。在半导体基板10上至少形成有一个(在半导体集成电路基板上有多个，而在半导体芯片上有一个)集成电路(例如有晶体管或存储器的电路)。在半导体基板10上形成有多个电极(例如衬垫)14。每一个电极14电连接在集成电路12上。每一个电极14也可以是用铝形成。电极14的表面形状没有特定的限制，但矩形的多。半导体基板10为半导体集成电路基板时，在成为多个半导体芯片的每一个区域上，形成两个以上的(一组)电极14。
在半导体基板10上形成一层或其以上的钝化膜16、18。钝化膜16、18可以由SiO2、SiN、聚酰亚胺树脂等来形成。在图1A所示的例中，在钝化膜16上形成有连接电极14、集成电路12和电极的配线(图中未示)。另外，另一个钝化膜18至少避开电极14的表面的一部分而形成。钝化膜18覆盖电极14的表面而形成之后，蚀刻其一部分而露出电极14的一部分，也是可以的。蚀刻的方法，可以采用干式蚀刻法或湿式蚀刻法。在蚀刻钝化膜18时，也可以蚀刻电极14的表面。
在本实施方式中，半导体基板10上，在其第一面20形成凹部22(参照图1C)。第一面20是形成电极14的一侧(形成集成电路12的一侧)的面。凹部22是避开集成电路12的元件和配线而形成。如图1B所示，也可以在电极14上形成通孔24。通孔24的形成中也可以采用蚀刻法(干式蚀刻法或湿式蚀刻法)。也可以利用平板印刷工序来形成图案的抗蚀层(未图示)之后，进行蚀刻。在电极14的下面，已经形成钝化膜16时，在这上也形成通孔26(参照图1C)。由于钝化膜16，对电极14的蚀刻被停止时，为了形成通孔26，也可以利用别的蚀刻剂来替代用于电极14时所使用的蚀刻剂。此时，也可以再度利用平板印刷工序来形成图案的保护层(图中未示)。
如图1C所示，为了与通孔24(和通孔26)连通，在半导体基板10形成凹部22。通孔24(和通孔26)和凹部22合在一起形成凹部22，也是可以的。也可以采用蚀刻法(干式蚀刻法或湿式蚀刻法)形成凹部22。利用平板印刷工序来形成图案的抗蚀层(图中未示)之后，进行蚀刻，也是可以的。或也可以利用激光(例如CO2激光、YAG激光等)来形成凹部22。激光也可以适用于通孔24、26的形成。也可以利用一种类的蚀刻或激光来连续形成凹部22和通孔24、26。也可以应用喷砂加工来形成凹部22。
如图1D所示，也可以在凹部22的内侧上形成绝缘层28。绝缘层28可以是氧化膜。例如，半导体基板10的基本材质为Si时，绝缘层28也可以是SiO2，也可以是SiN。绝缘层28形成在凹部22的底面。但是，绝缘层28不填埋凹部22。即，由绝缘层28来形成凹部22。绝缘层28也可以形成在钝化膜16的通孔26的内壁面。绝缘层28也可以形成在钝化膜18上。
绝缘层28也可以形成在电极14的通孔24的内壁面。绝缘层28避开电极14的一部分(例如其上表面)而形成。覆盖电极14的全表面而形成绝缘层28之后，蚀刻(干式蚀刻法或湿式蚀刻法)其一部分而露出电极14的一部分，也是可以的。也可以利用平板印刷工序来形成图案的抗蚀层(图中未示)之后，进行蚀刻。
接着，在凹部22(例如绝缘层28的内侧)上设置导电部30(参照图2B)。导电部30可以是用Cu或W来形成。如图2A所示，也可以在形成导电部30的外层部32之后，形成其中心部34。中心部34可以利用Cu、W或掺杂多晶硅(例如低温多晶硅)中的任一种来形成。外层部32可以是至少包含阻挡层。阻挡层是防止中心部34或下面要说明的种子层的材料扩散在半导体基板10(例如Si)的层。阻挡层可以利用不同于中心部34的材料(例如TiW、TiN)来形成。利用电解电镀方法形成中心部34时，外层部32也可以包含种子层。形成阻挡层之后，形成种子层。种子层是相同于中心部34的材料(例如Cu)来形成。另外，导电部30(至少其中心部34)也可以利用无电解电镀或喷墨方式来形成。
如图2B所示，在钝化膜18上也形成外层部32时，如图2C所示，蚀刻外层部32的钝化膜18上的部分。形成外层部32之后，形成中心部34的方法来可以设置导电部30。导电部30的一部分位于半导体基板10的凹部22内。因为凹部22的内壁面与导电部30之间介入绝缘层28，所以两者的电连接被切断。导电部30电连接在电极14。例如，在电极14露出于绝缘层28的部分，可以连接导电部30。导电部30的一部分可以位于钝化膜18上。导电部30也可以只设在电极14的区域内。导电部30也可以至少凸出于凹部22上方。例如，也可以导电部30凸出于钝化膜18。
另外，作为变形例，在钝化膜18上留下外层部32的状态，形成中心部34，也是可以的。此时，因为连接在中心部34的层也形成在钝化膜18的上方，所以蚀刻此层。
如图2D所示，也可以在导电部30上面设置焊料36。焊料36可以利用焊锡来形成，形成软焊料或硬焊料，均可以。利用抗蚀层来覆盖导电部30以外的区域来形成焊料36，也是可以的。通过以上的工序，由导电部30或在加上焊料36而可以形成缓冲块(bump)。
如图3A所示，在本实施方式中，至少利用例如机械研磨·磨削、或化学研磨·磨削之一的方法，也可以削去半导体基板10的第二面(相反于第一面20的面)38。形成在凹部22的绝缘层28被露出之前为止，进行该工序。另外，省略图3A所示的工序，进行下面的图3B所示的工序，也是可以的。
如图3B所示，使导电部30凸出于第二面38。例如，蚀刻半导体基板10的第二面38，以露出绝缘层28，。详细地，蚀刻半导体基板10的第二面38，以便导电部30(具体来说是其凹部22内部分)被绝缘层28覆盖的状态下凸出。对半导体基板10(例如Si为基本材质)蚀刻量多于对绝缘层28(例如SiO2来形成的)性质的蚀刻剂来进行蚀刻，也是可以的。蚀刻剂可以是SF6或CF4或Cl2气体。可以使用干式蚀刻装置来进行蚀刻。或是，氟酸和硝酸的混合液或氟酸、硝酸和醋酸的混合液，也是可以的。
如图3C所示，磨削或研磨导电部30，使其新生面(只是由构成材料形成的面即除去氧化膜或被沉积的有机物的面)露出为止。磨削可以使用磨石。例如，可以使用100#～4000#程度粒度的磨石，但如果使用1000#～4000#程度粒度的磨石，可以防止绝缘层28的破损。研磨中可以使用研磨布。研磨布可以是绒面型或泡沫聚氨酯类，也可以是无纺布。在Na、NH4等的碱性阳离子溶液中作为研磨粒子分散胶态硅石的浆料，可以使用于研磨。研磨粒子具有0.03μm～10μm程度的直径，重量比率10％程度来分散。浆料也可以包含螯合剂、氨、双氧水等的添加剂。研磨压力可以是5g/cm2～1kg/cm2程度。
在凹部22上已形成绝缘层28时，比导电部30先研磨或磨削绝缘层28。也可以连续进行绝缘层28研磨或磨削和导电部30的研磨或磨削。至少去除形成在凹部22底面的绝缘层28部分。这样，露出导电部30，还露出其新生面。露出导电部30的新生面而使导电部30的前端部的外周面覆盖在绝缘层28，也是可以的。也可以使导电部30的中心部34的新生面不露出的样子露出外层部32(例如阻挡层)的新生面，也可以露出外层部32和中心部34的新生面。
另外，在半导体基板10的第一面20的一侧设置例如玻璃板、树脂层、树脂带等的加强部件(例如粘接剂或粘接板来粘接)之后，可以进行图3A～3C的至少任一个工序。
利用以上的工序，可以使导电部30凸出于半导体基板10的第二面38。凸出的导电部30成为凸起电极。导电部30也成为第一面20和第二面38的穿透电极。根据本实施方式，因为露出导电部30的新生面，可以形成电连接时的特性优越的穿透电极。另外，也可以在新生面被氧化之前(例如露出新生面之后马上或尽可能地早(例如24小时之内))，电连接导电部30。通过以上的工序可以制造半导体装置(具有穿透电极的半导体基板)，其结构是由上述的制造方法可以导致的内容。
如图4所示，也可以半导体基板10为半导体集成电路基板时，对应于各自的集成电路12(参照图1A)形成凹部22之后，切断(切割)半导体基板10。切断可以使用切割机(切丁机)40或激光(例如CO2激光、YAG激光)。由此，可以制造半导体装置(具有穿透电极的半导体芯片)，其结构是由上述的制造方法可以导致的内容。
半导体装置的制造方法可以包括：迭加具有上述的导电部30的多个半导体基板10，通过导电部30电连接各自的半导体基板10的工序。具体地，可以电连接上、下导电部30，也可以连接导电部30和电极14。电连接可以采用焊锡或金属接合，也可以使用各向异性导电材料(各向异性导电膜或各向异性导电膏)，也可以适用利用绝缘性粘接剂的收缩力的压接，也可以组合利用这些。
也可以迭加作为半导体芯片的半导体基板10。或如图5所示，也可以迭加作为半导体集成电路基板的多个半导体基板10。此时，也可以切断迭加的多个半导体基板10。或者，如图6所示，也可以在作为半导体集成电路基板的半导体基板10上，迭加上述的、从半导体基板10切断的半导体芯片50。此时，也可以迭加多个半导体芯片50。
图7是表示本发明实施方式的半导体装置(迭加型半导体装置)的图。迭加型半导体装置具有：多个从上述的半导体基板10切断的半导体芯片50。多个的半导体芯片50是迭加的。可以用焊料36来接合上、下导电部30之间或导电部30和电极14。也可以在迭加的多个半导体芯片50中的一个(例如第二面38方向的最外侧的半导体芯片50)上迭加没有穿透电极的半导体芯片60。半导体芯片60的内容除了没有穿透电极以外，其他相当于半导体芯片50。半导体芯片50的导电部30，也可以接合在半导体芯片60的电极64。
也可以在上、下半导体芯片50之间或上、下半导体芯片60、50之间设置绝缘材料(例如粘接剂·树脂·未充满材料)66。利用绝缘材料66维持或加强导电部30的接合状态。
迭加的多个半导体芯片50可以安装在配线(电路)基板70上。迭加的多个半导体芯片50中的最外侧的半导体芯片50也可以安装在配线基板(例如附加极)70。其安装上，可以采用倒装焊接法。此时，第一面20的方向上具有最外侧(例如最下面)的导电部30的半导体芯片50安装在配线基板70。例如，可以在配线模72上电连接(例如接合)从导电部30的第一面20的凸出部或电极14。半导体芯片50和配线基板70之间设置绝缘材料(例如粘接剂·树脂·不满材料)66，也是可以的。利用绝缘材料66维持或加强导电部30或电极14的接合状态。
或者，作为没有图示的例子，也可以采用正焊法(face up bonding)把迭加的半导体芯片50安装在配线基板70。此时，在配线模72上电连接(接合)导电部30的第二面38的凸出部。配线基板70上，设有电连接在配线模72的外部接头(例如焊锡柱)74。或在半导体芯片50上，形成应力缓和层，在其上面，从电极14形成配线模，在其上面，形成外部接头，也是可以的。其他的内容可以从上述的制造方法来导致。
图8是表示：装有多个半导体芯片迭加而成的半导体装置1的电路基板1000。用上述的导电部30来电连接多个半导体芯片。作为具有上述的半导体装置的电子器械，图9中表示笔记本型个人电脑2000、图10中表示手机3000。
本发明不限于上述的实施方式，可以有种种变形。例如，本发明包括：实质上和实施方式中所说明的构成相同的构成(例如功能、方法和结果相同的构成或目的和结果相同的构成)。另外，本发明还包括：转换实施方式中所说明构成中的不是本质性的部分。另外，本发明还包括：可以达到实施方式中所说明的构成相同效果或相同目的的构成。另外，本发明还包括：在本实施方式中所说明的构成上附加已知的技术。

Claims (6)

1、一种半导体装置的制造方法，其中包括：(a)形成有集成电路的半导体基板上，从第一面形成凹部；(b)在上述凹部上设置导电部；(c)从相反于上述半导体基板的上述第一面的第二面上凸出上述导电部；以及，(d)磨削或研磨上述导电部，使其新生面露出为止的工序。
2、根据权利要求1所述的半导体装置的制造方法，其特征在于：在上述(a)工序后、(b)工序前，还包括在上述凹部的底面和内壁面上设置绝缘层的工序，在上述(b)工序中，在上述绝缘层的内侧设置导电部。
3、根据权利要求2所述的半导体装置的制造方法，其特征在于：在上述的(c)工序中，被上述绝缘层覆盖的状态，使上述导电部凸出，在上述的(d)工序中，磨削或研磨上述的绝缘层和上述的导电部。
4、权利要求3所述的半导体装置的制造方法，其特征在于：在上述的(c)工序中，利用对上述半导体基板的蚀刻量多于对上述绝缘层的蚀刻量的蚀刻剂，进行上述半导体基板的第二面的蚀刻的方法，使上述导电部凸出于上述第二面。
5、根据权利要求1至4的任意1项中所述的半导体装置的制造方法，其特征在于：上述的半导体基板是半导体集成电路基板，还包括形成多个上述集成电路，分别对应上述集成电路形成上述凹部，切断上述半导体基板的工序。
6、一种半导体装置的制造方法，其特征在于：包括(a)形成有集成电路的半导体基板上，从第一面形成凹部；(b)在上述凹部上设置导电部；(c)从相反于上述半导体基板上述第一面的第二面，凸出上述导电部；以及，(d)磨削或研磨上述导电部，使其新生面露出为止和迭加结束上述(a)～(d)工序的多个上述半导体基板，并通过上述导电部谋求电连接的工序。
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