CN1525552A - 制造高压双栅装置的方法 - Google Patents
制造高压双栅装置的方法 Download PDFInfo
- Publication number
- CN1525552A CN1525552A CNA2004100072148A CN200410007214A CN1525552A CN 1525552 A CN1525552 A CN 1525552A CN A2004100072148 A CNA2004100072148 A CN A2004100072148A CN 200410007214 A CN200410007214 A CN 200410007214A CN 1525552 A CN1525552 A CN 1525552A
- Authority
- CN
- China
- Prior art keywords
- high voltage
- pressure
- film
- forming
- gate oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
Abstract
一种制造高压双栅装置的方法,其藉由在形成一氮化物膜的选择性蚀刻制造工艺之后形成一高压氧化物膜,可限制损坏器件隔离层。该方法包括:在一具有一低压装置形成区及一高压装置形成区的半导体基板的该高压装置形成区中,形成高压n型阱区及高压p型阱区;在所述阱区中形成一高压NMOS晶体管的源极/漏极以及一高压PMOS晶体管的源极/漏极;藉由STI形成在一器件隔离层中形成一器件隔离层,并且在该整个表面上形成一缓冲氮化物膜;在该缓冲氮化物膜上形成一高压栅氧化物膜,并且仅在该高压装置形成区中保留该高压栅氧化物膜;以及在该低压装置形成区中形成低压n型阱区及低压p型阱区,并且在所述表面上形成一低压栅氧化物膜。
Description
技术领域
本发明涉及一种制造半导体装置的方法,具体而言,本发明涉及一种制造高压双栅装置的方法,该方法藉由在形成一氮化物膜的选择性蚀刻制造工艺之后形成一高压氧化物膜,该高压双栅装置就可抑制损坏器件隔离层。
背景技术
如LDI(LCD驱动器IC)产品等电力装置产品需要用于驱动一逻辑电路的低压(LV)操作,以及在驱动一装置后用于驱动一LCD的高压(HV)操作。因此,应制作一双栅结构的栅氧化物膜,另外,随着细线幅度的趋势,因而必然采用沟槽隔离(trench isolation;TI)制造工艺。
然而,如果直接调整双栅氧化物制造程序来配合TI制造工艺所形成的STI结构,则在形成适用于HV的双栅氧化物膜之后,会发生LV区域的过度STI凹处,因而造成损坏装置特性。
其原因如下:用于STI结构间隙填满的涂覆材料为如USG或HDP等CVD氧化物膜,而热氧化物膜材料的涂覆材料则是当做栅氧化物膜。因此,在形成热氧化物膜的双氧化物膜后,就会由于介于该热氧化物膜与该CVD氧化物膜之间的湿式蚀刻速率不同而导致在一有源区与一场区之间产生严重塌陷。
下文中将参考附图来说明先前技术的高压双栅装置。
图1显示现有高压双栅装置结构的断面图。
如图所示,可得知由于介于HV有源区的氮化物与STI上的氮化物之间的厚度不同,造成干式蚀刻制造工艺中的HV氮化物蚀刻不足以彻底去除该有源区的氮化物。
这会导致损坏STI上的HDP氧化物膜,并且由于蚀刻选择性而影响沟槽边角的硅。
另外,当藉由湿式蚀刻来去除氮化物时,由于H3PO4及HDP的蚀刻选择率约为1,所以氧化物膜凹处仍然会发生,并且会损失逻辑区中的氮化物。
然而,先前技术的高压双栅装置有如下的问题。
在蚀刻高压装置区中的氮化物后,会由于介于有源区中的氮化物与STI上的氮化物之间的厚度不同,而导致损失STI上的HDP氧化物膜,并且因蚀刻选择性而影响沟槽边角的硅。
另外,在藉由湿式蚀刻来去除氮化物后,场氧化物膜凹处仍然会发生,并且会损失逻辑区中的氮化物。
发明内容
本发明的设计考虑到先前技术的问题,因此本发明的目的是提供一种制造高压双栅装置的方法,该方法藉由在形成一氮化物膜的选择性蚀刻制造工艺之后形成一高压氧化物膜,该高压双栅装置就可抑制损坏器件隔离层。
为了达到上文所述的目的,本发明提供一种根据本发明制造高压双栅装置的方法,包括下列步骤:在一具有一低压装置形成区及一高压装置形成区的半导体基板的该高压装置形成区中,形成高压n型阱区及高压p型阱区;在所述阱区中形成一高压NMOS晶体管的源极/漏极以及一高压PMOS晶体管的源极/漏极;藉由STI形成在一器件隔离层中形成一器件隔离层,并且在该整个表面上形成一缓冲氮化物膜;在该缓冲氮化物膜上形成一高压栅氧化物膜,并且仅在该高压装置形成区中保留该高压栅氧化物膜;以及在该低压装置形成区中形成低压n型阱区及低压p型阱区,并且在所述表面上形成一低压栅氧化物膜。
附图说明
从前文中参考附图的具体实施例详细说明,将可明白本发明的其它目的及观点,其中:
图1显示先前技术的高压双栅装置结构的断面图;以及
图2a到2p显示根据本发明的制造高压双栅装置制造工艺的断面图。
附图符号说明
21 半导体基板
22 缓冲氧化物膜
23 氮化物膜
24 高压n型阱区
25 高压p型阱区
26 高压NMOS晶体管的源极/漏极区
27 高压PMOS晶体管的源极/漏极区
28 第二缓冲氧化物膜
29 平坦化停止层
30 高密度等离子体(HDP)氧化物膜
31 器件隔离层
32 缓冲氮化物
33 高压栅氧化物膜
34 低压n型阱区
35 低压p型阱区
36 低压栅氧化物膜
37 装置驱动栅多硅层
PR1,PR2,PR3,PR4,PR5,PR6,PR7,PR8光致抗蚀剂图案
具体实施方式
下文中将参考附图来详细说明本发明的优选具体实施例。
图2a到2p显示根据本发明的制造高压双栅装置制造工艺的断面图。
在本发明中,为了防止在蚀刻氮化物过程中发生有源区损失,因而形成一薄氮化物膜,选择性蚀刻该薄氮化物膜,接着形成一高压栅氧化物膜,藉以抑制发生损失的场部分。
首先,如图2a所示,在一半导体基板21上形成一第一缓冲氧化物膜22。
接着如图2b所示,形成一氮化物膜23,使用一光致抗蚀剂图案PR1来界定一高压n型阱区,并且进行离子注入工艺。
接着如图2c所示,使用一光致抗蚀剂图案PR2来界定一高压p型阱区,接着进行离子注入工艺。
并且,如图2d所示,藉由置入(drive-in)扩散制造工艺来形成一高压n型阱区24及一高压p型阱区25。
接着,形成一光致抗蚀剂图案PR3,然后进行用于形成一高压NMOS晶体管的源极/漏极的离子注入工艺。
继续如图2e所示,形成一光致抗蚀剂图案PR4,然后进行用于形成一高压PMOS晶体管的源极/漏极的离子注入工艺。
接着如图2f所示,藉由退火处理使离子注入的源极和漏极置入扩散,以形成该高压NMOS晶体管的源极/漏极区26以及该高压PMOS晶体管的源极/漏极区27。
继续藉由湿式蚀刻来去除该缓冲氧化物膜22,形成一第二缓冲氧化物膜28,并且在该形成的氧化物膜上沉积约1000的氮化物,以便在CMP制造工艺中当做一平坦化停止层29。
接着如图2g所示,使用一光致抗蚀剂图案PR5来形成用于器件隔离的沟槽,其中,STI区已经开口。
继续如图2h所示,在包含该沟槽的整个表面上沉积一高密度等离子体(HDP)氧化物膜30。
接着如图2i所示,藉由CMP去除及平坦化该高密度等离子体(HDP)氧化物膜30及该平坦化停止层29,以形成一器件隔离层31,接着藉由湿式蚀刻来去除残余氮化物。
继续如图2j所示,沉积一厚度小于300的缓冲氮化物32。
接着如图2k所示,在该缓冲氮化物32的整个表面上沉积一厚度为1000的高压栅氧化物膜33。
继续如图2l所示,使用一低压晶体管形成区形成有开口的光致抗蚀剂图案PR6来去除一低压晶体管形成区中的该缓冲氮化物32及该高压栅氧化物膜33。
接着如图2m所示,使用一光致抗蚀剂图案PR7来进行离子注入工艺,以形成一低压n型阱区34。
接着如图2n所示,使用一光致抗蚀剂图案PR8来进行离子注入工艺,以形成一低压p型阱区35。
接着如图2o所示,将Vt控制离子注入该低压晶体管形成区,接着形成一低压栅氧化物膜36。
继续如图2p所示,沉积并且接着选择性图案化一装置驱动栅多硅层37,以形成栅电极。
已参考特定具体实施例并配合特定应用程序来说明本发明。熟知技艺以及使用本发明讲授的人士应明白属于本发明范畴内的额外修改及应用。因此,随附申请专利范围预计涵盖属于本发明范畴内的任何及所有此类应用、修改及具体实施例。
如上文所述的制造高压双栅装置的方法具有下列优点。
本发明可藉由形成一薄氮化物膜来限制器件隔离层的损失,以便防止在蚀刻该氮化物过程中发生有源区损失。
即,在选择性蚀刻该氮化物膜后,会形成该高压栅氧化物膜,以便抑制该器件隔离层损失,藉以改良装置操作特性并且增加装置可靠性。
Claims (3)
1.一种制造一高压双栅装置的方法,包括下列步骤:
在一具有一低压装置形成区及一高压装置形成区的半导体基板的该高压装置形成区中,形成高压n型阱区及高压p型阱区;
在所述阱区中形成一高压NMOS晶体管的源极/漏极以及一高压PMOS晶体管的源极/漏极;
藉由浅沟槽隔离工艺形成一器件隔离层,并且在该整个表面上形成一缓冲氮化物膜;
在该缓冲氮化物膜上形成一高压栅氧化物膜,并且仅在该高压装置形成区中保留该高压栅氧化物膜;以及
在该低压装置形成区中形成低压n型阱区及低压p型阱区,并且在所述表面上形成一低压栅氧化物膜。
2.如权利要求1所述的方法,其中在图案化该高压栅氧化物膜的步骤中,藉由该缓冲氮化物膜来封锁该器件隔离层。
3.如权利要求1所述的方法,其中藉由沉积一高密度等离子体氧化物膜并且接着藉由CMP将该高密度等离子体氧化物膜平坦化,来形成该器件隔离层。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0012403A KR100460272B1 (ko) | 2003-02-27 | 2003-02-27 | 고전압 듀얼 게이트 소자의 형성 방법 |
KR12403/2003 | 2003-02-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN1525552A true CN1525552A (zh) | 2004-09-01 |
Family
ID=32906561
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA2004100072148A Pending CN1525552A (zh) | 2003-02-27 | 2004-02-27 | 制造高压双栅装置的方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6927114B2 (zh) |
JP (1) | JP4738750B2 (zh) |
KR (1) | KR100460272B1 (zh) |
CN (1) | CN1525552A (zh) |
TW (1) | TWI340408B (zh) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100416780C (zh) * | 2005-06-03 | 2008-09-03 | 联华电子股份有限公司 | 高压金属氧化物半导体晶体管元件及其制造方法 |
US7842577B2 (en) | 2008-05-27 | 2010-11-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Two-step STI formation process |
CN102110655A (zh) * | 2009-12-24 | 2011-06-29 | 上海华虹Nec电子有限公司 | Eeprom器件的制作方法 |
CN101030556B (zh) * | 2006-03-01 | 2012-04-04 | 瑞萨电子株式会社 | 半导体器件的制造方法 |
US8502316B2 (en) | 2010-02-11 | 2013-08-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned two-step STI formation through dummy poly removal |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7205201B2 (en) * | 2004-08-09 | 2007-04-17 | System General Corp. | CMOS compatible process with different-voltage devices |
CN100428443C (zh) * | 2005-08-05 | 2008-10-22 | 联华电子股份有限公司 | 一种降低晶片电荷伤害的方法 |
KR100760924B1 (ko) * | 2006-09-13 | 2007-09-21 | 동부일렉트로닉스 주식회사 | 반도체 소자 형성방법 |
KR100847837B1 (ko) * | 2006-12-29 | 2008-07-23 | 동부일렉트로닉스 주식회사 | 디모스 소자 및 그 제조 방법 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4978628A (en) * | 1986-11-19 | 1990-12-18 | Teledyne Industries, Inc. | Drail-well/extension high voltage MOS transistor structure and method of fabrication |
US6249030B1 (en) * | 1992-12-07 | 2001-06-19 | Hyundai Electronics Industries Co., Ltd. | BI-CMOS integrated circuit |
US5369052A (en) * | 1993-12-06 | 1994-11-29 | Motorola, Inc. | Method of forming dual field oxide isolation |
JPH07183409A (ja) * | 1993-12-24 | 1995-07-21 | Seiko Epson Corp | 半導体装置とその製造方法 |
US5861347A (en) * | 1997-07-03 | 1999-01-19 | Motorola Inc. | Method for forming a high voltage gate dielectric for use in integrated circuit |
EP0986100B1 (en) * | 1998-09-11 | 2010-05-19 | STMicroelectronics Srl | Electronic device comprising EEPROM memory cells, HV transistors, and LV transistors with silicided junctions, as well as manufacturing method thereof |
KR100281908B1 (ko) * | 1998-11-20 | 2001-02-15 | 김덕중 | 반도체소자 및 그 제조방법 |
US6399448B1 (en) * | 1999-11-19 | 2002-06-04 | Chartered Semiconductor Manufacturing Ltd. | Method for forming dual gate oxide |
KR100364599B1 (ko) * | 2001-02-13 | 2002-12-16 | 삼성전자 주식회사 | 반도체 소자 제조방법 |
JP2002170888A (ja) * | 2000-11-30 | 2002-06-14 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2003031679A (ja) * | 2001-07-13 | 2003-01-31 | Umc Japan | 半導体装置の製造方法 |
KR100387531B1 (ko) * | 2001-07-30 | 2003-06-18 | 삼성전자주식회사 | 반도체소자 제조방법 |
-
2003
- 2003-02-27 KR KR10-2003-0012403A patent/KR100460272B1/ko active IP Right Grant
-
2004
- 2004-02-24 US US10/785,493 patent/US6927114B2/en not_active Expired - Lifetime
- 2004-02-24 JP JP2004047298A patent/JP4738750B2/ja not_active Expired - Lifetime
- 2004-02-27 CN CNA2004100072148A patent/CN1525552A/zh active Pending
- 2004-02-27 TW TW093105171A patent/TWI340408B/zh active
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100416780C (zh) * | 2005-06-03 | 2008-09-03 | 联华电子股份有限公司 | 高压金属氧化物半导体晶体管元件及其制造方法 |
CN101030556B (zh) * | 2006-03-01 | 2012-04-04 | 瑞萨电子株式会社 | 半导体器件的制造方法 |
US7842577B2 (en) | 2008-05-27 | 2010-11-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Two-step STI formation process |
CN101593718B (zh) * | 2008-05-27 | 2011-09-07 | 台湾积体电路制造股份有限公司 | 形成集成电路结构的方法 |
US8338909B2 (en) | 2008-05-27 | 2012-12-25 | Taiwan Semiconductor Manufactuirng Company, Ltd. | Two-Step STI formation process |
CN102110655A (zh) * | 2009-12-24 | 2011-06-29 | 上海华虹Nec电子有限公司 | Eeprom器件的制作方法 |
CN102110655B (zh) * | 2009-12-24 | 2013-09-11 | 上海华虹Nec电子有限公司 | Eeprom器件的制作方法 |
US8502316B2 (en) | 2010-02-11 | 2013-08-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned two-step STI formation through dummy poly removal |
Also Published As
Publication number | Publication date |
---|---|
TWI340408B (en) | 2011-04-11 |
KR100460272B1 (ko) | 2004-12-08 |
US20040171197A1 (en) | 2004-09-02 |
US6927114B2 (en) | 2005-08-09 |
TW200423236A (en) | 2004-11-01 |
KR20040077026A (ko) | 2004-09-04 |
JP2004260179A (ja) | 2004-09-16 |
JP4738750B2 (ja) | 2011-08-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1263119C (zh) | 用于生产cmos器件的方法 | |
CN100505263C (zh) | 半导体结构及其形成方法 | |
CN1828908A (zh) | 半导体结构及制造半导体结构的方法 | |
CN100477148C (zh) | 制造半导体器件的器件隔离膜的方法 | |
CN1714451A (zh) | 双晶体管或非器件 | |
CN1525552A (zh) | 制造高压双栅装置的方法 | |
CN1199256C (zh) | 利用绝缘衬垫防止窄器件中的阈值电压的滚降 | |
CN1622310A (zh) | 具有沟道隔离结构的半导体装置及其制造方法 | |
CN1096114C (zh) | 具有双栅极半导体器件的制造方法 | |
CN1457087A (zh) | 半导体元件的接触孔的形成方法 | |
CN1527374A (zh) | 半导体组件的制造方法 | |
KR20050048114A (ko) | 플래쉬 메모리 소자의 제조 방법 | |
CN101894799A (zh) | 提高nmos晶体管电子迁移率的方法 | |
CN1523675A (zh) | 半导体器件及其制造方法 | |
CN1705086A (zh) | 用于制造具有多栅氧化膜的半导体器件的方法 | |
KR100717503B1 (ko) | 반도체 소자 및 그 제조 방법 | |
KR101100752B1 (ko) | 반도체 소자의 제조 방법 | |
KR100944587B1 (ko) | 반도체 소자의 제조 방법 | |
KR100959241B1 (ko) | 반도체 소자의 제조 방법 | |
CN1917173A (zh) | 栅介电层的制造方法 | |
Liu et al. | High-performance CMOS with oxidation-planarized twin tubs and one-mask sealed diffusion-junctions | |
CN1440067A (zh) | 一种后浅槽隔离工艺方法 | |
KR20040002003A (ko) | 반도체 소자의 제조방법 | |
CN1753165A (zh) | 一种集成电路的制作方法及结构 | |
CN1992347A (zh) | 高压半导体器件及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
AD01 | Patent right deemed abandoned | ||
C20 | Patent right or utility model deemed to be abandoned or is abandoned |