CN1535472A - 在绝缘体上的外延半导体结构和器件 - Google Patents

在绝缘体上的外延半导体结构和器件 Download PDF

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CN1535472A
CN1535472A CNA028146921A CN02814692A CN1535472A CN 1535472 A CN1535472 A CN 1535472A CN A028146921 A CNA028146921 A CN A028146921A CN 02814692 A CN02814692 A CN 02814692A CN 1535472 A CN1535472 A CN 1535472A
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库尔特·W·艾森贝塞尔
3
俞志毅
拉万德拦那斯·德鲁帕德
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Abstract

通过形成用于生长单晶层的柔性衬底，在例如大尺寸硅晶片的单晶衬底(22)上面生长高质量外延单晶材料层(26)。调节缓冲层(24)包括通过氧化硅的非晶界面层(28)与硅晶片(22)隔开的单晶氧化层。非晶界面层释放应力并允许生长高质量单晶氧化物调节缓冲层。调节缓冲层与下面的硅晶片和上面的单晶材料层都晶格匹配。接着在调节缓冲层上形成单晶层(26)，以使单晶层的晶格常数基本上与随后生长的单晶膜的晶格常数相匹配。

Description

在绝缘体上的外延半导体结构和器件
发明领域
本发明一般涉及半导体结构和器件及其制造方法，尤其涉及在绝缘体上的半导体(SOI)结构和器件以及SOI结构、器件和集成电路的制造和使用，该SOI结构、器件和集成电路包括由半导体材料和/或例如金属和非金属的其它类型材料构成的单晶材料层。
技术背景
半导体器件通常包括多层导电、绝缘和半导体层。通常，层的结晶度改善了这些层的所需性质。例如，随着层结晶度的提高，改善了半导体层的电子迁移率和带隙。同样，随着这些层结晶度的提高，改善了导电层的自由电子浓度和绝缘或介质膜的电子电荷位移矢量和电子能可恢复性。
多年来，曾尝试在异质衬底(例如硅(Si))上生长各种单一薄膜。但是，为了获得各种单一层的最佳特性，需要高结晶质量单晶膜。例如，曾尝试在例如锗、硅和各种绝缘体的衬底上生长各种单晶层。因为在结晶核和生长晶体之间的晶格失配导致单晶材料的最终层是低结晶质量的，这些尝试一般都没有成功。
如果可低成本地得到高质量单晶材料的大面积薄膜，那么同由半导体材料的体晶片开始或在半导体材料体晶片上这种材料的外延膜中制造这些器件的成本相比，可以以低成本在该膜中或使用该膜有利地制造许多半导体器件。此外，如果可以从例如硅晶片的体晶片开始实现高质量单晶材料薄膜，那么可以获得利用硅和高质量单晶材料的最佳性质的集成器件结构。
因此，需要一种在另一单晶材料上提供高质量单晶膜或层的半导体结构和制造该结构的工艺。也就是说，需要提供对高质量单晶材料层是柔性的单晶衬底的形成，以获得用于形成具有与在下面的衬底相同晶向的生长单晶膜的高质量半导体结构、器件和集成电路的真正二维生长。该单晶材料层由半导体材料以及例如金属和非金属的其它类型材料构成。
附图说明
通过附图中的实例说明本发明，且不限制本发明，其中相同的标号代表相同的元件，其中：
图1、2和3以剖面图示意性说明按照本发明的各个实施例的器件结构；
图4图解说明最大可得膜厚度和结晶核和生长晶体表层之间晶格失配之间的关系；
图5-7以剖面图示意性说明形成按照本发明器件结构的另一实施例；
图8以剖面图示意说明形成按照本发明一个实施例的单片集成电路；和
图9以剖面图示意说明按照本发明的另一实施例的单片集成电路。
本领域技术人员可以理解，为了简化和清晰，在附图中的元件仅是说明性的，其无需按比例示出。例如，在附图中某些元件的尺寸相对于另一些元件可以放大以有助于提高对本发明实施例的理解。
具体实施方式
图1以剖面图示意性说明按照本发明实施例的部分半导体结构20。半导体结构20包括单晶衬底22、含单晶材料的调节缓冲层24和单晶材料层26。在本文中，术语“单晶”具有半导体工业内通用的含义。该术语应指单一晶体或基本上为单一晶体的材料，并应包括具有较低数量缺陷(例如位错等)的那些材料，这些缺陷在半导体工业中常见的硅或锗、或硅和锗的混合衬底以及这些材料的外延层中是常见的。
按照本发明的一个实施例，结构20还包括位于衬底22和调节缓冲层24之间的非晶中间层28。结构20还包括在调节缓冲层和单晶材料层26之间的模板(template)层30。以下将详尽说明模板层有助于促使单晶材料层在调节缓冲层上生长。非晶中间层有助于释放调节缓冲层中的应力，通过这样做来帮助高结晶质量调节缓冲层的生长。
按照本发明的实施例，衬底22是单晶半导体晶片，优选是大直径的。例如晶片可以是周期表IV族的材料。IV族半导体材料的实例包括硅、锗、混合硅和锗、混合硅和碳、混合硅、锗和碳等。优选地，衬底22是包含硅或锗的晶片，最好是用在半导体工业中的高质量单晶硅晶片。调节缓冲层24优选是在下面衬底上外延生长的单晶氧化物或氮化物材料。按照本发明的一个实施例，在层24生长期间，通过氧化衬底22，在衬底22和生长的调节缓冲层之间的界面，在衬底22上生长非晶中间层28。非晶中间层用作释放应力，否则由于衬底和缓冲层晶格常数的不同可能在单晶调节缓冲层中产生应力。这里所用的晶格常数指在表面平面中测量的晶胞原子之间的距离。如果这种应力没有通过非晶中间层释放，该应力可能在调节缓冲层的晶体结构中引起缺陷。结果在调节缓冲层晶体结构中的缺陷将使得难于在单晶材料层26中获得高质量晶体结构，单晶材料层26包括半导体材料或例如金属或非金属的其它类型材料。
调节缓冲层24优选为根据它与下面的衬底和上面的材料层的结晶相配度而选择的单晶氧化物或氮化物材料。例如，该材料可以是具有与衬底和随后应用的单晶材料层接近匹配的晶格结构的氧化物或氮化物。适用于调节缓冲层的材料包括金属氧化物，例如碱土金属钛酸盐、碱土金属锆酸盐、碱土金属铪酸盐、碱土金属钽酸盐、碱土金属钌酸盐、碱土金属铌酸盐、碱土金属钒酸盐、碱土金属锡基钙钛矿、镧铝酸盐、镧钪氧化物和氧化钆。此外，各种氮化物，例如氮化镓、氮化铝，和氮化硼也可以用于调节缓冲层。尽管例如钌酸锶是导体，但这些材料大多数是绝缘体。一般这些材料是金属氧化物或金属氮化物，特别是这些金属氧化物或氮化物典型地包括至少两种不同的金属元素。在某些特定的应用中，金属氧化物或氮化物可以包括三种或更多不同的金属元素。
按照本发明的一个实施例，调节缓冲层24是具有经验式ABOx的材料，其中A是镁(Mg)、钙(Ca)、锶(Sr)、钡(Ba)或这些材料两种或多种的组合。调节缓冲层24的组分最好选择成它至少部分、优选基本上与下面的材料层晶格匹配。
非晶界面层28优选是由氧化衬底22的表面形成的氧化物，最好是由氧化硅构成。层28的厚度足够释放造成衬底22和调节缓冲层24的晶格常数之间失配的应力。层28典型具有大约0.5-5nm范围的厚度。
总的来说，层32在调节缓冲层24和在递变层32上面随后淀积的单晶材料层的晶格常数之间提供晶格常数过渡。特别是层32的材料选择成通过改变层32的组分可以改变层32的晶格常数，以使层32的底部与调节缓冲层24晶格匹配，且层32的顶部与随后应用的单晶材料层晶格匹配。
根据需要选择递变单晶层32的材料，用于特定的结构或应用。例如，层32的单晶材料可以包括混合IV族半导体，其中通过改变膜成分比例作为膜厚度函数改变材料的晶格常数。按照本发明的一个实施例，层32包括SiyGe1-y(y的范围从0到1)，其中锗的浓度在模板30表面附近很低(即0％)而在层32的顶部附近很高(即100％)。在这种情况下，层32的下表面与包括调节缓冲层24的材料接近晶格匹配，而层32的顶部与锗晶格匹配。按照本发明的另一实施例，层32包括锗，其与包括调节缓冲层24(例如SrTiO3)的材料接近晶格匹配。这里所用的术语“递变”指包括多于一种半导体成分的单晶层，其中通过改变膜(例如SiyGe1-y或SiC)成分作为膜厚度函数改变单晶材料的晶格常数。由此，结构20向随后单晶材料的生长提供了合适的衬底，该单晶材料的晶格常数不同于衬底22或调节缓冲层24材料的晶格常数。
以下将介绍用于模板30的适当材料。合适的模板材料在选定位置以化学方法键合到调节缓冲层24的表面，并提供用于递变单晶层32外延生长形成晶核的位置。当使用时，模板层30具有从大约1到大约10单原子层范围的厚度。
图2以剖面图说明按照本发明的又一实施例的部分半导体结构40。除了在递变层32上形成单晶材料附加层26之外，结构40与先前介绍的半导体结构20相似。层26的材料可包括绝缘、半导体或导体材料。例如，层26可包括半导体材料，例如IV族材料；导体材料，例如金属；绝缘材料，例如氧化物。
图3以剖面图示意性说明按照本发明另一示例性实施例的部分半导体结构34。除了结构34包括非晶层36(而不是调节缓冲层24和非晶界面层28)和附加单晶层38之外，结构34与结构20相似。
以下将更为详尽地说明通过与上述方式相似的方式首先形成调节缓冲层和非晶界面层来形成非晶层36。接着在单晶调节缓冲层上面形成(通过外延生长)单晶层38。接着使调节缓冲层经受退火处理以把单晶调节缓冲层转化为非晶层。以这种方式形成的非晶层36包括调节缓冲层和界面层材料，该非晶层可合并或不合并。由此，层36可包括一层或二层非晶层。在衬底22和附加单晶层26(在层38之后形成)之间形成的非晶层36释放了在层22和层38之间的应力，并向随后的处理(例如形成单晶材料层26)提供了真正的柔性衬底。
与图1和2有关的上述在前工艺适用于在单晶衬底上生长单晶材料层。但是，结合图3介绍的工艺对于生长单晶材料层更好，因为它释放了层26中所有应力，该工艺包括把单晶调节缓冲层转换为非晶氧化层。
附加单晶层38可包括本申请中所述的与单晶材料层26或附加缓冲层32有关的任何材料。例如，当单晶材料层26包括半导体材料时，层38可包括单晶IV族材料。
按照本发明的一个实施例，附加单晶层38用作形成层36期间的退火覆盖层并用作随后形成单晶层26的模板。因此，层38优选足够厚以提供用于层26(至少单原子层)生长的合适模板并且足够薄以使层38形成为基本上无缺陷的单晶材料。
按照本发明的另一个实施例，附加单晶层38包括厚度足以在层38内形成器件的单晶材料(例如与单晶层26有关的上面介绍的材料)。在这种情况下，按照本发明的半导体结构不包括单晶材料层26。换句话说，按照该实施例的半导体结构仅包括设置在非晶氧化层36上的一个单晶层。
以下非限定性的示例性实例说明了按照本发明各个替换实施例、用于结构20、40和34中的材料组合。这些实例仅是说明性的，并不使本发明限制于这些说明性的实例。
实例1
按照本发明的一个实施例，单晶衬底22是(100)方向取向的硅衬底。例如硅衬底可以是通常用于制造具有大约200-300mm直径的互补金属氧化物半导体(CMOS)集成电路的硅衬底。按照本发明的该实施例，调节缓冲层24是CazSr1-zTiO3(其中z的范围从0到1)的单晶层，非晶中间层是在硅衬底和调节缓冲层之间界面形成的氧化硅(SiOx)层。选择z值以获得与随后形成的层32的相应晶格常数接近匹配的一个或多个晶格常数。调节缓冲层可以具有大约2到大约100纳米(nm)的厚度，优选具有大约5nm的厚度。总的来说，希望调节缓冲层足够厚以使递变层与衬底绝缘。厚度大于100nm的层通常提供较少的附加好处，同时增加了不必要的成本；但是，如果需要还是要制造较厚层。氧化硅非晶中间层具有大约0.5-5nm的厚度，优选具有大约1到2nm的厚度。
按照本发明的该实施例，单晶层32是包括SiyGe1-y的IV族半导体层，其中y的范围从0到1，其具有大约1nm到大约100μm的厚度，优选具有大约0.1μm到10μm的厚度，最好具有大约0.1到5μm的厚度。厚度一般取决于随后淀积的材料(例如图2-3的层26)。还可以类似地改变其它化合物半导体材料的组分，例如上面列举的那些，以用同样的方式来控制层32的晶格常数。为了易于在单晶氧化物上外延生长递变层，通过覆盖氧化层来形成模板层。模板层优选是1-10单原子层的Sr-Si、SiOx、Sr-Si-O、Ti-Si、Ti-Ge、Sr-Ge-O、Sr-Ge、GeOx。
实例2
按照本发明的又一实施例，单晶衬底22是上述硅衬底。调节缓冲层是立方或斜方晶相的锶或钡锆酸盐或铪酸盐单晶氧化物，具有在硅衬底和调节缓冲层之间界面形成的非晶氧化硅中间层。调节缓冲层具有大约2-100nm的厚度，优选具有至少5nm的厚度以确保适当的结晶度和表面质量，并由单晶SrZrO3、BaZrO3、SrTiO3或BaTiO3构成。例如，在大约700℃温度可生长Sr(Zr，Ti)O3单晶氧化层。最终结晶氧化物的晶格结构相对于衬底硅晶格结构旋转45度。
由这些锆酸盐或钛酸盐材料构成的调节缓冲层适用于包括例如锗(Ge)的半导体材料的单晶材料层的生长，具有大约1.0nm到10μm的厚度。对该结构适合的模板是1-10单原子层的Ti-Ge、Sr-Ge-O、Sr-Ge或GeOx，优选1-2单原子层的这些材料中的一个。通过实例，对于Sr(Zr，Ti)O3调节缓冲层，用1-2单原子层钛之后淀积1-2单原子层的锗结束表面来形成Ti-Ge模板。接着在模板层上生长单原子锗层。最终的半导体材料晶格结构相对于调节缓冲层晶格结构旋转45度，并且对(100)Ge的晶格失配少于2.5％，优选少于大约1.0％。
实例3
该实例也说明用在图2说明的结构40中的材料。衬底材料22、调节缓冲层24、单晶递变层32和模板层30可以与上述实例1介绍的相同。按照该实施例的一个方案，层32包括SiyGe1-y，其中硅组分从0到大约50％变化。缓冲层优选具有大约10-30nm的厚度。从SiGe到Ge改变层32的组分用于提供在下面的单晶氧化物材料和上面的单晶材料层(在该实例中是Ge层)之间的晶格匹配。
实例4
该实例提供用在如图3说明的结构34中的示例材料。与实例4有关的衬底材料22、模板层30和单晶材料层26可以与上述的相同。
非晶层36是由非晶中间层材料(例如上述层28的材料)和调节缓冲层材料(例如上述层24的材料)的组合适当构成的非晶层。例如，非晶层36包括在形成非晶层36的退火工艺期间其至少部分地组合或混合的SiOx、SrzBa1-zTiO3(其中z的范围从0到1)和Si的组合。
非晶层36的厚度从一个应用中到在另一个应用中可以变化，取决于所需层36的绝缘性质、包括层26的单晶材料类型等因素。按照本实施例的一个示例性方案，层36的厚度从大约2nm到大约100nm，优选大约2-10nm，最好是大约5-6nm。
层38包括可以在例如用于形成调节缓冲层24的材料的单晶材料上外延生长的单晶材料。按照本发明的一个实施例，层38包括与含层26的材料相同的材料。例如，如果层26包括SiGe，层38也包括SiGe。但是，按照本发明其它实施例，层38包括与用于形成层26的材料不同的材料。按照本发明的一个示例性实施例，层38包括硅且为大约1单原子层到大约100nm厚。
再参照图1-3，衬底22是单晶衬底，例如单晶硅衬底。单晶衬底的晶体结构特征在于晶格常数和晶格取向。相似地，调节缓冲层24也是单晶材料并且该单晶材料的晶格特征在于晶格常数和晶向。调节缓冲层和单晶衬底的晶格常数必须接近匹配，或作为替换，必须能够根据相对于另一个晶向旋转一个晶向来获得晶格常数的基本匹配。在本文中，术语“基本相等”和“基本匹配”意为晶格常数之间存在足够的相似性以能够在下面的层上生长高质量结晶层。
图4图解说明高结晶质量的生长晶体层的可得厚度作为结晶核和生长晶体的晶格常数之间失配函数的关系。曲线42说明高结晶质量材料的边界。曲线42右边的区域代表具有大量缺陷的层。由于没有晶格失配，理论上在结晶核上可能生长无限厚、高质量的外延层。随着晶格常数失配的增加，迅速减小了高质量结晶层的可得厚度。作为参考点，例如，结晶核和生长层之间的晶格常数失配大约大于2％，那么不能获得超过大约20nm的单晶外延层。
按照本发明的一个实施例，衬底22是(100)或(111)取向的单晶硅晶片，调节缓冲层24是钙锶钛酸盐层。通过相对于硅衬底晶片晶向把钛酸盐材料的晶向旋转45获得了这两种材料之间晶格常数的基本匹配。如果它足够厚，非晶界面层28结构中的内含物，在该实例中是氧化硅层，用于减小在钛酸盐单晶层中的应力，该应力可能是由基质硅晶片和生长的钛酸盐层晶格常数的任何失配引起的。结果，按照本发明的实施例，可以获得高质量的厚单晶钛酸盐层。
参照图2-3，层26是外延生长的单晶材料层，而且单晶材料的特征也在于晶格常数和晶向。按照本发明的一个实施例，层26的晶格常数与衬底22的晶格常数不同。为了在该外延生长单晶层32中获得高结晶质量，调节缓冲层必须是高结晶质量的。此外，为了在层26中获得高结晶质量，需要晶核(在这里是单晶层)和生长晶体晶格常数之间基本匹配。适当地选择材料，通过改变层32的组分改变层32的晶格常数来获得晶格常数的这种基本匹配。例如，如果生长的晶体是SiGe，调节缓冲层是单晶CazSr1-zTiO3，通过从硅到硅-锗改变SiyGe1-y层32的组分获得了两种材料晶格常数的基本匹配。在氧化层和生长的单晶材料层之间的结晶层32减小了在生长的单晶材料层中由晶格常数的微小差异引起的应力。由此获得了在生长单晶材料层中的较好结晶质量。而且，层32易于把晶体缺陷限制在层32和36界面或在层32和36界面附近并远离层26。
以下实例说明按照本发明的一个实施例、用于制造例如图1-3所示的结构的半导体结构的工艺。该工艺起始于提供包括硅或锗的单晶半导体衬底。按照本发明的优选实施例，半导体衬底是具有(100)取向的硅晶片。衬底优选在晶轴上趋向或至多偏离晶轴5度。至少部分衬底具有裸表面，尽管如下所述衬底的其它部分可以包括其它结构。术语“裸”在本文中意为在部分衬底中的表面被清洗以去除任何氧化物、污染物或其它杂质。众所周知，裸硅是高活性的并易于形成自然氧化物。术语“裸”意为包括这种自然氧化物。在半导体衬底上还有意地生长薄氧化硅，尽管这种生长氧化物对于按照本发明的工艺不是必须的。为了在单晶衬底上面外延生长单晶氧化层，首先必须去除自然氧化层以暴露下面衬底的晶体结构。优选通过分子束外延(MBE)进行以下的工艺，尽管按照本发明也可以使用其它外延工艺。通过首先在MBE设备中热淀积锶、钡、锶和钡的组合物或其它碱土金属或碱土金属的组合物来去除自然氧化物。在使用锶的情况下，接着把衬底加热到大约750℃的温度以使锶与自然氧化硅层反应。锶用于减少氧化硅来形成无氧化硅表面。最终表面表现出有序的2×1结构。如果没有获得这种有序的2×1结构，结构可以暴露于附加锶直到获得有序2×1结构。有序2×1结构形成用于单晶氧化物的上面层有序生长的模板。模板提供必需的化学和物理性质以使上面层的结晶生长形成晶核。
按照本发明的一个替换实施例，转化自然氧化硅，并制备衬底用于通过低温MBE和通过随后加热该结构到大约750℃的温度把碱土金属氧化物(例如氧化锶、锶钡氧化物或氧化钡)淀积到衬底表面上来生长单晶氧化层。在该温度，在氧化锶和自然氧化硅之间发生固态反应，减少了自然氧化硅并保留了有序2×1结构。这再次形成了用于随后有序单晶氧化层生长的模板。
按照本发明的一个实施例，在氧化硅从衬底的表面去除之后，把衬底冷却到大约200-800℃的温度范围，并通过分子束外延在模板层上生长钛酸锶层。通过打开MBE设备中的闸门接触锶、钛和氧源，开始MBE工艺。锶和钛的比率大约为1∶1。氧气的局部压力最初设置在最小值以在每分钟大约0.3-0.5nm的生长速度生长化学计量的钛酸锶。在最初生长钛酸锶之后，氧气的局部压力增加到最初最小值之上。氧气的过压力引起在下面的衬底和生长的钛酸锶层之间的界面生长非晶氧化硅层。氧气通过生长的钛酸锶层扩散到氧气与在下面的衬底表面的硅反应处的界面，引起了氧化硅层的生长。钛酸锶作为有序(100)单晶生长，(100)晶向相对于下面的衬底旋转45°。由于硅衬底和生长晶体之间的晶格常数的微小失配在钛酸锶层中可能存在应力，而在非晶硅氧化中间层中释放了该应力。
在钛酸锶层生长到所需厚度之后，由模板层覆盖单晶钛酸锶，模板层对随后生长的所需单晶层32的外延层是导电的。例如，对于单晶锗层的随后生长，通过结束生长1-2单原子层的钛、1-2单原子层的钛-氧或1-2单原子层的锶-氧来覆盖钛酸锶单晶层的MBE生长。在该覆盖层形成之后，使用MBE生长技术形成硅覆盖层31。在模板(如果需要的话，还有覆盖层31)形成之后，通过外延生长例如锗层而形成层32。
通过上述工艺外加附加单晶层26淀积步骤形成图2说明的结构。使用上述方法在模板或覆盖层上面合适地形成层26。
如上所述通过在生长调节缓冲层、在衬底22上形成非晶氧化层、在调节缓冲层上生长单晶层32来形成图3所说明的结构34。接着使调节缓冲层、非晶氧化层和覆盖层经受足以把调节缓冲层的晶体结构从单晶变为非晶的退火工艺，由此形成非晶层以使非晶氧化层、现在的非晶调节缓冲层和部分覆盖层31的组合形成单一非晶层36。按照本发明的一个实施例，随后在层31上生长层32和26。此外，还可以在层32生长之后进行退火工艺。
按照该实施例的一个方案，通过使衬底22、调节缓冲层、非晶氧化层和覆盖层31经受快速热退火工艺(最高温度大约700℃到大约1000℃，处理时间大约5秒到大约10分)形成了层36。但是，按照本发明还可以使用其它合适的退火工艺以把调节缓冲层转化为非晶层。例如，可以应用激光退火、电子束退火或“常规”热退火工艺(在适当环境中)来形成层36。当应用常规热退火来形成层36时，在退火工艺期间需要层30和/或31的一个或多个组分的过压来防止层分解。
上述工艺说明了通过分子束外延工艺形成包括硅衬底、上面的氧化层和含锗半导体层的单晶材料层的半导体结构的工艺。该工艺还可以通过化学气相淀积(CVD)、金属有机物化学气相淀积(MOCVD)、迁移增强外延(MEE)、原子层外延(ALE)、物理气相淀积(PVD)、化学溶液淀积(CSD)和脉冲激光淀积(PLD)等工艺来进行。而且，通过相似的工艺，还可以生长其它单晶调节缓冲层，例如碱土金属钛酸盐、锆酸盐、铪酸盐、钽酸盐、钒酸盐、钌酸盐和铌酸盐、和例如碱土金属锡基钙钛矿的钙钛矿氧化物、镧铝酸盐、镧钪氧化物和氧化钆。而且，通过相似的工艺，例如MBE，在单晶递变层上面可以淀积包括其它半导体、金属和其它材料的其它单晶材料层。
单晶材料层、单晶递变层和单晶调节缓冲层的每一个变种优选使用用于开始单晶层生长的适当模板。例如，如果调节缓冲层是碱土金属锆酸盐，那么可通过锆薄层覆盖氧化物。可在淀积锆之后淀积硅以使硅与锆反应作为淀积硅锗的前体(precursor)。同样，如果单晶调节缓冲层是碱土金属铪酸盐，那么可通过铪薄层覆盖氧化层。淀积铪之后淀积硅。在同样的方式中，用锶或锶和氧层覆盖钛酸锶，用钡或钡和氧层覆盖钛酸钡。在进行这些淀积的每一个之后淀积硅以使硅与覆盖材料反应来形成用于淀积包括递变单晶材料(例如SiGe和SiC)的单晶材料层的模板。
图5-7以剖面图示意性说明形成按照本发明的器件结构的另一实施例。该实施例包括用作使用笼形物或Zintl型键合的过渡层的柔性层。特别是该实施例利用金属间模板层来降低材料层之间界面的表面能，由此通过层生长产生二维层。
图5说明的结构包括单晶衬底102、非晶界面层108和调节缓冲层104。如前面参照图1和2的介绍，在衬底102和调节缓冲层104之间的界面，在衬底102上生长非晶中间层108。非晶界面层108包括前面参照图1和2中的非晶界面层28介绍的那些材料的任何一种，但优选包括单晶氧化物材料，例如CazSr1-zTiO3单晶层，其中z的范围从0到1。衬底102优选是硅，但还可以包括前面参照图1-3中衬底22介绍的那些材料的任何一种。
如图5说明的，在调节缓冲层104上淀积模板层130，模板层130优选包括由金属和具有大量离子特性的类金属构成的Zintl型相材料(phase material)薄层。如在前面介绍的实施例中，通过MBE、CVD、MOCVD、MEE、ALE、PVD、CSD、PLD等方法淀积模板层130获得一个单原子层的厚度。模板层130用作没有方向键合的“软”层，但是具有吸收在含晶格失配的层之间建立的应力的高结晶性。用于模板130的材料包括但不限于包含Si、Ga、In、Sr和Sb的材料，例如SrAl2、(MgCaYb)Ga2、(Ca、Sr、Eu、Tb)In2、BaGe2As和SrSn2As2。
在模板层130上外延生长单晶递变材料层126获得如图7说明的最终结构。作为特定实例，可以使用SrAl2层作为模板层130，并在SrAl2上生长适当的单晶材料层126，例如化合物半导体材料SiyGe1-y，其中y的范围从0到1。Al-Ti(来自CazSr1-zTiO3层的调节缓冲层，其中z的范围从0到1)键主要是金属性的，而Al-Ge(来自SiyGe1-y层)键是弱共价的。Sr参与两种不同类型的键合，它的部分电荷进到在包括CazSr1-zTiO3的下调节缓冲层104中的氧原子参与离子键合，它的其它部分价电荷以典型Zintl相材料进行的方法捐助给Al。电荷转移的数量取决于包括模板层130的元素的相对负电性和原子间距离。在该实例中，Al呈sp3杂化并易于与单晶材料层126形成键，在该实例中单晶材料层126包括半导体材料SiyGe1-y。
由使用用在该实施例中的Zintl型模板层产生的柔性衬底可以吸收大量应力，而无需显著能量消耗。在上述实例中，通过改变SrAl2层的容量来调节Al的键强度，由此使得器件对于特定应用是可调的，特定应用包括用于CMOS技术的Si器件的单片集成和高-k介电材料的单片集成。
图8以剖面图示意说明按照本发明的又一实施例的器件结构140。器件结构140包括单晶半导体衬底142，优选为单晶硅晶片。单晶半导体衬底142包括两个区143和144。在区域143中至少部分地形成一般由虚线146表示的电半导体部件。电部件146可以是电阻、电容、例如二极管或晶体管的有源半导体部件或例如CMOS集成电路的集成电路。例如，电半导体部件146可以是CMOS集成电路，该CMOS集成电路被构造成执行数字信号处理或非常适合硅集成电路执行的其它功能。通过在半导体工业公知和广为应用的常规半导体处理，可以形成在区域143中的电半导体部件。例如二氧化硅层等的绝缘材料层148覆在电半导体部件146上。
从区域144的表面去除在区域143中半导体部件146的处理期间形成或淀积的绝缘材料148和其它任何层，以在该区提供裸硅表面。众所周知，裸硅表面是高活性的，在裸表面上可以迅速形成自然硅氧化层。锶或锶和氧层淀积到区域144表面上的自然氧化层上并与氧化的表面反应，形成第一模板层(未示出)。按照本发明的一个实施例，通过分子束外延工艺在模板层上面形成单晶氧化层。包含钙、锶、钛和氧的反应物淀积到模板层上形成单晶氧化层。在淀积的初期，局部氧压保持在与钙、锶和钛完全反应形成单晶钙锶钛酸盐所需的最小值附近。接着增加局部氧压以提供过压氧并使氧气通过生长的单晶氧化层扩散。通过钙锶钛酸盐扩散的氧在区域144表面与硅反应以在第二区域上和硅衬底和单晶氧化物之间界面形成氧化硅非晶层。
按照本发明的实施例，通过淀积层150结束淀积单晶氧化层的步骤，层150可以是1-10单原子层的钛、钡、锶、钡和氧、钛和氧、或锶和氧。接着通过分子束外延工艺在第二模板层上面淀积单晶半导体材料的覆盖层152。
按照本实施例的一个方案，在形成层152之后，置于衬底142和钛酸盐层之间的单晶钛酸盐层和氧化硅层经受退火工艺，以使钛酸盐和氧化层形成非晶氧化层154。接着使用与上面介绍的与图1的层32有关的技术在层152上外延生长包括按照本发明一个实施例的SiyGe1-y(其中y的范围从0到1)的递变层156。此外，可以在形成模板层152之前执行上述退火工艺。
接着，在递变层156上形成单晶材料层158，例如Ge。可以使用与层26有关的、这里前面介绍的任意材料和任意技术来形成层158。
按照本发明的又一个实施例，在化合物半导体层158中至少部分地形成一般由虚线160表示的半导体部件。通过在Ge器件制造中常规使用的处理步骤形成半导体部件160。形成由线162示意性表示的金属导体，从而电耦连器件146和器件160，由此实现包括至少一个在硅衬底中形成的部件和一个在单晶材料层中形成的器件的集成器件。虽然作为在硅衬底142上形成并具有锶或钙锶钛酸盐层和锗层158的结构介绍了示例性结构140，但是可以使用本说明书其它地方介绍的其它单晶衬底、氧化层和其它单晶材料层来制造同样的器件。
例如，图9以剖面图示意性说明按照本发明又一实施例的器件结构170。器件结构170包括单晶半导体衬底172，优选为单晶硅晶片。单晶半导体衬底172包括两个区173和174。在区域173中至少部分地形成一般由虚线176表示的电半导体部件。电部件176可以是电阻、电容、有源半导体部件(例如二极管或晶体管)或例如CMOS集成电路的集成电路。例如，电半导体部件176可以是CMOS集成电路，该CMOS集成电路被构造成执行数字信号处理或非常适合硅集成电路执行的另外功能。通过在半导体工业公知和广为应用的常规半导体处理，可以形成在区域173中的电半导体部件。例如二氧化硅层等的绝缘材料层178覆在电半导体部件176上。
从区域174的表面去除在区域173中半导体部件176的处理期间形成或淀积的绝缘材料178和其它层，以在该区提供裸硅表面。锶或锶和氧层淀积到区域174表面上的自然氧化层上并与氧化的表面反应形成第一模板层(未示出)。按照本发明的一个实施例，通过分子束外延工艺在模板层上面形成单晶氧化层。包含锶、钛和氧的反应物淀积到模板层上形成单晶氧化层。在淀积的初期，局部氧压保持在与锶和钛完全反应形成单晶钛酸锶层所需的最小值附近。接着增加局部氧压以提供过氧压并使氧气通过生长的单晶氧化层扩散。通过钛酸锶扩散的氧在区域174表面与硅反应以在第二区上以及在硅衬底和单晶氧化物之间界面形成氧化硅非晶层。
按照本发明的实施例，通过对层180的淀积结束淀积单晶氧化层的步骤，层180可以是1-10单原子层的钛、钡、锶、钡和氧、钛和氧、或锶和氧。接着通过分子束外延工艺在第二模板层上面淀积单晶半导体材料覆盖层182。
按照本实施例的一个方案，在形成层182之后，置于衬底172和钛酸盐层之间的单晶钛酸盐层和氧化硅层经受退火工艺以使钛酸盐和氧化层形成非晶氧化层184。接着使用与上面介绍的与图1的层32有关的技术在层182上外延生长包括按照本发明该实施例的Ge的层186。此外，可以在形成模板层182之前执行上述退火工艺。
接着，在层186上形成单晶材料层188，例如Ge。可以使用与层26有关的这里前面介绍的任意材料和任意技术来形成层188。
按照本发明的又一个实施例，在半导体层188中至少部分地形成一般由虚线160表示的半导体部件。形成由线162示意性表示的金属导体，从而电耦连器件176和器件160，由此实施包括至少一个在硅衬底中形成的部件和一个在单晶材料层中形成的器件的集成器件。
应该清楚，那些特别说明的具有两种不同IV族半导体部分的结构的实施例是为了说明本发明的实施例，而非限定本发明。存在本发明的多种其它组合和其它实施例。例如，本发明包括制造材料层的结构和方法，该材料层形成包括其它层(例如金属和非金属层)的半导体结构、器件和集成电路。特别是本发明包括形成柔性衬底的方法，该柔性衬底用于制造半导体结构、器件和集成电路和适合制造那些结构、器件和集成电路的材料层。
按照本发明的一个实施例，单晶半导体晶片可用于在晶片上面形成单晶材料层。在这种情况中，在晶片上单晶层内制造半导体电部件期间所用的晶片实际上是“操作”(handle)晶片。因此，可以在至少大约200毫米直径和可能在至少大约300毫米直径的晶片上的半导体材料内形成电部件。
通过使用这种类型的衬底，较廉价“操作”晶片通过把某些单晶材料晶片放置在相对较耐久和易于制造的基底材料上克服了它们易碎的性质。因此，形成集成电路，以使即使衬底自身包括不同单晶半导体材料，也可在单晶材料层内或使用单晶材料层形成所有电部件，特别是所有有源电器件。因为与较小和较易碎衬底(例如常规化合物半导体晶片)相比，较大衬底可以更经济和更容易地被处理，所以降低了用于应用非硅单晶材料的某些器件的制造成本。
在上述详述中，参照特定实施例介绍了本发明。但是，本领域普通技术人员应领会，在不脱离如所附权利要求所阐述的本发明的范围的前提下，可以做出各种改进和变型。因此，详述和附图应认为是说明性的，而非限制含义，而且所有这些改进都包括在本发明的范围内。参考特定实施例，以上介绍了好处、其它优点和问题的解决方案。但是，好处、优点、问题的解决方案和可以使得任何好处、优点或解决方案产生或变得更显著的任何元素不应被解释为任一或所有权利要求的关键、所需或必要特征或元素。这里所用的术语“包括”、“包含”(comprises、comprising)或其任何其它变型意旨涵盖非排他性的包含，由此，包括列举元素的工艺、方法、制品或设备不仅包括那些元素，还包括没有列举表述或这些工艺、方法、制品或设备所固有的其它元素。

Claims (24)

1.一种半导体结构，包括：
单晶衬底；
在所述衬底上形成的调节缓冲层；
在所述单晶调节缓冲层上形成的模板；和
在所述模板上面形成的单晶层，所述单晶层包括选自由Si、SiC、Ge和SiyGe1-y构成的组中的材料，其中y的范围从0到1。
2.如权利要求1所述的半导体结构，还包括置于所述单晶衬底和所述调节缓冲层之间的非晶层。
3.如权利要求2所述的半导体结构，其中所述非晶层包括氧化硅。
4.如权利要求2所述的半导体结构，其中所述非晶层为大约0.5到大约5.0纳米厚。
5.如权利要求1所述的半导体结构，其中所述调节缓冲层包括选自由碱土金属钛酸盐、碱土金属锆酸盐、碱土金属铪酸盐、碱土金属钽酸盐、碱土金属钌酸盐、碱土金属铌酸盐和钙钛矿氧化物构成的组中的氧化物。
6.如权利要求1所述的半导体结构，其中所述调节缓冲层包括CazSr1-zTiO3，其中z的范围从0到1。
7.如权利要求1所述的半导体结构，其中所述调节缓冲层为大约2到大约100纳米厚。
8.如权利要求1所述的半导体结构，其中所述调节缓冲层为大约5纳米厚。
9.如权利要求1所述的半导体结构，其中所述单晶递变层为大约1纳米到大约100微米厚。
10.如权利要求9所述的半导体结构，其中所述单晶递变层为大约0.1到大约5微米厚。
11.如权利要求1所述的半导体结构，还包括覆盖层。
12.如权利要求11所述的半导体结构，其中所述覆盖层包括单晶硅。
13.如权利要求1所述的半导体结构，其中所述调节缓冲层包括非晶膜。
14.如权利要求1所述的半导体结构，其中所述调节缓冲层包括单晶膜。
15.一种使用权利要求1所述的半导体结构形成的微电子器件。
16.一种用于制造半导体结构的工艺，包括如下步骤：
提供单晶衬底；
在所述单晶半导体衬底上面外延生长单晶调节缓冲层；
在所述单晶衬底和所述调节缓冲层之间形成非晶层；和
在所述调节缓冲层上面外延生长单晶层，其中所述单晶层包括选自由Si、SiC、Ge和SiyGe1-y构成的组中的材料，其中y的范围从0到1。
17.如权利要求16所述的工艺，其中所述外延生长单晶调节缓冲层的步骤包括外延生长含CazSr1-zTiO3的单晶调节缓冲层，其中z的范围从0到1。
18.如权利要求16所述的工艺，还包括加热所述单晶调节缓冲层和所述非晶层以使得所述单晶调节缓冲层变成非晶的步骤。
19.如权利要求18所述的工艺，其中所述加热步骤包括快速热退火。
20.如权利要求19所述的工艺，还包括在所述单晶调节缓冲层上形成第一模板的步骤。
21.如权利要求20所述的工艺，还包括在所述模板上形成覆盖层。
22.如权利要求16所述的工艺，还包括在所述单晶衬底上面形成模板的步骤。
23.如权利要求16所述的工艺，还包括在所述单晶层上面外延生长单晶材料层。
24.使用权利要求16所述的方法形成微电子器件。
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CN100593110C (zh) * 2005-05-24 2010-03-03 中国科学院物理研究所 具有高灵敏度的光电型探测器
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CN108054824A (zh) * 2017-12-26 2018-05-18 北京中兑志远科技发展有限公司 一种能提高光电转化效率的光伏发电装置

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