CN1542929B - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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CN1542929B
CN1542929B CN2004100351663A CN200410035166A CN1542929B CN 1542929 B CN1542929 B CN 1542929B CN 2004100351663 A CN2004100351663 A CN 2004100351663A CN 200410035166 A CN200410035166 A CN 200410035166A CN 1542929 B CN1542929 B CN 1542929B
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film
gate electrode
annealing
impurity
tft
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CN1542929A (zh
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张宏勇
高山彻
竹村保彦
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Semiconductor Energy Laboratory Co Ltd
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Abstract

本发明涉及半导体器件的一种制造方法,其特征在于,它包括下列步骤:在具有绝缘表面的衬底上形成一层晶体半导体膜;在所述晶体半导体膜上通过利用四乙氧基硅烷形成包括二氧化硅的栅绝缘膜;形成邻近所述晶体半导体膜的栅电极,其中所述栅绝缘膜插入在所述晶体半导体膜和所述栅电极之间,所述栅电极包括从由钽、钛、钨、钼和硅组成的组中选取的一种材料;以及通过所述栅绝缘膜向所述晶体半导体膜中引入杂质元素,从而在所述晶体半导体膜中形成至少一个杂质区。

Description

半导体器件的制造方法
本申请是申请号为98116322.X、申请日为1994年3月12日的原案申请的分案申请,该原案的首个在先申请为JP93-78997,首个在先申请日为1993年3月12日。
技术领域
本发明涉及一种薄膜晶体管(TFT)及其制造方法。依本发明的薄膜晶体管可以做在诸如玻璃的绝缘衬底上,也可做在如由晶体硅制成的衬底上。特别是本发明涉及一种通过结晶化和热退火激活等工艺步骤来制造的薄膜晶体管。
背景技术
近来,对包含一绝缘衬底并在其上设有一薄膜有源层(有时也称之为有源区)的绝缘栅型半导体器件进行了有效地研究。特别是,对薄膜型绝缘栅晶体管即通常所说的薄膜晶体管(TFT)的研究付出了极大的努力。将多个TFT做在透明的绝缘衬底上,主要是为了用它们来控制矩阵驱动显示装置的每个象素或驱动电路。根据TFT所用的半导体的材料和状态,可将TFT分为非晶硅TFT和结晶硅TFT。
在上述的诸多TFT中,非晶TFT的制造可不必经受高温工艺过程。非晶TFT早已投入实用,因为当把它们制做在大面积衬底上时,其成品率高。一般在实际的非晶硅TFT中采用倒梯型(也称之为底栅型)非晶硅TFT。此类非晶硅TFT的栅电极设在有源区的下方。
制造现有的TFT的工艺步骤包括:在一衬底上形成一栅电极;形成做为栅绝缘膜的非晶硅膜和有源层;以及在非晶硅膜上形成一N型结晶细密的硅膜,以设置源和漏区。然而、由于N型硅膜与作为基底而设置的非晶硅膜的腐蚀速率几乎相同,所以该工艺要求额外的步骤,例如设置一腐蚀终止层和类似层。
作为一种克服上述问题的措施,提供一种用离子掺杂工艺,将高速离子直接注入到非晶硅膜中形成源和漏的方法。
但该法尚有不尽入意之处,因为它产生的离子注入区的结晶性被明显损伤。这些区的电导率低,因而尚不适于实用。也曾提出,用激光束和类似的光能使这些区退火,以增大其结晶性,然而,此法不适用于批量生产。
目前实际有用的方法是靠加热使非晶硅结晶化的方法。但是此法要求在600℃或以上的温度的退火。因而由于衬底的问题此工艺也不受欢迎。更具体地说,一般用于非晶硅TFT的元碱玻璃衬底在600℃或低一些温度下即开始变形(如Corning7059玻璃衬底软化点在593℃)。在600℃的退火会使玻璃衬底收缩或变形。
而且,600℃的退火会损伤先前在低温下制作的非晶硅的特性。更具体地说,使有源区也经受在600℃的结晶化,而完全丧失了有利的特性,即非晶硅TFT不再具有它的低漏电流之特征。这问题要求结晶化工艺能在更低温度下进行(最好是在低于玻璃的变形温度50℃或再低些的温度)。
一般,处于非晶态的半导体具有低的电场迁移率。因而,它们不能用于要求高速运作的TFT。而且,P型非晶硅的电场迁移率极低。这就使P沟TFT(PMOS TFT)的制造行不通。以此推断得不到互补的MOS电路,因为为实现CMOS必须P沟TFT与N沟TFT(NMOS TFT)相结合。
与非晶半导体相比,晶体半导体具有更高的电场迁移率,因而适用于高速运作的TFT。结晶硅的优点还在于,用它容易制作CMOS电路,因为由结晶硅不仅能得到NMOS TFT,而且还能得到PMOS TFT。因此提出一种具有称为单片结构的有源矩阵驱动的液晶显示器,不仅在有源矩阵部分,而且在外围电路(例如驱动电路)均由CMOS的晶体TFT组成。由于这些原因,使得对使用结晶硅的TFT的研究及开发最近更加活跃。
对非晶硅用激光或光强相等的强光辐照可以得到结晶硅。然而,此工艺不适于批量生产;而且不稳定,因为激光输出本身就不稳定,还因为工艺过程太短。
一种使非晶硅结晶化的实际可行的工艺最近是采用热处理,即热结晶化。此工艺能生产出质量均匀的结晶硅,不管批量如何。但该工艺仍存在问题,尚待解决。
一般,热结晶化要求在大约600℃实施长时间的退火,或在高达1000℃温度,或甚至更高的温度退火。后种工艺使得对衬底材料的选择变窄,因为它不能应用于除石英衬底以外的衬底,前述的处理还有另一些问题。
具体地说,使用廉价的无碱玻璃衬底(如Corning#7059玻璃衬底)来制造TFT的工艺过程包括:
在衬底上淀积一层非晶硅膜;
在600℃或更高的温度经24小时或更长的时间使非晶硅膜结晶化;
淀积一层栅绝缘膜;
形成栅电极;
引入杂质(用离子注入或离子掺杂);
在600℃或更高的温度经24小时或更长的时间退火使掺入的杂质激活;
形成层间绝缘体;以及
形成源和漏区。
在上述工艺步骤中,发现第六步使掺入的杂质激活最成问题。大多数无碱玻璃在600℃附近(如Corning#7059玻璃的软化温度为593℃)会变形。这就意味着,在该步必须考虑衬底的收缩。在第二步中,即退火步骤,衬底的收缩是不成问题的,因为还未在衬底上构成图形。然而,在第六步,在衬底上已构成电路图形,若衬底收缩,则在后几步不能进行掩模对准。这显然会降低成品率。这就要求在较低的温度下进行第六步,最好在比玻璃变形温度低50℃或再低些的温度下进行。
如前所述,使用激光可降低工艺温度。但是该工艺的可靠性差,因为不仅激光不稳定,而且还由于在被激光辐照的部位(源和漏区)与未被激光辐照的部位(有源区即栅电极下方的区域)之间的温升不同而产生应力。
发明内容
因而使用激光来制造TFT是困难的,目前尚未发现其它有效的措施来克服这些问题。本发明为上述困难提供一种解决办法。即本发明之目的在于提出一种克服上述问题并适于批量生产的工艺。
作为本发明者们广泛研究的结果,发现基本上为非晶的硅膜的结晶化可借助加入微量催化材料而被加速。按此方法,结晶化可以在较低的温度较短的时间内完成。优选的催化材料包括一些纯金属即:镍(Ni)、铁(Fe)、钴(Co)和铂(Pt),或一种化合物,如本文所列举的元素的硅化物。具体地说,根据本发明的工艺包括:在非晶硅膜之上或之下并与之接触形成一种含有薄膜、颗粒、团块等形状的催化元素的材料,以及在一适当的温度,一般在580℃或再低些,最好在550℃或再低些将形成的材料热退火使之结晶化。另一种方法是,不必形成一种含催化元素与非晶硅膜接触的材料,代之以用诸如离子注入等方法将催化元素掺入非晶硅膜中。
当然,提高退火的温度可以缩短结晶化的周期。而且,随着镍、铁、钴或铂浓度的增加而使结晶化的周期变短、结晶化的温度变低。通过深入的研究,本发明者们发现,至少一种上述催化元素的掺入浓度在1×1017cm-3以上方能加速结晶化,其浓度最好在5×1018cm-3或更高些。
但,上列各催化材料对硅不利。因而,最好将其浓度控制到尽可能低的水平。通过研究,本发明者们发现总浓度的优选范围在1×1020cm-8或再低些。特别是,在有源层,催化材料的浓度必须控制到1×1018cm-3或以下,最好低于1×1017cm-3,低于1×1016cm-3则更好。
附图说明
图1(A)-1(E)示意表示按本发明的一个实施方案(实施例1)的工艺所得到的按顺序的结构剖面图;
图2(A)-2(E)示意表示按本发明的另一实施方案(实施例2)的工艺所得到的按顺序的结构剖面图;
图3(A)-3(E)示意表示按本发明的又一实施方案(实施例3)的工艺所所到的按顺序的结构剖面图;以及
图4(A)-4(E)示意表示按本发明的再一个实施方案(实施例4)的工艺所得到的按顺序的结构剖面图。
具体实施方式
如前所述,本发明者们已注意到催化元素的作用,并发现可以利用这些元素来克服已有技术工艺中的问题。一种依本发明的一实施方案制作TFT的工艺包括:
形成一栅电极;
淀积一栅绝缘膜;
淀积一层非晶硅膜;
用离子注入或离子掺杂将杂质引入非晶硅膜内;
在该硅膜上形成含一种催化元素的物质膜;
在550℃或550℃以下热处理不长于8小时使掺入的杂质激活;以及
形成源和漏电极。
一种按本发明另一实施方案的工艺包括:
形成一栅电极;
淀积一层栅绝缘膜;
淀积一层非晶硅膜;
用离子注入或离子掺杂将杂质引入非晶硅膜;
用离子注入或离子掺杂将催化元素引入该硅膜;
在550℃或低于550℃热处理不长于8小时使掺入的杂质激活;以及
形成源和漏电极。
在上述工艺步骤中,第四步与其后的一步之次序是可调换的。即,掺杂步骤既可在引入催化元素步骤之前,也可在其后进行。主要是引入源和漏区的催化元素显著地加速了这两区的结晶化。因此在550℃或以下的温度足以能完成激活,一般在500℃或再低些温度进行。退火8小时或更短些,一般是退火4小时或更短些已足够。特别是,发现当用离子注入或离子掺杂将催化元素引入硅膜时,结晶化进行得极其迅速,因为发现元素是均匀地分布在硅膜中。
在杂质掺杂中,可使用掩模将催化元素掺入硅膜中。按自对准方式,从栅电极背后照射可以得到该掩膜。
另一种按本发明的又一实施方案制作TFT的工艺包括:
淀积一层非晶硅膜;
将非晶硅膜在600℃或其以上的温度加热24小时或更长些,使其结晶化;
淀积一层栅绝缘膜;
形成一栅电极;
用离子注入或离子掺杂将杂质引入非晶硅膜;
在硅膜上淀积一层含一种催化元素的膜;
在600℃或其以下热处理不长于8小时使掺入的杂质激活;
形成层间绝缘体;以及
形成源和漏电极。
再一种按本发明的一实施方案制作TFT的工艺包括:
淀积一层非晶硅膜;
在600℃或其以上将非晶硅膜加热24小时或更长些,使其结晶化;
淀积一层栅绝缘膜;
形成一栅电极;
用离子注入或离子掺杂将杂质引入非晶硅膜;
用离子注入或离子掺杂将一种催化元素引入该硅膜;
在600℃或其以下热处理不长于8小时使掺入的杂质激活;
形成层间绝缘体;以及
形成源和漏电极。
在上述工艺步骤中,第5步和其下一步的次序可以颠倒。即,掺杂步骤既可在引入催化元素步骤之前也可在其后进行。主要是引入源和漏区的催化元素显著地加速了这两区的结晶化。因而,在600℃或其以下足以进行激活,一般在550℃或其以下。对退火而言,8小时或短些,一般用4小时或短些已经足够。特别是,当用离子注入或离子掺杂将催化元素引入硅膜时,发现结晶化进行得极其迅速,因为发现元素均匀分布在硅膜中。
本发明的工艺之特征在于,该工艺包括,加入对硅不利的催化元素,但在有源区的浓度被压到极低水平1×1018cm-3或其以下。即,所有的前述工艺均包括,在掺杂时为有源区提供一掩模或栅电极。因而,催化元素不会直接接触到或注入进有源区。而保持TFT的可靠性和特性不被削弱。特别是,将Ni掺入杂质区其浓度为有源区的10倍或以上,再择优设定退火温度和时间,可以使杂质区被激活并同时保持非晶态。因为退火是在热平衡下完成的,不会碰到激光退火中出现的温度差。
下面参照非限定的实施例,对本发明做更详细的说明。但应了解此非对本发明的限制。
实施例1
图1表示按本发明的一个实施方案的工艺所得到的按步序的结构剖面图。参照图1,在Corning#7059玻璃衬底1上形成一层厚度为3000-8000
Figure S04135166320040524D000081
钽膜,并构成图形,形成栅电极2。然后,将钽膜表面阳极氧化,形成厚度为1000-3000
Figure S04135166320040524D000082
例如2000
Figure S04135166320040524D000083
的阳极氧化膜3。然后用等离子CVD淀积一层厚度为1000-5000例如1500
Figure S04135166320040524D000085
的氮化硅膜4。紧接着用等离子CVD在其上淀积一层厚度为200-1500
Figure S04135166320040524D000086
例如500的本征(I-型)非晶硅膜。将最后得到的非晶硅膜构图得到半导体区域5,如图1(A)所示。
将所得到衬底表面被覆以光刻胶,并从衬底背面曝光,以形成与栅电极图形一致的掩模6,如图1(B)所示。
用离子掺杂,使用所得到的掩模6,将磷作为杂质注入半导体区5。用磷化氢(PH3)作为掺杂气体进行离子掺杂,所用的加速电压在60-90KV,例如80KV,所用的剂量在1×1015-8×1015cm-2范围。在此情况下,磷的掺入剂量为2×1015cm-2。以此方法形成N型杂质区7a和7b,如图1(C)所示。
然后,用掩模6通过离子掺杂注入镍离子。所用的剂量为2×1013-2×1014cm-2,更具体地讲例如是5×1013cm-2。其结果,发现镍在N型杂质区26a和26b中的浓度大约5×1018cm-3。如此就得到了如图1(D)所示的结构。
然后,将所得结构在含分压强最好为0.1-1大气压的氢的氢气氛中在500℃退火4小时。以此方法激活杂质。因为镍离子已事先注入到杂质区,由于镍对结晶化的催化作用,发现在这些区域中的结晶化被加快了。这样就激活了杂质区7a和7b。
随后用等离子CVD淀积3000
Figure S04135166320040524D000091
厚的氧化硅膜8,作为层间绝缘体,在其上形成接触孔以便为TFT的源和漏区,用含金属材料如氮化钛和铝的多层膜,建立带互连9a和9b的电极。这就完成了一个完整的薄膜晶体管,如图1(E)所示。
用二次离子质谱仪(SIMS)测量按上述工艺制得的TFT的杂质区和有源区的镍浓度。测得杂质区含镍浓度为1×1018-5×1018cm-3。这与低于探查极限1×1016cm-3的有源区的浓度形成明显的对照。
实施例2
图2表示用本发明的一实施方案所得到的各步序结构的剖面图。参照图2,在Corning#7059玻璃衬底11上形成厚度为3000-8000例如5000的钽膜,并构图形成栅电极12。然后,用阳极氧化法,使钽膜的表面形成厚度为1000-3000例如2000
Figure S04135166320040524D000101
的阳极氧化膜。然后,用等离子CVD法淀积厚度为1000-5000例如为1500
Figure S04135166320040524D000103
的氮化硅膜14。紧接着,在其上用等离子CVD淀积厚度为200-1500例如在本例中为500
Figure S04135166320040524D000105
的本征(I型)非晶硅膜。将得到的非晶硅膜构图以得到半导体区15,如图2(A)所示。
在所得衬底的表面上被覆一层光刻胶,从衬底的背面曝光以形成与图2(B)所示栅电极图形一致的掩模16。
通过离子掺杂法,用所得的掩模16,以磷作杂质注入半导体区15。用磷化氢(PH3)作掺杂气体完成离子掺杂,所加的加速电压在60-90KV,例如用80KV,剂量在1×1015-8×1015cm-2。在本例中掺入磷所用的剂量为2×1015cm-2。以此方式,形成了N型杂质区17a和17b,如图2(C)所示。
然后,用溅射法在整个表面上淀积厚度为5-200
Figure S04135166320040524D000106
例如20
Figure S04135166320040524D000107
的一层硅化镍膜(以化学式表达为NiSix,此处X为0.4-2.5例如2.0)18。由于所得到的膜薄至大约20,看来好像一些团粒,而不像连续的膜。在本例中膜的外观并不那么重要。这样就得到了如图2(D)所示之结构。
然后,将所得结构在含氢的气氛中退火,所用的温度为450℃,时间4小时,氢的分压强最好为0.1-1大气压。以此方式,激活杂质。因为硅化镍膜18是预先淀积的,由它扩散镍原子,对N型杂质区17a和17b的结晶化起催化剂作用。这样就加速了这些区的结晶化,使杂质区17a和17b激活。
随后,用等离子CVD淀积一层3000厚氧化硅膜19作为层间绝缘体,并在其上形成接触孔,以便为TFT的源和漏区,用含金属材料如氮化钛和铝的多层膜,建立带互连20a和20b的电极。这就完成了一个完整的薄膜晶体管,如图2(E)所示。
用二次离子质谱仪(SIMS)测量按上述工艺制得的TFT的杂质区和有源区镍的浓度。测得杂质区含镍浓度为1×1018-3×1018。这与在1×1016-5×1016范围的有源区浓度成鲜明的对照。
实施例3
图3表示用本发明另一实施方案的工艺所制得的各步序结构的剖面图。参照图3,在一块7059玻璃衬底110上用溅射法形成一层2000
Figure S04135166320040524D000112
厚的氧化硅膜111,作为底膜。然后,用等离子CVD在其上淀积厚度为500-1500,例如1500的本征(I型)非晶硅膜。然后,在氮气氛中600℃退火48小时,使非晶硅膜结晶化。退火之后,将硅膜构成图形形成岛状硅区112,用溅射法在其上淀积一层1000厚的氧化硅膜113作为栅绝缘膜。溅射工艺是在含氧和氩的气氛中以氧化硅作为溅射的靶进行的,氩对氧之比不高于0.5,例如为0.1或0.1以下。在工艺过程中,衬底的温度保持在200-400℃,例如350℃。然后,用减压CVD淀积厚度为6000-8000
Figure S04135166320040524D000116
例如6000
Figure S04135166320040524D000117
的含磷为0.1-2%的硅膜。淀积氧化硅膜的步骤最好与淀积硅膜的步骤连续进行。将所得的硅膜构图形成栅电极114,如图3(A)所示。
然后,用等离子掺杂,用栅电极作掩模,将磷作为杂质引入硅区。用磷化氢(PH3)作为掺杂气体,进行掺杂,所用的加速电压为60-90KV,例如为80KV,所用的剂量为1×1015-8×1015cm-2。在本实施例中所掺杂的磷的剂量为2×1015cm-2。以此方式,形成了N型杂质区115a和115b,如图3(B)所示。
腐蚀杂质区上的氧化硅膜113以露出杂质区115,在整个表面上用溅射法淀积厚度为5-200
Figure S04135166320040524D000121
,例如20的硅化镍膜(用化学式NiSix表示,此处X为0.4-2.5,例如2.0)116。由于所得的膜大约为20
Figure S04135166320040524D000123
之薄,看来好像团粒,不像连续膜。在本例中,该膜的外观不那么重要。这样就得到了如图3(C)所示之结构。
然后,把所得结构放入氮气氛中在500℃退火4小时以激活杂质。因为镍从预先淀积在其上的硅化镍膜扩散进入N型杂质区115a和115b,发现经退火加速了结晶化的发生。以此方式,激活了杂质115a和115b。所得结构如图3(D)所示。
然后,用等离子CVD淀积6000
Figure S04135166320040524D000124
厚的氧化硅膜117作为层间绝缘层,以在其上开出接触孔用含金属材料,如氮化钛和铝的多层膜为TFT的源和漏区形成带互连118a和118b的电极。最后,将所得结构在1大气压的氢气氛中在350℃退火30分钟。这样就完成了一完整的薄膜晶体管,如图3(E)所示。
用二次离子质谱仪(SIMS)测量按上述工艺制得的TFT的源和漏区以及有源区镍的浓度。发现源和漏区的含镍浓度为1×1018-5×1018cm-3。这与低于探查极限1×1016cm-3的有源区的浓度成鲜明的对比。
实施例4
图4表示用本发明另一实施方案的工艺所制得的各步序结构的剂面图。参照图4,在一块Corning#7059玻璃衬底29上,用溅射法形成一层2000
Figure S04135166320040524D000125
厚的氧化硅膜作底膜。然后,用等离子CVD在其上淀积一层本征(I型)非晶硅膜,其厚度在500-1500范围,例如1500。然后,在氮气氛中,在600℃退火48小时,使非晶硅膜结晶化。退火之后,将硅膜构图形成岛状硅膜22。
然后,用等离子CVD,使用四乙氧硅烷(TEOS;Si(OC2H5)4)和氧作为原材料淀积一层1000
Figure S04135166320040524D000131
存的氧化硅膜23作为栅绝缘膜。于是在原始气体材料中添加三氯乙烯。在薄膜淀积开始之前,以400SCCM(每分标准立方厘米)的流量向反应腔通氧气,当将总压力保持在5Pa,衬底温度为300℃,并施加150W的RF功率时,在反应腔内产生等离子体。这种状态保持10分钟。然后,以分别为300SCCM,15SCCM和2SCCM的流量向反应腔通入氧、TEOS和三氯乙烯,淀积氧化硅膜。在淀积薄膜期间,使衬底温度、RF功率和总压强分别保持在300℃、75W和5Pa。当完成薄膜淀积时,给反应腔通入压力为100Torr的氢气,以完成在350℃的氢退火35分钟。
随后,用溅射法淀积厚度在3000-8000
Figure S04135166320040524D000132
,例如为6000
Figure S04135166320040524D000133
的钽膜。可以用钛、钨、钼或硅代替钽。然而,该膜必须有足够高的耐热性能,以耐得住后来的激活处理。氧化硅膜23和钽膜的两步淀积步骤最好连续进行。将钽膜构图形成TFT的栅电极24。再将钽膜表面阳极氧化,在其表面上形成氧化层25。阳极氧化是在含1-5%的洒石酸的乙二醇溶液中进行的。于是得到2000厚的氧化层,如图4(A)。
以栅电极作为掩模用等离子掺杂,将磷作为杂质注入硅区。用磷化氢(PH3)作掺杂气体进行掺杂工艺,所用的加速电压80KV。在此例中,以2×1015cm-2的剂量掺入磷。以此方式,形成了N型杂质区26a和26b。可以看到,在此情况所建立的杂质区26偏离了栅电极24,如图4(B)所示。
然后,用离子掺杂以栅电极作掩模注入镍离子。引入镍所用的剂量在2×1013-2×1014cm-2的范围,例如更具体地用5×1013cm-2。其结果,发现镍在N型杂质区26a和26b内的浓度大约为5×1018cm-3。于是得到如图4(C)所示之结构。
然后将所得的结构在氮气氛中在500℃退火4小时,以激活杂质。由于镍离子预先被注入N型杂质区26a和26b,发现由于镍对结晶化的催化作用,加速了这些区域内的再结晶化的进行。于是使杂质区26a和26b激活。所得结构如图4(D)所示。随后,用TEOS作原材料,用等离子CVD淀积2000
Figure S04135166320040524D000141
厚的氧化硅膜27作为层间绝缘体,在其上形成接触孔,用含金属材料如氮化钛和铝的多层膜为TFT的源和漏区形成带互连28a和28b的电极。于是完成了完整的半导体电路,如图4(E)所示。
发现这样制作的薄膜晶体管,在栅电压为10V时,其场效应迁移率在70-100cm2/Vs范围,当给栅极施加-20V电压时,其阀值电压为2.5-4.0V,漏电流为10-13A或更低。
本发明借助在4小时之短的期间内,在500℃之低的温度下将掺入的杂质激活,提高了薄膜晶体管的生产量。因而本发明提供一种解决现有技术问题的方法;由于在600℃或其以上所进行的高温工艺中,已遇到玻璃衬底变形这样严重的问题,在上述这样低的温度下实现了结晶化避免了玻璃衬底收缩和弯曲。
上面列举的本发明的优点还包括能一次处理大面积的衬底。更具体地说,由大面积衬底切成多个半导体电路(如矩阵电路)。因而明显地可以降低电路的单个成本。当应用于液晶显示器的生产时,根据本发明的工艺可提高生产率并改进了显示器的性能。由上述可见,本发明可广泛用于工业生产。
尽管参照具体的实施例详细地叙述了本发明,但本领域的技术人员应该明了,不脱离本发明的精神和范畴可以进行各式各样的变化和改型。

Claims (8)

1.一种制造半导体器件的方法,其特征在于,它包括下列步骤:
在具有绝缘表面的衬底上形成非晶半导体膜;
使所述非晶半导体膜结晶以便形成晶体半导体膜;
在所述晶体半导体膜上通过利用四乙氧基硅烷、氧和三氯乙烯形成氧化硅膜作为栅绝缘膜;
形成邻近所述晶体半导体膜的栅电极,其中所述栅绝缘膜插入在所述晶体半导体膜和所述栅电极之间,所述栅电极包括从由钽、钛、钨、钼和硅组成的组中选取的一种材料;
在形成所述栅电极之后,通过所述栅绝缘膜向所述晶体半导体膜中引入杂质元素,从而在所述晶体半导体膜中形成至少一个杂质区;
将浓度在1×1017cm-3到1×1020cm-3之间的催化材料引入杂质区;以及
退火以便激活杂质元素。
2.根据权利要求1所述的制造半导体器件的方法,其特征在于,还包括以下步骤:
形成包括氮化钛和铝的导电膜,所述导电膜电连接到所述杂质区。
3.根据权利要求1所述的制造半导体器件的方法,其特征在于,还包括以下步骤:
在所述栅电极之上通过利用四乙氧基硅烷形成氧化硅膜作为层间绝缘膜。
4.根据权利要求1所述的方法,其特征在于,所述退火是在含氮气氛中进行的。
5.根据权利要求1至3的任何一项所述的方法,其特征在于,所述杂质元素是磷。
6.根据权利要求1至3的任何一项所述的方法,其特征在于,通过等离子化学汽相淀积形成所述栅绝缘膜。
7.根据权利要求3所述的方法,其特征在于,通过等离子化学汽相淀积形成所述层间绝缘膜。
8.根据权利要求1所述的方法,其特征在于,所述退火在580℃或低于580℃。
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US5646424A (en) 1997-07-08
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CN1215224A (zh) 1999-04-28
KR100203982B1 (ko) 1999-06-15
CN1095204C (zh) 2002-11-27
CN1154165C (zh) 2004-06-16
US6060725A (en) 2000-05-09
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CN1108004A (zh) 1995-09-06
CN1542929A (zh) 2004-11-03
CN1275813A (zh) 2000-12-06

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