CN1543675A - 具有无凸块的叠片互连层的微电子组件 - Google Patents

具有无凸块的叠片互连层的微电子组件 Download PDF

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CN1543675A
CN1543675A CNA018207138A CN01820713A CN1543675A CN 1543675 A CN1543675 A CN 1543675A CN A018207138 A CNA018207138 A CN A018207138A CN 01820713 A CN01820713 A CN 01820713A CN 1543675 A CN1543675 A CN 1543675A
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microelectronic chip
micromodule
lamination
interconnector
active surface
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CNA018207138A
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CN100367496C (zh
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P��H��Τĭ
P·H·韦默
S·N·托勒
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Intel Corp
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Intel Corp
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Abstract

公开了一种微电子器件制造技术，可将至少一个微电子芯片设置在微电子组件芯部至少一个开口中，并用封装材料将微电子芯片组/单个片固定在开口中；还可无需微电子组件芯部将至少一个微电子芯片封装在封装材料中，或固定至少一个微电子芯片到散热器中至少一个开口内。然后电介质材料和导电迹线组成的叠片互连条连接微电子芯片组/单个片到封装材料、微电子组件芯部及散热器中至少一个上，形成微电子器件。

Description

具有无凸块的叠片互连层的微电子组件
技术领域
本发明涉及制造微电子器件的装置和工艺。具体地，本发明涉及一种制造技术，可封装至少一个微电子芯片和提供叠片互连层以实现电接触。
背景技术
高性能，低成本和日益微型化的集成电路元件和具有更高封装密度的集成电路是计算机工业正在实现的目标。当这些目标实现时，微电子芯片变得更小。当然，更高封装密度的目标要求整个微电子芯片组件等于或稍大于(大约10％到30％)微电子芯片本身的尺寸。这样的微电子芯片封装称作“芯片级封装”或“CSP”。
如图35所示，实际的CSP涉及在微电子芯片402的有效表面404上直接制造组装层。组装层包括设置在微电子芯片有效表面404上的电介质层406。导电迹线408可在电介质层406上形成，其中各导电迹线408的一部分至少要接触有效表面404上的一个触点412。外触点，如与外部元件(未显示)接触的焊球或导电极，可制造成与至少一个导电迹线408电接触。图35显示出外触点，如焊球414，其被电介质层406上的焊接掩膜材料416包围。但是，在这种实际CPS情况下，对某些类型的微电子芯片(如逻辑芯片)，微电子芯片有效表面404提供的表面区通常不能提供足够的需要与外部元件(未显示)接触的全部外触点使用的表面。
额外的表面区域可以通过使用插入件(interposer)，比如基片(基本上为刚性材料)或柔性件(基本上为柔性材料)来提供。图36显示了具有微电子芯片424的基片插入件422，芯片424通过小焊球428连接到并电接触基片插入件422的第一表面426。小焊球428在微电子芯片424上的触点432和基片插入件的第一表面426之间延伸。导电迹线434通过通道442不连续地与基片插入件422的第二表面438上的结合片436电接触。外触点444(显示为焊球)在结合片436上形成。外触点444用于实现微电子芯片424和外电子系统(未显示)之间的电连通。
使用基片插入件422要求许多的工艺步骤。这些工艺步骤增加了组件的成本。另外，使用小焊球428带来了拥挤问题，这可能导致小焊球428之间短路，和使微电子芯片424和基片插入件之间插入底层充填材料以防止污染和提供机械稳定出现困难。此外，由于基片插入件422的厚度，目前的组件不能满足另外的微电子芯片424的能量传送要求，这使得连接区侧的电容具有过高的电感。
图37显示了柔性元件插入件452，其中微电子芯片456的有效表面454通过粘结剂层462连接到柔性元件插入件452的第一表面458。微电子芯片456封装到封装材料464中。柔性元件插入件452通过激光切割形成开口，其穿过柔性元件插入件452到达微电子芯片有效表面454上的触点466和位于柔性元件插入件452中选择的金属片。导电金属层在柔性元件插入件452的第二表面472上和在开口中形成。导电金属层通过标准的光掩膜/蚀刻工艺形成图案，形成了导电通道474和导电迹线476。外触点在导电迹线476上形成(显示为焊球248，其周围是靠近导电迹线476的焊接掩膜材料482)。
使用柔性元件插入件452要求用粘结材料层来形成柔性元件插入件452并要求将柔性元件插入件452粘结到微电子芯片456。这些粘结工艺相当的困难，增加了组件的成本。此外，发现生产的组件可靠性很差。
因此，希望能开发出新的装置和技术来提供额外的表面区域以形成用于芯片级封装的迹线，并能够克服上面讨论的问题。
附图说明
尽管本说明书要求由权利要求来特别指出和明确公布什么涉及到本发明，但本发明的优点从下面对本发明的介绍并通过参考附图进行阅读可容易地了解，其中：
图1到8是显示形成叠片互连条的方法的侧视截面图；
图9和10分别是可用于本发明实施例的组件芯部的斜视图和顶视图；
图11到19是根据本发明的制造带组件芯部的微电子组件的方法的侧视截面图；
图20和21是根据本发明的没有组件芯部的微电子组件的侧视截面图；
图22是可用于本发明一个实施例的散热器的斜视图；
图23到34是根据本发明的形成带散热器的微电子组件的各种方法的侧视截面图；
图35是现有技术的微电子器件的实际CSP的侧视截面图；
图36是现有技术的使用基片插入件的微电子器件的CSP的截面图；
图37是现有技术的使用柔性元件插入件的微电子器件的CSP的截面图。
具体实施方式
在下面的详细介绍中，要参考以说明方式来显示本发明的特定实施例的附图。非常详细地对这些实施例进行介绍，使得所属领域的技术人员能够实施本发明。应当认识到，尽管本发明的各个实施例不同，但没有必要互相排斥。例如，本文介绍的涉及一个实施例的特殊特征，结构，或特点可在另外的实施例中实施，这不会脱离本发明的精神实质和范围。另外，应当知道在各个公开的实施例中的各种元件的位置或设置可以在不脱离本发明的精神实质和范围的情况下进行改进。因此，不能认为下面进行的详细介绍是限制性的，本发明的范围只能由所附权利要求来限定，只能在得到权利要求授权的等效体的完整范围内进行适当的解释。附图中相同的数字代表这些附图中相同或类似的功能体。
本发明包括一种微电子器件制造技术，可将至少一个微电子芯片设置在微电子组件芯部中至少一个开口内，并用封装材料将微电子芯片组/单个片固定在开口中；还可无需微电子组件芯部将至少一个微电子芯片封装在封装材料中，或固定至少一个微电子芯片到散热器中至少一个开口内。然后电介质材料和导电迹线组成的叠片互连条连接微电子芯片组/单个片到封装材料、微电子组件芯部及散热器中至少一个上，形成微电子器件。
图1到8显示了形成叠片互连条的方法。如图1所示，金属箔片102，如铜、铜合金、铝、铝合金等制成的，层压到电介质层104的第一表面106，如由玻璃-环氧材料(如FR4材料)、环氧树脂、聚酰亚胺和类似材料组成的电介质层。至少一个开口108穿过电介质层104，暴露出一部分金属箔片102，如图2所示。然后对金属箔片102/电介质层104叠片进行清洗(除油)。
如图3所示，开口108(见图2)中填充了导电材料，比如用通过所属领域的技术人员都知道的电镀技术得到的金属，形成导电插塞112。如图4所示，金属箔片102然后可通过平版印刷和蚀刻技术形成图案，形成至少一个导电件，如连接区114和迹线120(未在图3显示，可见图16)。如图5所示，导电结合层116，由如锡/铅焊料、无铅焊料(如，锡/银焊料和锡/银/铜焊料)、导电粘结剂(如掺金属的环氧树脂)和类似材料组成，在导电插塞112上形成，并靠近电介质层104的第二表面118。施加导电结合层116可通过各种常用的方法，包括但不限于电镀焊料或焊料金属，丝网印刷糊状物(可是导电粘结剂或是焊料糊)，使用FurukaWa Super钎焊工艺，使用Super Juffit工艺和类似的方法。然后可设置粘结剂层122到电介质层第二表面118和导电结合层116上，形成叠层结构124，如图6所示。将多个叠层结构124，124｀和124｀｀对准，如图7所示。应当注意到叠层结构124｀有导电插塞112｀和连接区114｀，还可包括迹线120｀，迹线在电介质层104｀的相对的表面上形成，但没有导电结合层和粘结层，而相邻的叠层结构124和124｀｀上有这些层。若干单个叠层结构124、124｀和124｀｀然后进行真空热压工艺，形成叠片互连条130，如图8所示。真空热压工艺使单个叠层结构(124，124｀和/或124｀｀)的导电结合层116结合相邻的单个叠层结构的连接区(114，114｀和/或114｀｀)和迹线120｀，如图8所显示的。当然，应当认识到叠片互连条130并不限于3层，而是可包括少些或更多的层。这种叠片互连条130可从美国加利福尼亚州Santa Clara市的Ibiden U.S.A公司获得。其他的具有基本类似特征但用不同生产工艺生产的叠片互连条可从日本大阪市的Matsushita ElectronicComponents公司获得(如ALIVH，任何层内通道孔)和美国印第安纳州Elkhart市的CTS公司获得(如ViaPly)。还可以使用其他的工艺，如Ibiden的IBSS or Baby Yasha工艺技术，或者Shinko的DLL工艺技术(菲律宾马尼拉市Shinko Electric Industries公司)。在这种情况下，一般用于传统倒装晶片(flip chip)的焊料凸块会被电镀金属栓(铜或其他适当的金属或合金)代替。制造完成后，叠片互连条130可通过使用适当测试装置的电测法或其他方法对其功能进行测试。
图9到19显示了形成微电子器件的一种方法。图9显示了用于制造微电子器件的微电子组件芯部202。微电子组件芯部202最好包括基本为平面的材料。用于制造微电子组件芯部202的材料包括但不限于双马来酰亚胺三氮杂苯(BT)树脂基叠片材料、FR4叠片材料(阻燃玻璃/环氧材料)、各种聚酰亚胺叠层材料、陶瓷材料和类似材料，以及金属材料(如铜)和类似材料。微电子组件芯部202具有至少一个开口204，其从微电子组件芯部202的第一表面206延伸到微电子组件芯部202相对的第二表面208。如图10所示，开口204可具有任何形状和尺寸，包括但不限于矩形/方形204a，矩形/方形带圆角204b，和圆形204c。对开口204的尺寸和形状的唯一限制是必须有适当的尺寸和形状，以容纳相应的微电子芯片组或单个芯片，如下面将进行的讨论。
图11显示出连接保护膜212的微电子组件芯部第一表面206。保护膜212最好是柔性材料，比如Kapton聚酰亚胺膜(美国特拉华州Wilmington市的E.I.du Pont de Nemours and Company生产)，但是也可以用任何适当材料制造，包括金属膜。在优选实施例中，保护膜212与微电子组件芯部具有基本上相同的热膨胀系数(CET)。图12显示了微电子芯片214，各微电子芯片具有有效表面216和背面218，芯片放置在微电子组件芯部202的相应开口204中。微电子芯片214可以是任何已知有源或无源的器件，包括但不限于，逻辑芯片(CPUs)，存储器(DRAM，SRAM，SDRAM等)，控制器(芯片组)，电容器，电阻，电感器和类似器件。微电子芯片214最好进行电的和/或其他的测试，以便在使用之前清除丧失功能的微电子芯片。
在一个实施例(已显示)中，微电子组件芯部202的厚度217和微电子元件214的厚度215基本上相等。微电子元件215设置成其有效表面216与保护膜212连接。保护膜212上具有粘结剂，如硅树脂或丙烯酸粘结剂，连接到微电子组件芯部第一表面206和微电子元件有效表面216。施加这种粘结剂型保护膜后，可以放置微电子元件和微电子组件芯部202到模具、液体分配封装系统(优选)、真空压力机、或其他进行封装工艺的设备中。保护膜212还可以是无粘结剂膜，如乙烯基-四氟乙烯(ETFE)或特氟纶(Teflen)膜，通过进行封装工艺的模具或其他设备的内表面，膜保持在微电子芯片有效表面216和微电子组件芯部第一表面206上。在另一实施例中，微电子芯片214和微电子组件芯部202可以保持在相对可重复使用的压板的适当位置(通过粘结剂、真空吸力或其他方式)，压板位于带状膜上。
然后用封装材料222对微电子芯片214进行封装，可用塑料、树脂、环氧树脂、弹性体(如橡胶)材料，和类似材料。如图13所示，封装材料222施加到开口204中未被微电子芯片214占据的部分。微电子芯片214的封装可通过任何工艺来实现，包括但不限于，传递模塑法及压缩模塑法和挤压。封装材料222将微电子芯片214固定在微电子组件芯部202中，使形成的结构具有机械刚度并提供了下一步连接叠片互连条的表面区。
封装后去除保护膜212，如图14所示，使微电子芯片有效表面216暴露。还如图14所示，封装材料222最好通过模压或挤压来充填微电子组件芯部第一表面206和微电子芯片有效表面216之间的空间。这样可导致封装材料222的至少一个表面224基本上与微电子芯片有效表面216和微电子组件芯部第一表面206在同一平面。
图15显示了被封装材料222封装在微电子组件芯部的单个微电子芯片214的视图。微电子芯片214当然包括多个位于微电子芯片有效表面216的电触点232。电触点232电连接到微电子芯片214内的电路(未显示)。为了简单和清楚起见，只显示了4个电触点232。
如图16所示，叠片内连条130(优选)对接并电接触电触点232。为了与嵌入的微电子芯片形成机械连接和电连接，在叠片内连条130和嵌入的微电子芯片之间的层必须包括适当的电介质材料230(比如玻璃-环氧材料，如FR4材料；环氧树脂，聚酰亚胺和类似材料)和导电粘结剂材料240(比如，掺金属环氧树脂和类似材料)。在优选实施例中，这些粘结剂材料将在形成叠片内连条130的叠层后施加。取决于对准的情况，可以将迹线放在对接微电子芯片214的表面上。如果不能将迹线放置到对接微电子芯片214的表面上，叠片内连条130将在朝向微电子芯片214的侧面不设置迹线。
如图17所示，在连接叠片内连条130后，连接区114可用于形成导电内连接，比如焊料凸块，焊球，销和类似构件；以连通外部元件(未显示)。例如，焊接掩膜材料252可设置在叠片内连条130上。多个通道然后在焊接掩膜材料252上形成，暴露至少一部分连接区114或迹线120。多个导电凸块258，如焊料凸块，可通过丝网印刷焊接糊状物，然后进行回流焊工艺；或通过已知的电镀技术，在各个连接区114或迹线120上的暴露部分形成。
图18显示了多个用封装材料222封装在微电子组件芯部202中的微电子芯片214。叠片内连条130通过前面讨论过的方式连接到微电子芯片有效表面216，微电子组件芯部第一表面206，和封装材料表面224。各个微电子芯片214然后沿穿过叠片内连条130和微电子组件芯部202的线264(切割)单个化，形成至少一个单个化的微电子芯片组件266，图19所示。还应当认识到，各个微电子芯片214可以首先进行单个化，再连接单个化的互连条130，这样将消除芯片对芯片的对准问题，直接形成单个微电子芯片组件266。
在优选的实施例中，已知优良(即，经过电的或其他的装置测试的)的微电子元件214可结合到微电子组件芯部202中对应于已知优良的叠片内连条130的位置。因此，由于连接到丧失功能的叠片内连条130而损失已知优良的微电子元件214的情况可得到避免。应当认识到，微电子芯片组件还可以通过连接各单个叠片连接条到各个封装的单个微电子元件来形成。
当然，还应当认识到多个微电子元件214可用封装材料222封装到微电子组件芯部202的单个开口204中。
还应当认识到，微电子组件芯部202不是必需的。微电子芯片214可简单地封装在封装材料222中，如图20所示。各个芯片214然后沿穿过叠片互连条130和封装材料222的线268(切割)进行单个化，形成至少一个单个微电子芯片组件270，如图21所示。还应当认识到，各个微电子芯片214可以首先单个化，再连接单个化的互连条130，这样可消除芯片对芯片的对准问题，直接形成单个微电子芯片组件270。
在本发明的另一个实施例中，可将散热器302结合到微电子芯片组件。图22显示了可用于制造微电子组件的散热器302。散热器302最好包括基本上共面的高导热材料。用于制造散热器302的材料可包括但不限于金属，如铜、铜合金、钼、钼合金、铝、铝合金和类似金属。用于制造散热器的材料还可以包括但不限于，导热陶瓷材料，比如AlSiC，AlN和类似陶瓷。还应当认识到，散热器302可能是更复杂的装置，如热管。散热器302具有至少一个凹进部分304，其从第一表面306延伸到散热器302中。图23显示了散热器302的侧视截面图。各个凹进部分304由至少一个侧壁308和基本上平面的底表面3121形成，侧壁可以是斜面以帮助对准微电子芯片。尽管图22到23显示了具有基本上斜面的凹进部分侧壁308的散热器凹进部分304，应当认识到也可以使用基本上垂直的侧壁。
图24显示了微电子芯片314，其具有有效表面316和背面318，芯片设置在对应的散热器凹进部分304中(见图23)，其中凹进部分304具有适当的尺寸和形状，以容纳微电子芯片314。在微电子芯片314和散热器302上的基准符号(未显示)可用来对准。在图24显示的实施例中，微电子芯片314用导热粘结剂材料322连接到凹进部分304的底表面312。粘结剂材料322可包括树脂或掺有导热颗粒材料的环氧材料，比如氮化银或铝。粘结剂材料322还可包括具有低熔点温度的金属和金属合金(如钎焊材料)，和类似材料。
在另一个实施例中，使用了自对准钎焊工艺来连接微电子芯片314到凹进部分的底表面312。图25到29显示了自对准钎焊工艺，将微电子芯片简单和精确地放置到散热器凹进部分304中，同时在微电子芯片314和散热器302之间提供传导热。如图25所示，在微电子芯片314进行切割前，使第一批多个焊料凸块332，可以是高导热材料如铅、锡、铟、镓、铋、镉、锌、铜、金、银、锑、锗和其合金，最好是金/硅共晶材料，跨越整个晶片形成。这样保证了第一批多个焊料凸块332在所有的微电子芯片314上具有相同的位置，可降低成本。第一批多个焊接凸块332可与晶片前侧面上的特征，如基准符号(未显示)对准。
施加第一批多个焊料凸块332可通过首先设置润湿层334，如在所述领域内称为晶种层，到对应微电子芯片背面318的晶片背面。可取下的焊接挡片，如光阻材料，在整个润湿层334上形成图案，以防止第一批多个焊料凸块332的焊料过早地润湿整个润湿层334。第一批多个焊料凸块332可通过电镀技术形成，或通过丝网印刷糊状物到光阻材料的开口中，然后回流焊接糊状物形成焊料凸块。
如图26所示，第二批多个焊料凸块338可以通过上面介绍的技术设置，利用润湿层342和可取下的焊接挡片344，施加到散热器凹进部分304的底表面312。第二批多个焊料凸块338可以用上面所介绍的制造第一批多个焊料凸块所用材料来制造。第二批多个焊料凸块338可以与散热器302上的特征，如基准符号(未显示)对准。为节省费用和简化工艺，第一批多个焊料凸块332或第二批多个焊料凸块338还可以不设置，只是在对应的表面上施加润湿层和带图案的焊料层。
如图27所示，微电子芯片314(切割后)设置在散热器凹进部分304中，其中第一批多个焊料凸块332和第二批多个焊料凸块338在希望的位置与微电子芯片对准。第一批多个焊球332和第二批多个焊球338可以在初始对准和最后热接触时有不同的尺寸和成分。当然，还应认识到，可以只向微电子芯片314或散热器凹进部分304设置焊料凸块。
将散热器302加热到第一批多个焊料凸块332和第二批焊料凸块338的熔点或熔点以上，进行回流焊接，其中在与微电子芯片314对准的焊料凸块之间发生毛细管作用。然后取下微电子芯片上可取下的焊接挡片336和散热器上可取下的焊接挡片344，比如可通过所属领域都知道的光阻材料剥离工艺进行。接下来，如图28所示，压板346设置到微电子芯片有效表面316，以将微电子芯片314保持在水平的位置，在真空或部分真空条件下同时垂直下压和加热，再次对第一批多个焊球332和第二批多个焊球338的焊料进行回流。在这个过程中，任何水平相对运动通过沿方向350垂直下压而避免。保持该压力直到焊料冷却到低于熔化温度。这样将导致在微电子芯片背面318和凹进部分底表面312之间产生基本连续的热接触焊接层352，如图29所示。真空或部分真空有助于防止或减少基本连续热接触焊接层352中气泡的产生。使用压板346(见图28)还可使散热器顶表面306和微电子芯片有效表面316基本共面，如图29所示。
如前面所讨论的，叠片互连条然后连接到微电子芯片有效表面316和散热器第一表面306，如图30所示。各个微电子芯片然后可以通过叠片互连条130和散热器302进行单个化，形成至少一个单个微电子芯片组件320，如图31所示。还应认识到，各个微电子芯片314可以先单个化，再将单个化的叠片互连层130连接其上，这样可消除芯片对芯片对准的问题，直接形成单个的微电子芯片组件320。
在另一个实施例中，充填材料372，比如塑料、树脂、环氧树脂、和类似材料，可填充到任何微电子芯片314和凹进部分侧壁308之间的间隙中，形成在微电子芯片有效表面316和散热器第一表面306之间的填充材料372的共面表面374，如图32所示。这也可以通过设置带状膜376到微电子芯片有效表面316和散热器第一表面306上来实现，如图33所示。带状膜376最好基本是柔性的材料，比如Kapton聚酰亚胺膜(美国特拉华州Wilmington市E.I.du PontdeNemours and Company公司生产)，也可以用任何适当的材料，包括金属膜，其上设置粘结剂，比如硅树脂。充填材料372(未显示)通过至少一个从散热器第二表面延伸到凹进部分侧壁308的通道378注入。
清除带状膜376，如前所讨论的，然后将叠片互连条130连接到微电子芯片有效表面316和散热器第一表面306。各个微电子芯片314然后通过叠片互连条130和散热器302进行单个化，形成至少一个单个微电子芯片组件386，如图34所示。还应当知道，各个微电子芯片314可先进行单个化，然后再连接单个化叠片互连条130，这样可减少芯片对芯片对准的问题，直接形成单个的微电子芯片组件386。
在另一个实施例中，叠片互连条130可以首先连接到微电子芯片314和散热器302。然后可通过通道378引入封装材料372到叠片互连条130和微电子芯片314，及散热器302之间的间隙中。
由于微电子组件变薄，本发明在连接区侧电容形成低电感。此外，由于不必要在微电子芯片表面设置焊料凸块，故具有可量测性。此外，由于不需要进行复杂的组装，可实现节约成本。
从而，已经对本发明的优选实施例进行了介绍，应当认识到被所附的权利要求限定的本发明不受上述介绍中的具体细节的限制，在不脱离本发明的实质精神和范围的情况下可进行许多明显的改进。

Claims (31)

1.一种微电子组件，包括：
微电子芯片，具有有效表面和至少一个侧面；
封装材料，靠近所述至少一个微电子芯片侧面，其中所述封装材料包括至少一个基本上与所述微电子芯片有效表面共面的表面；和
叠片互连条，靠近所述微电子芯片有效表面和所述封装材料表面设置，所述叠片互连条与所述微电子芯片有效表面电接触。
2.根据权利要求1所述的微电子组件，其特征在于，所述叠片互连条包括：
至少一层电介质材料，具有第一表面和第二表面；
至少一个导电插塞，从所述第一表面延伸到所述第二表面；和
至少一个导电件，设置在所述电介质材料第一表面，与所述至少一个导电插塞接触。
3.根据权利要求2所述的微电子组件，其特征在于，所述叠片互连条的至少一个导电插塞通过分布在其间的导电粘结剂电连接到所述微电子芯片有效表面上至少一个电触点，电介质材料设置在所述叠片互连条和所述微电子芯片有效表面之间靠近所述导电粘结剂的区域。
4.一种制造微电子组件的方法，包括：
准备至少一个微电子芯片，其具有有效表面和至少一个侧面；
在所述至少一个微电子芯片有效表面上连接保护膜；
靠近所述至少一个微电子芯片侧面的封装材料封装所述至少一个微电子芯片，其中，所述封装材料包括至少一个基本上与所述微电子芯片有效表面共面的表面；
清除所述保护膜；
靠近所述微电子芯片有效表面和所述封装材料表面设置叠片互连条，所述叠片互连条与所述微电子芯片有效表面电接触。
5.根据权利要求4所述的方法，其特征在于，在所述微电子芯片有效表面上设置所述叠片互连条还包括用导电粘结剂连接所述叠片互连条的导电插塞到所述微电子芯片有效表面的电触点。
6.一种微电子组件，包括：
微电子组件芯部，具有第一表面和相对的第二表面，所述微电子组件芯部具有至少一个开口，其从所述微电子组件芯部第一表面延伸到所述微电子组件芯部第二表面；
至少一个微电子芯片，设置在所述至少一个开口中，所述至少一个微电子芯片具有有效表面；
封装材料，粘结所述微电子组件芯部和所述至少一个微电子芯片；和
叠片互连条，靠近所述微电子芯片有效表面和所述微电子组件芯部设置，所述叠片互连条与所述微电子芯片有效表面电接触。
7.根据权利要求6所述的微电子组件，其特征在于，所述微电子组件芯部包括从由双马来酰亚胺三嗪系树脂基叠片材料，FR4叠片材料，聚酰亚胺叠片材料，陶瓷和金属组成的一组材料中选出的材料。
8.根据权利要求6所述的微电子组件，其特征在于，所述封装材料还包括至少一个表面，与所述微电子芯片有效表面和所述微电子封装芯片第一表面共面。
9.根据权利要求6所述的微电子组件，其特征在于，所述叠片互连条包括：
至少一层电介质材料，具有第一表面和第二表面；
至少一个导电插塞，从所述第一表面延伸到所述第二表面；和
至少一个导电件，设置在所述电介质材料第一表面，与所述至少一个导电插塞接触。
10.根据权利要求9所述的微电子组件，其特征在于，所述叠片互连条的至少一个导电插塞通过设置在中间的导电粘结剂电连接至少一个所述微电子芯片有效表面上的电触点，电介质材料设置在所述叠片互连条和所述微电子芯片有效表面之间靠近所述导电粘结剂的区域。
11.一种制造微电子组件的方法，包括：
准备微电子组件芯部，其具有第一表面和相对的第二表面，所述微电子组件芯部具有至少一个开口，其从所述微电子组件芯部第一表面延伸到所述微电子组件芯部第二表面；
设置至少一个微电子芯片到所述至少一个开口，所述至少一个微电子芯片具有有效表面；
用封装材料连接所述微电子组件芯部和所述至少一个微电子芯片；和
靠近所述微电子芯片有效表面和所述封装材料表面设置叠片互连条，其中所述叠片互连条与所述微电子芯片有效表面电接触。
12.根据权利要求11所述的方法，其特征在于，相对所述微电子芯片有效表面设置所述叠片互连条还包括用导电粘结剂连接所述叠片互连条的导电插塞到所述微电子芯片有效表面的电触点。
13.根据权利要求11所述的方法，其特征在于，所述准备微电子组件芯部包括提供从由双马来酰亚胺三嗪系树脂基叠片材料、FR4叠片材料、聚酰亚胺叠片材料、陶瓷和金属组成的一组材料中选出的材料制成的微电子组件芯部。
14.根据权利要求11所述的方法，其特征在于，所述方法还包括在用封装材料粘结所述微电子组件芯部到所述至少一个微电子芯片之前，在所述微电子组件芯部第一表面和所述微电子芯片有效表面上连接保护膜。
15.根据权利要求11所述的方法，其特征在于，在用封装材料粘结所述微电子组件芯部到所述至少一个微电子芯片前，在所述微电子组件芯部第一表面和所述微电子芯片有效表面连接保护膜包括连接所述微电子组件芯部第一表面和所述微电子芯片有效表面到所述保护膜的粘结剂层。
16.一种微电子组件，包括：
具有第一表面的散热器，所述散热器具有至少一个凹进部分，所述凹进部分由至少一个从所述散热器第一表面延伸到凹进部分底表面的侧壁形成；
至少一个微电子芯片，设置在所述至少一个凹进部分中，所述至少一个微电子芯片具有有效表面，背面和至少一个侧面；
导热材料，其连接所述至少一个微电子芯片背面到所述凹进部分底表面；和
叠片互连条，靠近所述微电子芯片有效表面和所述散热器设置，所述叠片互连条与所述微电子芯片有效表面电接触。
17.根据权利要求16所述的微电子组件，其特征在于，所述叠片互连条包括：
至少一层电介质材料，具有第一表面和第二表面；
至少一个导电插塞，从所述第一表面延伸到所述第二表面；和
至少一个导电件，设置在所述电介质材料第一表面，与所述至少一个导电插塞接触。
18.根据权利要求17所述的微电子组件，其特征在于，所述叠片互连条的至少一个导电插塞电连接到所述微电子芯片有效表面上的至少一个电触点。
19.根据权利要求16所述的微电子组件，其特征在于，所述组件还包括填充材料，设置在所述至少一个凹进部分侧壁和所述至少一个微电子芯片侧面之间的间隙。
20.根据权利要求16所述的微电子组件，其特征在于，所述导热材料从树脂、环氧树脂、金属和金属合金等组成的一组材料中选出。
21.根据权利要求16所述的微电子组件，其特征在于，所述至少一个凹进部分侧壁基本上是斜面。
22.一种制造微电子组件的方法，包括：
准备散热器，其具有第一表面，所述散热器具有至少一个凹进部分，所述凹进部分由至少一个从所述散热器第一表面延伸到凹进部分底表面的侧壁形成；
设置至少一个微电子芯片到所述至少一个凹进部分中，所述至少一个微电子芯片具有有效表面，背面和至少一个侧面；
粘结所述至少一个微电子芯片背面到所述凹进部分底表面；和
靠近所述微电子芯片有效表面和所述微电子组件芯部设置叠片互连条到，其中所述叠片互连条与所述微电子芯片有效表面电接触。
23.根据权利要求22所述的方法，其特征在于，相对所述微电子芯片有效表面设置所述叠片互连条还包括用导电粘结剂连接所述叠片互连条的导电插塞到所述微电子芯片有效表面的电触点。
24.根据权利要求22所述的方法，其特征在于，所述方法还包括设置填充材料到所述至少一个凹进部分侧壁和所述至少一个微电子芯片侧面之间的间隙。
25.根据权利要求22所述的方法，其特征在于，将所述至少一个微电子芯片背面连接到所述凹进部分底表面包括用导热材料连接所述至少一个微电子芯片背面到所述底表面，所述导热材料从由掺有特殊导热材料的树脂材料和掺有特殊导热材料的环氧树脂材料组成的材料组中选出。
26.根据权利要求22所述的方法，其特征在于，将所述至少一个微电子芯片背面连接到所述凹进部分底表面包括用导热材料连接所述至少一个微电子芯片背面到所述底表面，所述导热材料从由金属和金属合金组成的材料组中选出。
27.根据权利要求22所述的方法，其特征在于，将所述至少一个微电子芯片背面连接到所述凹进部分底表面包括：
设置多个焊料凸块到所述至少一个微电子芯片背面和所述凹进部分底表面中至少一个上；和
通过回流焊所述多个第一焊料凸块和所述多个第二焊料凸块，在所述至少一个微电子芯片背面和所述凹进部分底表面之间形成基本上连续的焊接层。
28.根据权利要求27所述的方法，其特征在于，设置多个焊料凸块包括：
在所述至少一个微电子芯片背面形成焊接阻挡材料图案；和
形成在所述焊接阻挡材料中分布的所述多个焊料凸块。
29.根据权利要求27所述的方法，其特征在于，设置多个焊料凸块包括：
在所述凹进部分底表面上形成焊接阻挡材料图案；和
形成在所述焊接阻挡材料中分布的所述多个焊料凸块。
30.根据权利要求27所述的方法，其特征在于，在所述至少一个微电子芯片背面和所述凹进部分底表面中的至少一个上设置多个焊料凸块包括：
在所述至少一个微电子芯片背面设置多个第一焊料凸块包括在所述至少一个微电子芯片背面形成焊接阻挡材料图案；和形成所述多个在所述焊接阻挡材料中分布的焊料凸块；
在所述凹进部分底表面设置多个第二焊料凸块包括在所述凹进部分底表面上形成焊接阻挡材料图案；和形成所述多个在所述焊接阻挡材料中分布的焊料凸块；和
在所述至少一个微电子芯片背面和所述凹进部分底面之间形成基本上连续的焊接层包括：
回流焊所述多个第一焊料凸块和所述多个第二焊料凸块，使所述至少一个微电子芯片在所述凹进部分中对齐；
清除所述至少一个微电子芯片背面和所述凹进部分底表面上的焊接阻挡材料；和
保持所述至少一个微电子芯片在适当位置，同时对所述第一焊料凸块和所述多个第二焊料凸块再进行回流焊。
31.根据权利要求30所述的方法，其特征在于，所述方法还包括在形成所述基本连续焊接层时至少局部引入真空。
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