CN1545800A - 多媒体信号处理系统 - Google Patents
多媒体信号处理系统 Download PDFInfo
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Abstract
一种多媒体信号信息系统(图15),具有允许用户观看并立即回顾以前的节目材料的存储器(1505),该系统可以在观看或查看另一节目材料的同时储存节目,并可以接收来自不同来源(1406,1503,1505)的输入信号,普遍适用于多种不同的市场,例如数字卫星、数字有线以及模拟市场。
Description
技术领域
本发明涉及录制电视广播信号过后观看(time shifting)。更具体地讲,本发明涉及电视广播信号的实时捕获、储存、以及播放。
背景技术
录像机(VCR)在全球范围内改变了电视(TV)观众的生活。VCR为观众根据其生活方式、录制电视节目过后观看提供了便利。
观众使用VCR将电视节目储存在磁带上。使用VCR,观众就可以播放、倒带、快进、以及暂停所储存的节目材料。利用这些功能,观众就可以根据需要随时暂停在要看的节目上,快速翻过不想看的节目材料或商业节目,以及重放喜欢的画面。但VCR不能同时捕获并播放信息。
这一问题的解决办法之一是使用多个VCR。例如,如果有两台磁带录像机,这两台磁带录像机之间就可以进行往复式工作。在这种情况中,在喜欢节目的开始,启动第一台录像机。如果观众希望倒回广播内容,当第一台录像机停止,倒回到合适位置并播放开始的节目时,第二台录像机开始记录。然而,如果观众希望快进到初次请求倒带的时刻,则至少需要第三台录像机。在这种情况中,当第二台录像机停止并倒回到适当位置时,第三台录像机开始记录广播流。如果继续这种操作,人们会很快发现设备使用不便、不可靠、昂贵,且很难操作,同时也无法支持所有希望的功能。此外,录像带的长度有限,可能会在不合适的时间用完,这就大大降低了这种解决方案的价值。
目前,已有人提出使用数字计算机系统解决这一问题。1994年12月6日向Logan等人授权的专利号为5,371,551的美国专利,披露了一种同时进行视频录制和播放的方法。它提供了一种微处理器控制的广播和播放设备。所述装置将视频数据压缩并储存在硬盘上。然而,由于要求处理器速度要跟得上高速视频速度,而使设备成本昂贵且容易出现问题,所以这种方法很难实现。微处理器的速度必须非常快才能跟得上输入与输出视频数据的速度。
这样,就非常有必要提供一种使用户能够同时记录和播放电视广播节目的多媒体信号处理系统。更有必要地是,提供一种多媒体信号处理系统,该多媒体信号处理系统采用将微处理器从高速视频数据率事务中解脱出来的方法,从而最大程度上降低微处理器和系统要求。
发明内容
本发明提供了一种多媒体信号处理系统。本发明使用了一种易于操作、低成本的多媒体存储器和显示系统,允许用户观看电视广播节目时可以选择立刻回顾节目中的过去的画面。此外,利用本发明,在同时观看或回顾其它节目的同时,用户可储存所选择的电视广播节目。
本发明的优选实施例可接受多种格式的电视(TV)输入流,例如NTSC(National Television Standards Committee,国家电视制式委员会制式)或PAL(逐行倒相彩色电视制)制式广播的模拟格式,以及如DSS(Digital Satellite System,数字卫星系统)、DBS(DigitalBroadcast Services,数字广播业务),或ATSC(Advanced TelevisionStandards Committee,先进电视标准委员会)的数字格式。模拟电视流被转换为MPEG(Moving Pictures Experts Group,运动图像专家组)格式流,用于内部转换和操作,而从数字电视信号中提取出来的预先格式化的MPEG流,以与所编码的模拟流相似的格式呈现。
本发明会对所产生的MPEG流进行分析,并将其分为视频分量与音频分量。然后将分量储存到临时缓冲器(buffer,也称缓存器)中。指示发现的分量类型、位置、时间的事件会被记录下来。会通知程序逻辑已发生了某一事件,并从缓存中提取数据。
分析器和事件缓存器使CPU从分析MPEG流和分析数据流的实时特性的事务中解脱出来。这样,系统就允许采用更低速率的CPU和总线速度,从而可降低系统成本。
视频分量与音频分量被储存在存储设备上。当请求播放节目时,视频分量与音频分量就从存储设备提取出来并重新组成MPEG流。MPEG流被送到解码器。解码器将MPEG流转换为电视输出信号,并将电视输出信号传送到电视接收机。
用户的控制命令可被接受并通过系统发送。这些命令会影响所述MPEG流,并允许用户至少使用以下功能观看存储的节目:倒退、快进、播放、暂停、索引、快速/慢速倒播,以及快速/慢速播放。
而且,本发明采用通用系统体系结构,这就能以多种配置实现本发明,每一种均可以进行调整以接收来自不同来源的输入信号。在最高一层,系统面板包括输入部分和输出部分,其中输出部分包括核心功能部件。在所有的配置中,输出部分实际上基本相同,包括三个核心部件(可以作为三个分离的芯片或一个芯片组),而根据信号类型和信号源,输入部分会有所变化。在这种方式中,可以实现多种配置,每一种只需要对系统面板进行少量修改。这种系统体系结构使设计工作得以简化,并降低了为不同市场(例如数字卫星、数字电缆、以及数字电缆)生产不同产品的制造风险。
本发明输出部分的核心部件,包括:CPU,主要功能为初始化和控制其它系统硬件部件;MPEG-2解码器/图形子系统,与CPU相连,主要负责对来自输入部分的传送流进行解码;以及媒体管理器,它与MPEG-2解码器/图形子系统相连,具有包括媒体处理、高速传送输出以及其它I/O功能等的多种功能。本发明进一步包括:输入部分与输出部分之间的传送流接口;多个存储部件;一个或多个用于储存输入信号的分离的音频分量与视频分量的大容量存储设备;以及在本发明的多个系统部件之间传送数据的系统总线。结合附图、图解,通过对本发明的原理的以下详细说明,本发明的其它特点与优点将变得更加清楚。
附图说明
图1为根据本发明的本发明优选实施例的高级方框示意图;
图2为根据本发明,使用多个输入和输出模块的本发明优选实施例的方框示意图;
图3为根据本发明的运动图像专家组(Moving Pictures ExpertsGroup,MPEG)数据流及其视频分量与音频分量的示意图;
图4为根据本发明的媒体切换器中的一个分析器以及四个直接存储器存取(DMA)输入引擎的框图;
图5为根据本发明的封装单位流(PES)缓存分量的示意图;
图6为媒体切换器输出循环缓存中已分析的分量的PES缓存结构示意图;
图7为根据本发明的媒体切换器以及与之连接的多个部件的方框示意图;
图8为根据本发明的高级程序逻辑概念方框示意图;
图9为根据本发明的程序逻辑的层次分类方框示意图;
图10为根据本发明的本发明的片断缓存部分(clip cachecomponent)优选实施例的方框示意图;
图11为根据本发明的模拟广播演播室视频混合器的本发明优选实施例的方框示意图;
图12为根据本发明的隐藏式字幕(closed caption,简称CC字幕)分析器的方框示意图;
图13为根据本发明将VCR作为本发明整体部件的本发明优选实施例高级方框示意图;
图14为根据本发明的系统体系结构的高级方框示意图;
图15为根据本发明的图14的系统输出部分的方框示意图;
图16为根据本发明的适合接收模拟信号的图14的系统输入部分的第一种形式的方框示意图;
图17为根据本发明的适合接收数字卫星信号的图14的系统输入部分的第二种形式的方框示意图;
图18为根据本发明的适合接收数字有线信号的图14的系统输入部分的第三种形式的方框示意图;
图19为根据本发明的图14的系统的第一实施例的方框示意图;
图20为根据本发明的图14的系统的第二实施例的方框示意图;
图21为根据本发明的图14的系统的第三实施例的方框示意图;以及
图22为根据本发明的并行处理多通路媒体流的系统方框示意图。
具体实施方式
本发明具体体现为一种多媒体信号处理系统。根据本发明的系统提供了一种使用户能够观看电视广播节目的多媒体存储器以及显示系统,用户可以选择立刻回顾节目中以前的画面。此外,本发明使用户在观看或回顾另一个节目的同时能够储存所选电视广播节目,以及利用至少以下功能查看所存储的节目:倒带、快进、播放、暂停、索引、快速/慢速倒放,以及快速/慢速播放。
参照图1,本发明的优选实施例具有:输入部分101;媒体切换器102;以及输出部分103。输入部分101可接收多种格式的电视(TV)输入流,例如(美)国家电视制式委员会制式(NTSC)或逐行倒相彩色电视制式(PAL)广播,以及诸如数字卫星系统(DSS)、数字广播业务(DBS)、或先进电视标准委员会(ATSC)的数字制式。DBS、DSS、以及ATSC均基于称作运动图像专家组(Moving Pictures Experts Group 2,MPEG2)和MPEG2传送标准。MPEG2传送标准用于格式化来自电视源发射机的数字数据流,以便电视接收机能够分解输入流以在多路复用信号中找到节目。输入部分101产生MPEG流。MPEG2多路传输在同一广播信道中支持带有多个视频和音频馈送及专用数据的多套节目。输入部分101将信道调谐到某一特定节目,从中提取出特定MPEG节目,并将其馈送到系统的其它部分。使用分离的视频和音频解码器,将模拟电视信号编码为类似MPEG的格式,这样,系统的其它部分并不知道信号是如何取得的。信息(除视频和音频信号以外的信息)可以调制为多种标准方式的模拟电视信号垂直消隐间隔(Vertical BlankingInterval,VBI);例如,可以使用NABTS(North American BroadcastTeletext Standard,北美广播图文电视标准)标准将信息调制到NTSC信号的第10线至第20线上,而FCC将第21线强制用于CC字幕(Closed Caption),以及EDS(Extended Data Services,扩展数据服务)使用。这种信号由输入部分解码,并被传送到其它部分,它们就如同经MPEG2专用数据信道传送一样。
媒体切换器102起到微处理器CPU 106、硬盘或存储装置105以及内存104之间的中介作用。输入流被转换为MPEG流,并被传送到媒体切换器102。媒体切换器102将MPEG流缓存到存储器。如果用户正在观看实时电视节目,则其然后执行两步操作:将数据流传送到输出部分103,并同时将其写入硬盘或存储装置105。
输出部分103将MPEG流作为输入,并按照NTSC、PAL或其它需要的电视标准,生成一种模拟电视信号。输出部分103包括MPEG解码器、屏上显示(OSD)生成器、模拟电视编码器、以及音频逻辑。OSD生成器允许程序逻辑提供将被重叠在产生的模拟电视信号上的图像。另外,输出部分能够将程序逻辑提供的信息以多种标准格式(包括NABTS、CC、以及EDS)调制到输出信号的VBI。
参照图2,本发明易于扩展以容纳多个输入部分(调谐器)201、202、203、204,每个输入部分都能够被调谐到不同类型的输入。同样,也可以增加多个输出模块(解码器)206、207、208、209。采用多个解码器,可以实现多种特殊效果(例如,画中画)。媒体切换器205可在用户正在观看其它节目的同时记录某一节目。这就意味着在另一数据流被存储于硬盘的同时,可以从硬盘中提取出某一数据流。
参照图3,输入MPEG流301被交叉分为视频302、305、306以及音频303、304、307片段。这些单元必须被分离,并重组生成分离的视频308以及音频309流或缓冲。之所以这样做,是因为要使用分离的解码器将MPEG单元转换回音频或视频模拟分量。这种分离传送需要生成时序信息,这样解码器就可以与精确播放信号准确同步。
媒体切换器能够使用程序逻辑将正确的时序信息与每一片段关联起来,如果可能,将其直接嵌入到数据流中。每个片段的时序信息称为时间戳(time stamp)。这些时间戳单调增加,每次系统启动时从零开始。这就使本发明能够在任何特定视频片段中找到特定位置。例如,如果系统需要读取5秒正在缓存的连续输入视频流,则系统仅需要开始向前读取该视频流,并查找适合的时间戳。
可以对存储的文件执行二分搜索(binary search)以找出数据流。每个数据流均储存为一序列固定大小的片段,由于具有相同的时间戳,所以能够快速进行二分搜索。如果用户希望在节目中间开始,系统则对储存的片段进行二分搜索,直到找出合适的点,这可以以最小的信息量取得希望的结果。如果信号改为以MPEG流的形式进行储存,则需要从开头对数据流进行线性分析,以找到希望的位置。
参见图4,媒体切换器包括4个输入直接存储器存取(DirectMemory Access,DMA)引擎402、403、404、405,每个DMA引擎均有一个相关联的缓存410、411、412、413。理论上,每个DMA引擎具有:指针406;该指针的界限407;下一指针408;以及下一指针409的界限。每个DMA引擎专用于一个特定类型的信息,例如视频402、音频403、以及已分析事件405。缓存410、411、412、413循环收集特定的信息。DMA引擎将放入相关缓存的指针406加1,直到达到界限407,然后加入下一指针408以及界限409。将指针406和下一指针408设置为同一值,并根据相应的界限值创建循环缓冲器。下一指针408能够被设置指向一个不同的地址以提供矢量DMA。
输入流流经分析器401。分析器401对输入流进行分析,寻找指示视频、音频、或专用数据片段开始的MPEG的特殊事件。例如,当分析器401发现某一视频事件时,它会将数据流导向视频DMA引擎402。分析器401将数据进行缓存,并经视频DMA引擎402将其通过直接存储器存取(DMA)到视频缓存410中。同时,分析器401生成一个事件,并将其导向事件DMA引擎405,从而存入缓存413。当分析器401发现某一音频事件时,它就将字节流重新导向音频DMA引擎403,并生成一个事件存入事件缓存413。同样,当分析器401发现某一专用数据事件时,它就将字节流导向专用数据DMA引擎404,并将一个事件导入事件缓存413。当事件被放入事件缓存时,媒体切换器会利用中断机制通知程序逻辑。
参照图4和图5,事件缓存413由分析器401填充事件。事件缓存中的每个事件501具有:偏移量502;事件类型503;以及时间戳字段504。当每个事件放入缓存时,分析器401提供每一事件的类型和偏移量。例如,当出现某一音频事件时,事件类型字段被设置到某一音频事件,而偏移量指示了音频缓存411中的位置。程序逻辑知道音频缓存411从哪里开始以及在哪里加入偏移量,以找到数据流中的事件。地址偏移量502告诉程序逻辑下一事件发生在何处,而不是在何处结束。由于缓存了过去的事件,所以就可以找出当前事件的结束以及片段长度。
参照图5和图6,当程序逻辑被媒体切换器601中断时,程序逻辑便读取事件缓存602中积累的事件。从这些事件中,程序逻辑生成与已分析的MPEG片段615对应的一序列逻辑片段603。程序逻辑将偏移量502转换为每个片段的实际地址610,并使用最后缓存的事件,记录事件长度609。如果数据流由模拟信号编码生产,则其不包括解码器正确提供结果输出所使用的程序时间戳(Program Time Stamp,PTS)值。因此,程序逻辑就使用生成时戳504来计算每个片段的模拟PTS,并将其放入逻辑片段时间戳607。对于数字电视流,PTS值已被编码到数据流中。程序逻辑提取出该信息,并将其放入逻辑片段时间戳607。
程序逻辑继续收集逻辑片段603,直到它达到固定缓存大小。这时,程序逻辑就生成一个顺序包括这些逻辑片段603以及辅助控制信息的、称之为封装单位流(Packetized Elementary Stream,PES)605缓存的新缓存。每个逻辑片段指针604都直接指向由媒体切换器601填充的循环缓存,例如视频缓存613。这种新缓存然后被送到其它逻辑部件,这就可以以某种方式进一步处理缓存中的数据流,例如对其解码或将其写入存储介质。这样,处理器并不是将MPEG数据从存储器的一个位置复制到另一位置。由于存储器带宽与处理带宽要求降低,这就可以得到更高效经济的设计。
MPEG流转换到PES缓存的独特之处在于:如上所述,与逻辑片段相关的数据本身不需要出现在缓存中。当PES被写到存储器时,这些逻辑片段就以它们出现的逻辑顺序被写到存储介质。这就具有将数据流分量(无论它们是在视频、音频、或专用数据循环缓存中)集中到存储介质上的单个线性流数据缓存的效果。从存储介质只进行一次转换,该缓存就可以从存储介质读回,更新逻辑片段信息以与缓存606中实际位置一致。由于更高级的程序逻辑仅处理逻辑片段,所以它并不注意这种变换,这样就不需要在DRAM中的位置之间不断地复制数据,通过CPU可容易地管理流数据。
媒体切换器的特点在于能够高效、低成本地处理高数据率。它执行的功能包括:接收视频和音频数据;发送视频和音频数据;将视频和音频数据送至硬盘;以及从在低成本平台上的硬盘提取视频和音频数据。一般而言,利用DMA移动大量信息而极少受CPU干涉的能力,媒体切换器与微处理器CPU异步且自主地运行。
参照图7,媒体切换器701的输入侧与MPEG编码器703相连。此外还有MPEG音频704的专用电路,而垂直消陷期(verticalblanking interval,VBI)数据702也馈送入媒体切换器701。如果正在处理数字电视信号,则使用MPEG2传送分路器代替MPEG编码器703,并去除MPEG音频编码器704以及VBI解码器702。该分路器通过视频输入媒体切换器端口多路传输所提取的音频、视频、以及专用数据信道流。
分析器705分析来自MPEG编码器703、音频编码器704、以及VBI解码器702的输入数据,如果采用数字电视流,则分析来自传送多路分路器的输入数据。分析器705检测视频或音频流中的所有重要事件的开始、所有帧的开始、序列头的开始——程序逻辑为正确播放以及实现对数据流的特殊效果(例如,快进、回转、播放、暂停、快速/慢速播放、索引,以及快速/慢速倒放)所需了解的所有信息单位的开始。
当识别音频或视频片段,或专用数据时,分析器705就将标签707放入FIFO 706。DMA 709控制这些标签何时被取出。标签707以及片段的DMA地址被放入事件队列708中。不管是视频I-帧、视频B-帧、视频P-帧、视频PES、音频PES、序列头、音频帧,还是专用数据分组,帧类型信息均连同放置信息片段的相关循环缓存中的偏移量一起,被放置在事件队列708中。在被传送到DRAM 714后,CPU 713运行的程序逻辑开始检查循环缓存中的事件。
媒体切换器701具有连接到CPU 713和DRAM 714的数据总线711。媒体切换器701、CPU 713和DRAM 714也可以共用地址总线712。硬盘或存储装置710与媒体切换器701的一个端口相连。媒体切换器701将数据流输出到MPEG视频解码器715以及分离的音频解码器717。音频解码器717信号包括系统响应用户的遥控命令或其它内部事件生成的音频提示。混频器718对MPEG解码器输入的解码音频输出与分离的音频信号进行数字混频。合成出来的信号包括视频、音频、以及屏上显示信号,并被发送到电视716。
媒体切换器701接受8-bit数据并将其发送到硬盘,而同时它也可从硬盘提取另一数据流,并将其发送到MPEG解码器715。上述所有DMA引擎均可以同时工作。媒体切换器701能够使用FPGA(Field Programmable Gate Array,现场可编程门阵列)、ASIC、或离散逻辑电路用硬件实现。
程序逻辑并不需要分析大量数据流来查找每帧的开始,它只需在DRAM 714查看循环事件缓存,因为它能告诉每帧的开始位置以及帧的类型。这种方法对CPU 713的实时要求不强,从而可以节省大量的CPU运算能力。在任何时候,CPU 713都不用非常快。媒体切换器701已尽可能地把时间留给CPU 713,使其完成任务。分析器705和事件队列708将CPU 713从分析音频、视频、和缓存以及这些数据流的实时特性的事务中解脱了出来,从而实现了低成本。与其它方法相比,这也允许使用更低廉的存储器,使用时钟速率低得多的CPU运行环境中的总线结构。
CPU 713可以将DMA转移排队,并能在空闲时建立下一个DMA转移。这就给CPU 713留有大量时间间隔,从而服务DMA控制器709。由于允许大量等待时间,CPU 713可在较大时间窗口内响应DMA中断。不管是从MPEG2传送流提取出来的还是从模拟电视信号编码成的,MPEG流通常均使用一种称为VBR(VariableBit Rate encoding,可变比特率编码)的技术进行编码。这种技术可根据图像间的运动量改变表示图像序列所需数据量。这种技术能够大大降低信息所需的带宽,但快速运动(例如篮球比赛)序列则需要大得多的带宽进行编码。例如,休斯(Hughes)DirecTV卫星系统可采用带宽要求为1Mb/s到10Mb/s之间的任何带宽对信息进行编码,在帧与帧之间的带宽也会不同。对于任何计算机系统而言,不采用这种结构,就很难跟上如此快的变化数据率。
对于图8,CPU内的程序逻辑具有三个概念部分:数据源(source)801,转换(transform)802,以及接收器(sink)803。数据源801生成数据缓存。转换802处理数据缓存,而接收器803消耗数据缓存。转换负责对将要操作的数据进行缓存分配和排队。缓存会像“空”的一样被分配给数据源,并将其“充满”。然后,这些“充满”的缓存进行排队,并被送至接收器,而接收器将返回“空”缓存。
数据源801从编码器(例如数字卫星接收机)接受数据。它从下游转换器取得这些数据的缓存,将这些数据打包到缓存,然后如上所述将缓存推下管道。数据源对象801并不了解系统的其它部分的事件。接收器803消耗缓存:从上游转换器取出缓存,将数据发送到解码器,然后释放这些缓存用于重新使用。
这里使用两类转换802:空间转换和时间转换。空间转换是实现例如对经过的缓存数据进行图像卷积或压缩/解压的转换。当进、出系统的缓存之间没有可表示的时间关系时,则使用时间转换。这种转换将缓存写入存储介质上的文件804。该缓存晚些时间会被取出,被发送到管道,并在数据流内进行适当地排队。
参见图9,示出程序逻辑导出的C++类层次。TiVo媒介内核(Tmk)904、908、913协调操作系统内核。内核实现如下操作:内存分配,同步,以及线程处理。TmkCore 904、908、913将取自媒体内核的内存构造为对象。它提供操作者、新建和删除,用于构造和解构对象。每个对象(数据源901,转换902,以及接收器903)按定义进行多线程操作,并能并行运行。
Tmk管道类905、909、914负责系统的流量控制。管道指向流中从数据源901到接收器903的下一管道。要暂停管道,例如,将称为“暂停”的事件发送给管道中的第一个对象。该事件在管道中被中继到第二个对象,并依次向下。对于经过管道的数据,这种操作都是异步进行的。因此,类似诸如电话的应用,MPEG流的流控制是异步的,且与流本身是分离的。这样,逻辑设计便很简单,但同时也足以支持上述包括暂停、倒带、快进等其它特性。此外,由于缓存数据能够被简单地删除,解码器利用单一事件重置,此后,来自新的数据流的数据将向下传递到管道,这种结构就能够实现流来源之间快速而有效的切换。本发明需要的切换能力包括,例如切换正在输入部分捕获的信道,或在输入部分的现场信号与存储流之间进行切换。
数据源对象901是一个Tmk源906,而转换对象902是一个TmkXfrm 910对象。这些对象都是定义管道中类的标准行为的中间类。概念上,它们沿管道向下交换缓存。数据源对象901从物理数据源(例如媒体切换器)取出数据,并将其放入PES缓存。为了取得缓存,数据源对象901向其管道中的下游对象发出缓存请求(allocEmptyBuf)。阻塞源对象901,直至有了足够的存储量。这就意味着管道是自调节的;它具有自动流控制能力。当源对象901已填充完缓存时,它就通过pushFullBuf功能将缓存送回转换902。
接收器903也受到流控制。它称作nextFullBuf,告诉转换902它已做好接收下一填充缓存的准备。这种操作能够阻塞接收器903,直到缓存就绪。当接收器903结束缓存操作时(即,它已用完缓存中的数据),它就调用releaseEmptyBuf。ReleaseEmptyBuf将缓存返还给转换902。转换902然后能够将该缓存(例如)退还给源对象901以再次填充。该方法除了具有自动流控制的优点外,它还通过强制变换分配固定缓存,也限制了专用于缓存的内存数量。这是实现经济高效的有限的DRAM环境的重要特性。
MediaSwitch类909调用TmkClipCache 912对象的allocEmptyBuf方法,并从它那里接收PES缓存。它于是取得媒体切换器硬件中的循环缓存,并生成PES缓存。MediaSwitch类909将该缓存填满,并将其推送回TmkClipCache 912对象。
TmkClipCache 912在存储介质上保存一个缓存文件918。它也将两个指针保存在该缓存中:一个进栈指针919,指示来自源901的下一缓存的插入位置;以及一个当前指针920,指示当前使用的缓存。
缓存方案可以使用存储池实现,其中每个缓存均由存储管理器按需进行分配。这些缓存由链表918中的下一缓存指针链接在一起。当缓存被释放时,它们被释放回存储池,从而可以再分配给系统中的其它类或任务。进栈指针919指向链表中的最后那个缓存,而当前指针920指向当前使用的缓存。
由当前指针指向的缓存被交给Vela解码器类916。Vela解码类916与硬件中的解码器921进行对话。解码器921产生出经解码的电视信号,该信号再被编码为NTSC、PAL、或其它模拟格式的模拟电视信号。当Vela解码类916使用完缓存时,它便调用releaseEmptyBuf对象。
这种类结构使系统易于测试和调试。每一级都可以分开测试以确保其正常工作,而且在保持有效测试每个对象的同时,这些类也可以逐步聚合以实现期望的功能。
控制对象917接受用户的命令,并将事件发送到管道中以控制管道操作。例如,如果用户使用遥控器观看电视时,用户按下暂停时,控制对象917就向接收器903发送一个事件,告诉它暂停。接收器903则停止申求新缓存。当前指针920也停留于其当前的位置。当收到告诉其播放的另一事件时,接收器903则开始再次取缓存。系统精确同步;它从停止的那一帧开始。
遥控器也可有快进键。当按下快进键时,控制对象917便向转换902发送一个事件,告诉它向前移动两秒。转换902发现两秒的时间间隔是要求其向前移动三个缓存。它然后向下游管道发出一个重置事件,以便冲洗可能在硬件解码器中的任何排队数据或状态。这是一个关键步骤,由于MPEG流结构要求保持多个数据帧之间的状态,而该状态将通过重新定位指针而将置为无效。它然后将当前指针920向前移动3个缓存。当接收器903下次再调用nextFullBuf时,它就会取得新的当前缓存。快退操作与之相似,转换902则向后移动当前指针920。
系统时钟参考驻留在解码器中。对于快速播放,加快系统时钟参考;而对于慢速播放,则放慢。根据时钟速度,接收器仅需要更快或更慢地请求缓存。
对于图10,取自TmkXfrm类的其它两个对象被放置在磁盘存取的管道中。一个对象称作TmkClip读取器1003;另一个称为TmkClip写入器1001。缓存进入TmkClip写入器1001并被推入存储介质1004上的一个文件。TmkClip读取器1003请求脱离存储介质1005上某个文件的缓存。TmkClip读取器1003仅实现allocEmptyBuf和pushFullBuf方法,而TmkClip写入器1001仅实现nextFullBuf和releaseEmptyBuf方法。因此,TmkClip读取器1003可实现与输入(即TmkClipCache 1002的″推″一侧)相同的功能,而TmkClip写入器1001实现与输出(即TmkClipCache 1002的″拉″一侧)相同的功能。
参照图11,显示了一个可实现多种功能的优选实施例。信源1101有一个电视信号输入。信源将数据送到PushSwitch 1102(从TmkXfrm导出的一个变换)。PushSwitch 1102具有可由控制对象1114切换的多个输出。这就意味着根据用户意愿可以停止管道的一部分而开始另一部分。用户可以切换到不同的存储设备。PushSwitch1102可输出到TmkClip写入器1106,然后存入存储设备1107;或写到高速缓存转换1103。
这种设备的一个重要特点在于,使用它就能够在程序逻辑的控制下有选择地捕获输入信号成份。根据例如当前时间或特定时间间隔的信息,或观众按下的遥控按钮的信息,可以开启TmkClip写入器1106记录一部分信号,并在稍后的某个时间关闭。这种切换一般通过向PushSwitch 1102对象发送“切换”事件引发。
另一种触发选择捕获的方法是利用调制为VBI或放置在MPEG专用数据通道中的信息。从VBI或专用数据信道解码的数据被传送到程序逻辑。程序逻辑检查该数据以确定是否应该开始捕获电视信号。同样,该信息也可以指示记录应该何时结束,或另一数据项可以被调制为指示何时结束捕获的信号。开始与结束指示符可以清楚地调制到该信号中,或可用于解码此信息的其它信息(它以标准形式放置到信号中)中。
图12显示了演示程序逻辑使用触发捕获的特殊字或短语,如何包含在扫描CC字幕字段中的字,以确定开始和结束时间的例子。图中显示的数据流为NTSC或PAL字段流1201。CC字节从每个奇字段1202提取,并被输入到循环缓存或链表(使用如上所述的存储分配方案)1203,由字处理器1204处理。字分析器1204收集字符,直到遇到字边界,它通常是一段间隔、时期、或其它描绘字符。从上面描述可知,MPEG音频和视频片段集中在一串固定大小的PES缓存中。一个特殊片段被加到每个PES缓存,以保存取自CC字段1205的字。这样,保持CC信息与音频及视频信息的时间同步,并在播放流时,正确地呈现给观众。这种方式也允许程序逻辑在空闲时处理CC信息的存储流,这就分散了负载,减少了成本并提高了效率。在这种情况中,只需要将存储在特殊片段中的字传送到状态表逻辑1206。
本领域技术人员将容易意识到,虽然上述特别提到循环缓存,但也可由上面已描述的使用存储池分配方案的链表代替。
在流捕获期间,在表1206中查找指示识别该字操作的每个字。这种操作可以简单地改变识别状态机1207的状态,或使识别状态机1207发出如“开始捕获”、“停止捕获”、“短语查看”、或其它类似请求的动作请求。实际上,识别的字或短语可以导致管道被切换;例如,如果节目中使用了不合意的语言时,则可以重叠一个不同的音频轨道。
提示:可以随时修改或变动分析状态表1206和识别状态机1207。例如,可以为每个输入信道提供一个不同的表和状态机。作为选择,可根据情况(或因其它事件)切换这些单元。
参照图11,PullSwitch 1104输出到接收器1105。接收器1105调用nextFulIBuf和releaseEmptyBuf以从PullSwitch 1104取得或返回缓存。PullSwitch 1104可具有任意数量的输入。一个输入可以是ActionClip 1113。遥控可以切换输入源。控制对象1114向PullSwitch1104发送一个事件,告诉它切换。它将从当前输入源切换到控制对象选择的任何输入源。ActionClip类用于以预知和可控方式对不同的存储信号进行排队,这可由观众通过遥控加以控制。这样,如同TmkXfrm对象的派生,它接受用于切换到下一存储信号的“切换”事件。
这允许程序逻辑或用户创建定制视频输出序列。这就可以排列或组合任何数量的视频片段,就像是程序逻辑或用户正在使用广播演播室视频混合器一样。分配TmkClip读取器1108、1109、1110,且每一个均连到PullSwitch 1104。PullSwitch 1104在TmkClip读取器1108、1109、1110之间切换以组合成视频和视频削波(clip)。由于采用管道构造,流量控制是自动进行的。“推”和“拉”切换与广播演播室中的视频切换相同。
这里描述的导出类和结果对象可以任意方式合成,以创建多个不同的有用配置,用于储存、检索、切换和查看电视流。例如,如果可使用多个输入与输入部分,一个输入可以在另一输入存储的同时被查看,而第二个输出产生的画中画窗口被用于查看以前储存的数据流。这种配置表明,应用特定和新颖软件变换,就可在单个成本高效设备中,实现昂贵、精密硬件解决方案所实现的功能。
对于图13,显示了实现VCR备份的高级系统视图。输出模块1303将电视信号发送到VCR 1307。这就允许用户将电视节目直接记录在录像带上。本发明允许用户将要记录在录像带上的盘上节目进行排队,并规划节目发送到VCR 1307的时间。标题页(EPG data)能够在节目发送前送到VCR 1307。较长的节目可以通过按比例加快播放速度(即失落帧)以适合较短视频带录制。
VCR 1307输出也能够被导回到输入模块1301。在这种配置中,VCR就作为媒体切换器1302的备份系统。任何溢出的存储或较低优先权节目可被送到VCR 1307以便以后进行检索。
输入模块1301能够对在垂直消隐期(VBI)上编码的信息进行解码,并将这些信息送到系统的其它部件。输出模块1303能够将系统其它部分提供的数据编码成输出VBI数据。程序逻辑可以将各类的识别信息编码到输出信号,再使用VCR 1307将其记录在录像带上。通过将该录像带信息播放回输入,程序逻辑就能够读回该标识信息,这样就可以适当控制录像带记录的电视信号。例如,特殊节目可以同有关录制信息(如源网络)一起被录制。当该节目播放回输入模块中时,该信息就能够用于控制信号的存储以及播放的画面等。
本领域技术人员可以容易地意识到,这种机制可用于将多种数据项(并不一定是电视信号)引入程序逻辑。例如,可以将软件升级或其它数据传送到系统。从电视流接收这种数据的程序逻辑,可以施控制数据的处理,例如申请特定认证序列与/或根据一些先前取得的密钥解密嵌入信息。这种方法也可以用于正常的广播信号,从而实现一种将非电视控制信息和数据提供给程序逻辑的有效方法。
此外,本领域技术人员将容易意识到:虽然上面专门提到VCR,但是可以由任何多媒体记录设备(例如,数字化视频光盘-随机存取存储(DVD-RAM)录像机)方便地替换它。
图14为实现的本发明系统体系结构的高级视图的方框示意图。通常,采用本发明的系统板1400包括输入部分1401,它从多种信号源中接受一种输入信号。如下所述,该输入部分1401具有多种形式,每一种经调整就可从一种不同的来源接受输入信号。输出部分1402包括一个CPU 1403,CPU 1403主要负责初始化并控制本发明的多种硬件部件的操作。如上所述,CPU从处理高数据率的视频信号脱离出来,从而降低了处理器要求。经传送流接口1406,MPEG-2传送流解码/图形子系统1404接受从输入部分1401发送来的传送流。传送流解码器/图形子系统1404利用主机总线1408与CPU 1403通信。传送流解码器/图形子系统具有多种功能,将在以下描述,其主要功能是对从输入部分接收到的传送流进行解码,并将解码流作为视频信号输出到电视(未示出)。
输出部分进一步包括一个媒体管理器1405。媒体管理器具有多种功能,其主要功能是:根据其加入的I/O的数量和类型,起到系统部件间元件的桥接元件作用。例如,媒体管理器包括一个红外接收器/发射器接口,与用户操作本发明的手持遥控器连接。而且,媒体管理器具有重要的媒体处理功能。如上所指出的,传送信息由媒体管理器引导到MPEG-2解码器并被存储到存储设备。通过系统总线1407,媒体管理器1405与MPEG-2传送流解码/图形子系统1404通信。本发明的优选实施例使用PCI总线作为系统总线。优选地,输出部分分为三个分离芯片:CPU、MPEG-2解码器/图形子系统、以及媒体管理器。通过减小初始设计以及开发所需的时间与预算,这种简单的分离设置就能够大大减小各个单元的成本。另外,本领域技术人员将会意识到:输出部分也可设置为单一芯片或芯片集。
图15更详细地显示了输出部分1402。输出部分包括本发明的核心部件:CPU 1403;MPEG-2解码器/图形子系统1404;以及媒体管理器1405。CPU 1403的主要功能是运行系统软件、以及中间件和应用软件。系统软件包括OS(操作系统)内核和设备驱动程序。系统软件用于初始化和控制系统的各种硬件部件。CPU有关详细功能已在上文进行了描述。系统中几乎所有的数据运动都基于不涉及CPU的DMA转换或直接高速传送接口。虽然多种RISC处理器可适用于本发明,但本发明的当前实施例使用了由纽约的NEC公司生产的VR5432 CPU,它提供了时钟频率为202MHz、带有32K指令高速缓存和32K数据高速缓存的64-bit MIPS RISC体系结构。CPU通过系统总线1407与MPEG-2传送流解码/图形子系统1404通信。
MPEG-2解码器/图形子系统1404(例如加利福尼亚欧文的Broadcom公司提供的BCM7020)可视为输出部分1402的核心部件。实际上,MPEG-2解码器/图形子系统1404加入了许多重要部件,包括但并不局限于:
●一个主桥接电路;
●一个存储控制器;
●一个MPEG-2传送多路分配器;
●至少一个MPEG-2解码器;
●一个音频/视频解码器;
●一个PCI桥接电路;
●一个总线控制器;
●一个调制解调器接口;以及
●一个智能卡(SMARTCARD)接口。
如上所述,由输入部分1401生成的传送流被馈入一个传送接口1406,其上被多路分配为分离的音频和视频封装单位流(PES)。接着这些流被储存在硬盘驱动器1505,并通过输出1504播放。MPEG-2解码器/图形子系统1404中的传送流多路分配器负责多路分配操作。播放前,音频和视频分组流被从硬盘找出并重新集合到传送流中。接着,传送流再被解码为视频信号。部件1404中的MPEG-2传送流解码器负责对MPEG-2传送流进行解码。部件1404也包括用于生成高质量屏上显示的图形引擎,例如交互程序引导。部件1404的输出侧提供多个输出,包括S-video、音频、SPDIR(立体声成对数字接口)和CVBS(复合视频基带信号)。此外,还有智能卡(SMARTCARD)接口1503,以及设置与调制解调器1519接口的调制解调器端口1506。智能卡接口足以支持两个智能卡读取器。智能卡的功能将在下面详细描述。
输出部分1402进一步包括由OS内核控制的存储单元1501。系统软件提供单一设备驱动接口,它可为所有其它设备驱动程序一般使用DMA(Direct Memory Access,直接存储存取)的连续存储缓存。存储单元优选为动态随机存取存储器(Synchronous DynamicRandom Access Memory,SDRAM),容量优选至少为32MB。然而,其它存储器配置也在本发明的精神和范围内。此外,本发明可以包括不由OS内核控制的其它存储单元。
闪速可编程只读存储器(Programmable Read-only Memory,PROM)1502包括引导OS内核前初始化系统板的引导代码,这些引导代码或来自硬盘或通过TCP/IP网络连接。作为系统体系结构中的关键部件,除实现如存储检测和带电自检(Power-On Self Test,POST)等基本的系统启动任务外,PROM 1502可以保证PROM自身和OS内核不被篡改。这可以通过计算PROM码以及OS内核镜像上的数字签名实现。
如前面说明的,媒体管理器1405通过PCI总线1407连接到MPEG-2解码器/图形子系统1404,它起到系统硬件部件之间桥接或媒介作用,典型的硬件部件有:CPU 1403;硬盘或存储设备1505;以及存储器1501。媒体管理器1405功能依赖于集成在媒体管理器内的接口以及I/O设备。在本发明的优选实施例中,使用ASIC(Application Specific Integrated Circuit,特定用途集成电路)实现媒体管理器。然而,媒体管理器也可以用可编程逻辑设备实现,也可由多个分离设备组成。媒体管理器1405至少集成有以下部件:
●带数据加密的IDE主控制器;
●DMA控制器;
●IR接收器/发射器接口;
●多个UART(Universal Asynchronous Receiver/Transmitter,通用异步收发器);
●多条I2C(Inter-IC,集成电路之间)总线;
●多个GPIO(General Purpose I/O’s,通用输入输出);
●一个PCI总线仲裁器;
●MPEG-2媒体流处理器;
●PCM(Pulse Code Modulation,脉码调制)音频混频器;
●一个高速传送输出接口;
●一个扇速控制器;以及
●前面板按键矩阵扫描器。
如图15所示,媒体管理器包括用于控制系统温度的热电偶1507。热电偶通过I2C总线1508与媒体管理器接口。依次地,根据热电偶的输入,扇速由系统软件通过控制风扇1509的风扇控制器1510控制,以便将系统操作温度保持在最佳温度。
如上所述,媒体管理器也起到CPU 1403、内存1501、和硬盘1505之间协调媒体流传送的作用。这种作用通过上述媒体流处理器以及高速传送输出接口实现。
通过一个UART 1512,安全微控制器1511(例如加利福尼亚圣何塞(San Jose)的ATMEL公司提供的AT90S3232C)与媒体管理器ASIC 1405接口。优选地,为实现加密(例如,加密或认证),微控制器1511经过特殊设计。除提供如下所述的磁盘加密的主密钥外,微控制器也包含制造时随机生成的每个单元唯一的私人密钥(private key)。一经写入部件,密钥就不能读出且只能用于响应认证询问。
如图所示,为了储存记录的视频节目,设置了两个硬盘驱动器1505。如上所述,IDE主控制器集成在媒体管理器ASIC 1405上,并在每次传送的基础上,实现任一硬盘驱动器的加密特性。如上所述,为了对硬盘加密,微控制器要生成主密钥,对主密钥进行加密和解密。
RS232端口1514与另一个UART 1513接合。前面板导航束(navigation cluster)1516通过一个GPIO 1515与媒体管理器ASIC接合。通过IR接收器/发射器接口1517,IR接收发射器1518与媒体管理器ASIC接口。IR接收器组件装配在前面板导航束中,在透明窗口下,将在下面详述。它从手持遥控器接收已调信号并照原样输出到媒体管理器ASIC,或将其分配到CPU进行进一步处理,或提供一条到IR发射器1518的通路。
实时时钟(未示出)通过一个I2C端口与媒体管理器接合。由于本发明主要用作个人视频记录器,其中:在特定时间记录选择内容前,用户能够对系统进行编排,所以实时时钟成为一项基本要求。
如上所述,输入部分1401接收的输入信号以MPEG-2传送流形式传送到输出部分1402。根据信号源类型,在多种配置的一种中提供输入部分。通过提供针对数据源类型的输入部分1401,在保持各种类型输出相同的同时,仅需对系统板做较小的变化,就可以制造多种配置的产品。使用这种方式,就可以大大降低针对不同市场制造相应产品的风险。参照图16,显示了经过调整以接受模拟信号的输入部分1401。在优选实施例中,模拟输入部分可以接受多种格式的模拟信号:复合视频信号、NTSC、PAL、SECAM、或S-video信号。
对于NTSC信号,调谐器/RF解调器1601(例如由加利福尼亚圣何塞市的ALPS Electric公司提供的TMDH-2)将信号设置到期望的信道。优选的是,调谐器组件将调谐器、RF解调器、和RF分路器装配在同一部件中。经I2C总线端口,调谐器组件由媒体管理器ASIC 1405控制。
多标准声音处理器1603(例如由德国弗赖堡的MicronasSemiconductor公司提供的MSP4448G)可从合成音频连接器或调谐器/RF解调器1601接受模拟音频输入。此外,通过I2S总线,它从媒体管理器ASIC 1405接收数字音频输入。所产生的音频信号经I2S总线输出到MPEG编码器1604。
解码器1602,NTSC/PAL/SECAM视频解码器,例如由荷兰艾恩德霍芬的Philips Semiconductor公司生产的SAA7114H视频解码器,从调谐/RF解调器1601、合成视频输入或S-video输入接受输入,并将其转换为CCIR 656(Comité Consultatif International desRadiocommunications,第656号建议)数字格式并输入到MPEG-2编码器1604(如由BROADCOM公司生产的BCM7040)。
MPEG-2解码器1604从NTSC/PAL/SECAM视频解码器1602接受视频输入以及上述音频输入,从而生成MPEG-2传送流作为输出。在本发明的优选实施例中,编码器1604经设计可将音频与视频输入多路复用成一个固定比特率(CBR)的MPEG-2传送流。然而,为了节省磁盘空间,也可以将编码器1604设计为生成可变比特率(VBR)流。随后,经传送接口1406,传送流被送至解码器1404进行多路分路并做更进一步的处理。输入部分1401进一步包括不受OS内核控制的存储单元1605。图19为加入输入部分1401a和输出部分1402的系统板1900的方框示意图。如图所示,MPEG-2编码器与PCI总线1407上作为客户的MPEG-2解码器/图形分组件1404相连。
一种模拟前端的变化(未示出)包括经另一组合成音频/视频与/或S-视频连接器(S-video connector)的第二输入,用来接收发自便携式摄像机或VCR的内容。为了完全实现这一变化,需要另外的硬件和软件支持。
参照图17,示出了经过调整以接受数字卫星信号的输入部分1401b。数字卫星输入部分1401b从双卫星接收器(dual satellitereceiver)1701接收输入。解调器1702解调输入的QPSK(quadraturephase shift keying,四相移键控)信号以产生传送流。由于卫星传送流与MPEG-2不完全兼容,所以MPEG-2解码器/图形子部件1404必须具有解码任一类型流的能力。这样,不经任何进一步的修改和处理,经过传送接口1406,传送流就被传送到输出部分1402。图20为加入输入部分1401b的系统板2000的方框示意图。
参照图18,显示了设计接受数字或模拟信号的输入部分1401c。输入部分接受来自一个或多个数字和模拟格式的RF同轴连接器1801、1802的输入信号。模拟部分的功能与模拟输入1401a的功能相似。视频信号由双NTSC解码器1602进行解码。音频信号由两个多标准声音处理器1603处理,产生的输出馈送到双MPEG-2编码器。应该指出,在当前形式的输入部分中,每个部件均设置有两个。数字有线信号被引到双解调器1803。根据有线信号的调制方式,解调器可以是QAM(quadrature amplitude modulation,正交幅度调制)或QPSK解调器,或双制式解调器,支持电缆数据业务接口规范(Data Over Cable Service Interface Specification,DOCSIS)和数字视听协会(Digital Audio Visual Council,DAVIC)标准中的一种或两种。如图所示,数字信号解调器具有不受OS内核控制的相关存储单元1804。图21为加入数字电缆输入部分1401c的系统板2100的方框示意图。如在以前形式中,传送流经传送接口1406被送至输出部分1402。数字电缆输入部分1401c与PCI总线上作为客户端的MPEG-2解码器/图形部分1404相连。
如上所述,本发明计划用于PVR(Personal Video Recorder,个人视频记录器),其中用户可以实时观看所选择的视频流,或可以观看记录下来的视频流,检查视频流时可利用如倒退、暂停、播放、停止、慢放、快进等功能。此外,还设置有控制选择要记录的节目以及其它记录参数的功能。为此,本发明包括用户控制接口。用户与本发明交互主要通过电池供电的手持IR遥控器实现。用户发出的各种控制使遥控器发射出一种调制IR波束,而该波束会被PVR接收。IR接收/发射系统和接口已在上前进行了详细描述。然而,本发明的另一可选实施例提供了一种采用RF遥控器、接收器/发射器、以及接口,它可以替代或添加到IR驱动的遥控器上。
除了遥控器外,用户可以通过机器前面板上包括按钮或键的导航束与本发明进行交互。导航束实际上复制了遥控功能。这样,即使遥控器遗失、被盗或需要更换电波,导航束也可以提供本发明中的控制功能。如上所述,导航束的接口设置在媒体管理器ASIC上。
如上所述,系统板支持智能卡功能。可通过设置在本发明前面板上的插槽访问智能卡读取器。智能卡插槽的设置是为了应用于为了付费目的而需要进行用户认证的商业应用中,例如付费节目、音乐销售、商品销售等。
本发明使用微电子设计和制造领域技术人员所熟悉的传统制造技术制成。
如上所述,媒体管理器ASIC包括媒体流处理器。通常,媒体流处理器仅能用于处理单一信道,这就成为系统吞吐量的严重瓶颈。上面已经描述了可消除该瓶颈的常用多信道媒体处理器应用。此外,传统媒体流处理器必须位于其处理流数据通路中。这种要求使处理器必须集成在系统板上,这就很难做到不替换系统板而更新媒体流处理器。所以,需要提供一种可以灵活地加入现有硬件、具有从单道升级到多信道能力的PVR媒体流处理器的、独立于系统的装置。为此,本发明提供了一种独立于系统的、多通道媒体流处理器1000。如图22所示,多通路媒体流处理器包括:
●一个系统接口2201;
●一个媒体流识别器2202;
●一个媒体流处理器核心2203;
●一个多通路状态引擎2204;以及
●一个媒体流识别生成器2205。
系统接口2201起到系统总线上一个完全被动的从属客户的作用,它不以任何方式干涉数据传送,仅用于观察或“嗅探”总线。虽然本发明的媒体流处理器的其它部件均独立于系统,但可以为专用系统定制系统接口2201,或者利用硬布线元件或使用可编程开关,使其适用于连接多个不同的系统。对于特殊或专用系统,由于存储器总线上的硬件和协议几乎都是统一的,也可设置系统接口观察存储总线。系统接口实现了一种连接,通过它媒体处理器可以观察系统总线。
系统数据被发送到用于将媒体流与其它数据区别开的媒体流识别器2202,以识别需要处理的数据。媒体流识别器使用如源地址和目标地址的信息识别媒体流,这些信息在大多数系统中都是硬布线信号。
当识别媒体流时,媒体流识别生成器2205就在媒体流数据对象上加上标签,以便它们可以与各自的媒体流关联起来。在加上标签后,媒体流数据就被引导到媒体流处理器核心2203,在此进行并行处理而不是单通道处理。通过这种方式处理媒体流,就可以将吞吐量增加4到8倍。
对于多媒体流,当出现某一不同媒体标识时,多通道状态引擎2204会将保存出现不同媒体流标识时的媒体处理器状态。当最初的数据流再次出现时,状态就被重新载入并恢复处理最初的数据流。
产生的过程保存在媒体数据结构。这种数据结构一般是已知的。当处理每个流时,它就根据需要送至系统内存。
虽然本文对作为一种升级设备的多通道媒体流处理器进行了描述,它也可以作为媒体处理器加入一个新系统中。不需对系统板做大的改动,就可以将其容易地加入系统的体系结构中。
多通道媒体流处理器可以使用分离组件实现,也可以使用已有的装置编程方法,在可编程逻辑设备中实现。
虽然本发明是参照确定的优选实施例进行描述的,但本领域技术人员应当理解:可以由其它应用替代上述应用,而不背离本发明精神和范围。因此,本发明的保护范围仅由所附的权利要求限定。
Claims (61)
1.一种用于同时储存和播放多媒体数据的系统,包括:
输入部分,用于获取和调谐输入信号;
输出部分,其中所述输入信号作为传送流传送到所述输
出部分;所述输出部分包括:
处理器;
用于对所述传送流进行解码的装置,所述用于对所述传送流进行解码的装置通过一第一数据传送元件连接到所述处理器;以及
桥接元件,通过一第二数据传送元件连接到所述解码器/主控制器,所述桥接元件用于连接多个系统部件;
其中所述输入部分根据信号源类型而不同。
2.根据权利要求1所述的系统,其中所述输入部分适于接受模拟输入信号。
3.根据权利要求2所述的系统,其中所述输入部分接受来自RF同轴连接器、合成音频/视频连接器、以及S-视频连接器中的任一种的所述模拟输入信号。
4.根据权利要求2所述的系统,所述输入部分包括:
调谐器,用于调谐到预期信道;
解码器,用于数字化所述信号的视频分量;
多标准声音处理器,用于处理所述信号的音频分量;
MPEG-2编码器,其中所述MPEG-2编码器接收所述数字化视频分量和音频分量,其上所述信号被编码并多路传输到MPEG-2传送流中。
5.根据权利要求4所述的系统,还包括一个存储元件。
6.根据权利要求3所述的系统,还包括第二输入端,所述第二输入端包括第二组RF同轴连接器、合成音频/视频连接器、以及S-视频连接器。
7.根据权利要求1所述的系统,其中所述输入部分适于接受数字卫星输入信号。
8.根据权利要求7所述的系统,其中所述输入部分包括:
至少一个卫星调谐器;以及
至少一个解调元件,用于将数字卫星信号解调到MPEG-2传送流。
9.根据权利要求1所述的系统,其中所述输入部分适于接受来自至少一个RF同轴连接器的模拟格式和数字格式的输入信号。
10.根据权利要求9所述的系统,其中所述输入部分包括:
至少一个调谐器,用于调谐到预期信道;
至少一个解码器,用于数字化所述信号的视频分量;
至少一个多标准声音处理器,用于处理所述信号的音频分量;
MPEG-2编码器,具有多数据流编码能力,其中所述MPEG-2编码器接收所述数字化的视频分量和音频分量,所述信号在其上被编码并多路传输到MPEG-2传送流中。
11.根据权利要求10所述的系统,还包括至少一个存储元件。
12.根据权利要求1所述的系统,所述输出部分还包括一个传送接口,其中所述传送接口接收来自所述输入部分的所述传送流。
13.根据权利要求12所述的系统,用于对传送流进行解码的所述装置包括一个MPEG传送流解码/图形子系统,其中所述第一数据传送元件包括一条主机总线。
14.根据权利要求13所述的系统,其中所述传送流解码/图形子系统包括:
主桥接电路;
存储控制器;
MPEG-2传送多路分配器;
MPEG-2解码器;
音频/视频解码器;
图形处理器;
PCI桥接电路;
总线控制器;
智能卡接口;以及
调制解调器接口。
15.根据权利要求14所述的系统,所述传送流解码/图形子系统进一步包括至少一个传送流接口,其中所述传送流接口接收来自所述输入部分的所述传送流。
16.根据权利要求14所述的系统,其中所述传送流被多路分解为音频分组流和视频分组流,其中所述分组流被储存,并通过所述传送流解码/图形子系统的输出侧播放。
17.根据权利要求14所述的系统,其中所述传送流解码/图形子系统还包括多个输出,其中所述解码信号被输出到电视,所述输出包括以下任意一种:
S-视频信号;
音频信号;
SPDIR(Stereo Paired Digital Interface,立体声成对数字接口)信号;以及
CVBS信号(Composite Video Baseband Signal,复合视频基带信号)。
18.根据权利要求14所述的系统,还包括至少一个连接至所述传送流解码/图形子系统的智能卡读取器。
19.根据权利要求14所述的系统,还包括一个与所述传送流解码/图形子系统连接的闪速PROM,所述PROM包含用于在载入操作系统内核之前初始化所述系统的引导代码。
20.根据权利要求14所述的系统,还包括与所述传送流解码/图形子系统连接的SDRAM。
21.根据权利要求14所述的系统,还包括至少一个与所述调制解调器接口连接的调制解调器。
22.根据权利要求1所述的系统,其中所述处理器包括一个MIPS处理器,其中所述第一数据传送元件包括一条主机总线。
23.根据权利要求1所述的系统,其中所述处理器用于运行系统软件、中间件、以及应用软件。
24.根据权利要求23所述的系统,其中所述系统软件至少包括:操作系统内核以及设备驱动程序,所述系统软件用于初始化和控制硬件部件。
25.根据权利要求1所述系统,其中所述桥接元件包括媒体管理器,所述媒体管理器包括:
带数据加密的IDE主控制器;
DMA控制器;
IR接收器/发射器接口;
至少一个UART(Universal Asynchronous Receiver/Transmitter,通用异步接收器/发送器);
至少一条I2S总线;
至少一个GPIO(General Purpose Input/Output,通用输入/输出);
PCI总线仲裁器;
MPEG媒体流处理器;
PCM(Pulse Code Modulation,脉码调制)音频混频器;
高速传送输出接口;
风扇控制器;以及
用于前面板导航键区束的扫描接口。
26.根据权利要求25所述的系统,其中所述媒体管理器在ASIC(Application Specific Integrated Circuit,特定用途集成电路)或可编程逻辑设备中实现。
27.根据权利要求25所述的系统,还包括一个耦合至所述风扇控制器的温度传感器。
28.根据权利要求25所述的系统,还包括一个连接到所述风扇控制器的风扇。
29.根据权利要求25所述的系统,还包括一个连接到所述I2S总线的实时时钟。
30.根据权利要求25所述的系统,还包括连接到所述UART的安全微控制器,所述微控制器用于包括身份认证和加密/解密的密码应用。
31.根据权利要求25所述的系统,还包括耦合到所述UART的RS232端口。
32.根据权利要求25所述的系统,还包括集成在所述媒体管理器上的IEEE1394接口。
33.根据权利要求25所述的系统,还包括耦合至所述GPIO的前面板LED阵列。
34.根据权利要求25所述的系统,还包括耦合至所述GPIO的前面板导航束。
35.根据权利要求25所述的系统,还包括与所述IR接收器/发射器耦合的遥控器。
36.根据权利要求1所述的系统,其中所述第二数据传送元件包括系统总线。
37.根据权利要求36所述的系统,其中所述系统总线包括PCI总线。
38.根据权利要求37所述的系统,还包括耦合至所述PCI总线的USB(Universal Serial Bus,通用串行总线)控制器。
39.根据权利要求1所述的系统,其中所述系统实现的方式为一种系统板。
40.根据权利要求1所述的系统,其中所述输出部分实现的方式为许多微芯片,这些芯片通过所述数据传送元件彼此相连。
41.根据权利要求1所述的系统,其中所述输出部分实现的方式是单个的微芯片或者是芯片组。
42.一种用于同时处理通过几条通道的媒体流的系统,包括:
用于观察数据总线上的数据流的装置;
用于识别所述数据流中的媒体流的装置;
用于将媒体流数据对象与其各自的媒体流关联起来的装置;
多通道媒体流处理器,其中所述媒体处理器用于并行处理通过多条通道的媒体流数据;以及
用于在所述处理器从初始媒体流切换到下一媒体流时监视和保存所述处理器状态的装置,其中如果所述处理器切换回所述初始媒体流,则重新加载与所述初始媒体流关联的状态。
43.根据权利要求41所述的系统,其中用于观察所述数据流的所述装置包括一个系统接口,所述系统接口包括一个在所述总线上的被动的从属客户端,其中所述系统接口观察所述数据流而不会干扰数据流。
44.根据权利要求43所述的系统,其中所述系统接口专用于某一特定系统类型,所述专用系统接口由下述之一实现:可编程开关和硬布线。
45.根据权利要求43所述的系统,其中所述数据总线是下述之一:系统总线和存储总线。
46.根据权利要求42所述的系统,其中用于识别媒体流的所述装置包括一个媒体流识别器,其中所述媒体流根据源地址和目标地址将媒体流与所述数据流中的其它部分区别开。
47.根据权利要求42所述的系统,其中用于将媒体数据目标与其各自的媒体流关联的所述装置包括一个媒体标识生成器,所述媒体标识生成器向媒体流数据对象分配标签,以便任何数据对象均与其源流关联。
48.根据权利要求42所述的系统,其中用于监视和保存所述处理器状态的所述装置包括一个多通路状态引擎,所述状态引擎监视媒体流标识符,并在与所述下一媒体流关联的媒体流标识符被关联时保存所述处理器状态,所述保存的状态包括第一状态。
49.根据权利要求48所述的系统,其中如果出现与第一状态关联的媒体流标识符,则所述状态引擎重新载入所述第一状态。
50.根据权利要求42所述的系统,还包括媒体流数据结构,所述已处理的媒体流被保存到所述数据结构,并根据需要被传送至系统存储器。
51.根据权利要求42所述的系统,其中所述系统在可编程逻辑设备中实现。
52.一种用于同时处理通过几条通道的媒体流的系统,包括以下步骤:
观察数据总线上的数据流;
识别所述数据流中的媒体流;
将媒体流数据对象与其各自的媒体流关联起来;
并行处理通过多条通道的媒体流数据;以及
当处理器从初始媒体流切换到下一媒体流时,监视和保存所述处理器状态;以及
如果所述处理器切换回所述初始媒体流,则重新加载与所述初始流关联的状态。
53.根据权利要求52所述的系统,其中所述观察所述数据流的步骤包括以下步骤:
提供系统接口,所述系统接口包括一个在所述总线上的被动的从属客户端;以及
所述系统接口观察所述数据流,而不干扰数据流。
54.根据权利要求53所述的系统,其中所述系统接口专用于某一特定的系统类型,所述特定系统接口由可编程开关和硬布线的其中之一实现。
55.根据权利要求53所述的系统,其中所述数据总线是系统总线和存储总线的其中之一。
56.根据权利要求52所述的系统,其中所述识别数据流的步骤包括以下步骤:
根据源地址和目标地址将媒体流与所述数据流中的其它部分区别开。
57.根据权利要求52所述的方法,其中所述将媒体数据对象与其各自的媒体流关联起来的步骤包括:
向媒体流数据对象分配标签,以便任何数据对象均与其源流关联。
58.根据权利要求52所述的方法,其中所述监视和保存所述处理器状态的步骤包括以下步骤:
监视媒体流识别符;以及
当与所述下一媒体流关联的媒体流标识符被关联时,保存所述处理器状态,所述保存的状态包括第一状态。
59.根据权利要求58所述的方法,其中所述监视和保存所述处理器状态的步骤还包括:
如果出现与所述第一媒体流关联的媒体流标识符,则重新载入所述第一状态。
60.根据权利要求52所述的方法,还包括以下步骤:
将所述已处理的数据流保存到媒体数据结构;以及
根据需要传送到系统存储器。
61.根据权利要求52所述的方法,所述方法利用可编程逻辑设备实现。
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CN103154897A (zh) * | 2010-10-14 | 2013-06-12 | 阿尔卡特朗讯公司 | 用于电信网络应用的核抽象层 |
CN103154897B (zh) * | 2010-10-14 | 2016-08-03 | 阿尔卡特朗讯公司 | 用于电信网络应用的核抽象层 |
CN110362524A (zh) * | 2018-04-11 | 2019-10-22 | 杭州海康威视数字技术股份有限公司 | 时序信号生成方法、装置、逻辑电路板及存储介质 |
CN110362524B (zh) * | 2018-04-11 | 2021-04-09 | 杭州海康威视数字技术股份有限公司 | 时序信号生成方法、装置、逻辑电路板及存储介质 |
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US20090269031A1 (en) | 2009-10-29 |
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