CN1551310A - 半导体装置的制造方法、电光装置、集成电路及电子设备 - Google Patents
半导体装置的制造方法、电光装置、集成电路及电子设备 Download PDFInfo
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Abstract
一种半导体装置的制造方法,包括:将基板(10)上的半导体膜图案化、形成应分别形成源极/漏极区域及沟道形成区域的元件区域(14)的第1工序,形成包覆各元件区域的半导体膜的栅极绝缘膜(16)的第2工序,在栅极绝缘膜上的给定位置形成栅极(18)的第3工序,和在元件区域形成源极/漏极区域(20)及沟道形成区域(22)的第4工序;至少第3工序中的栅极(18)的形成利用包括使用全息图掩模的曝光工序的工艺来进行,第1工序中的元件区域(14)的形成和第4工序中的源极/漏极区域(20)及沟道区域(22)的形成利用包括使用投影型曝光掩模的曝光工序的工艺来进行。由此,可尽量避免生产效率的降低,并能在平整度低的基板上形成微细图案。
Description
技术领域
本发明涉及薄膜晶体管等半导体元件的制造方法,尤其涉及图案形成时的曝光技术。
背景技术
在薄膜晶体管等半导体元件的制造工艺中,可使用曝光技术来形成希望的图案。最近,作为高分辨率的曝光技术,全息图曝光技术引人注目。这种全息图曝光技术在譬如[Large-field,high-resolution photolithography;Francis Clube et al.,proc.SPIE1997,vol.3009,pp.36-45](非专利文献1)等文献中有记载。
[非专利文献1]
[Large-field,high-resolution photolithography]Francis Clube et al.,proc.SPIE1997,vol3009,pp.36-45.
在液晶显示装置等电光装置的制造中,为了降低成本使用平整度比较低的基板(例如,廉价的玻璃基板等)。然而,若用这种平整度低的基板,很难提高曝光的分辨率。在用逐次移动式曝光机和扫描仪等曝光装置的处理(投影型的曝光处理)中,从抑制成本上升及批量生产上的误差范围等考虑、为确保稳定的曝光精度而牺牲分辨率。尤其是,随着近年来的显示装置大型化,分辨率的提高变得很困难。由此,在上述全息图曝光技术中,虽然由于在原理上无光学象差,故容易提高分辨率,但是与使用逐次移动式曝光机等以前的曝光方法相比,有生产效率降低的倾向。因此,过多使用全息图曝光,虽然曝光分辨率提高,但是会造成生产效率的降低。所以,以前在平整度低的基板上形成图案时,很难做到提高曝光分辨率和确保生产效率两者同时皆顾。
发明内容
在此,本发明的目的是,提供一种尽量避免生产效率的降低且能在平整度低的基板上形成微细图案的技术。
为了达到上述目的,本发明采用一种在基板上形成含有栅极、源极/漏极区域及沟道形成区域的晶体管的半导体装置的制造方法,其特征在于,至少栅极利用包括使用全息图掩模的曝光工序的工艺形成,源极/漏极区域及沟道形成区域利用包括使用投影型曝光掩模的曝光工序的工艺形成。
更详细地讲,本发明为一种在基板上形成一个或多个含有栅极、源极/漏极区域及沟道形成区域的晶体管的半导体装置的制造方法,包括:将基板上的半导体膜图案化、形成应分别形成源极/漏极区域及沟道形成区域的元件区域的第1工序,形成包覆各所述元件区域的半导体膜的栅极绝缘膜的第2工序,在栅极绝缘膜上的给定位置形成栅极的第3工序,和在元件区域形成源极/漏极区域及沟道形成区域的第4工序,至少第3工序中的栅极的形成利用包括使用全息图掩模的曝光工序的工艺来进行,第1工序中的元件区域的形成和第4工序中的源极/漏极区域及沟道区域的形成利用包括使用投影型的曝光掩模的曝光工序的工艺来进行。
这样,通过至少在对晶体管的尺寸缩小影响最大的栅极的形成中应用全息图曝光技术,即使在平整度低的基板上也能形成微细的图案。而且,在栅极以外的形成工艺中,利用以前大量使用的采用投影型曝光掩模的曝光技术,能最大限度防止并能避免生产效率的降低。这样,既能满足确保微细化和生产效率这两个相矛盾的要求,又能在平整度低的基板上形成微细的晶体管。
优选所述第3工序包括:在栅极绝缘膜上形成导电体膜的工序,在导电体膜上用感光性材料形成第1感光膜的工序,利用具有对应于栅极的曝光图案的全息图掩模对第1感光膜进行曝光的工序,对曝光后的第1感光膜进行显像、保留与该感光膜的栅极相对应的区域并除去其余区域的工序,用在导电体膜上被保留的第1感光膜作为蚀刻掩模、蚀刻导电体膜来形成栅极的工序。这样,能实现栅极的微细化。
优选所述第1工序包括:在半导体膜上用感光性材料形成第2感光膜的工序,使用具有对应于元件区域的曝光图案和对应于在第3工序曝光时用于对准全息图掩模位置的第1对准标记的曝光图案的第1投影型曝光掩模、来对第2感光膜进行曝光的工序,对曝光后的第2感光膜进行显像、保留与该第2感光膜的栅极相应的区域及与第1对准标记相应的区域并除去其余区域的工序,用在导电体膜上被保留的第2感光膜作为蚀刻掩模、蚀刻导电体膜来形成元件区域和第1对准标记的工序。这样,对第3工序的全息图掩模的位置对准(Alignment)变得容易。
而且,优选第1投影型曝光掩模还具有对应于第2工序及其以后的工序中使用的第2对准标记的曝光图案、在第1工序中也同时形成该第2对准标记。这样,在第1工序以后、能利用第2对准标记容易地进行全息图掩模以外的曝光掩模及其他对象物的位置对准。
优选所述第4工序包括:用感光性材料形成包覆与多个所述晶体管相对应的多个元件区域的第3感光膜的工序,使用具有区分作为源极/漏极区域及沟道形成区域的形成对象的元件区域和不作为该形成对象的元件区域的曝光图案的第2投影型曝光掩模来对第3感光膜进行曝光的工序,对曝光后的第3感光膜进行显像、保留与不作为该第3感光膜的形成对象的元件区域对应的区域并除去其他区域的工序,和在除去第3感光膜而露出的形成对象的元件区域、向应成为源极/漏极区域的部位进行掺杂、形成源极/漏极区域及沟道形成区域的工序;用上述第2对准标记进行第2投影型曝光掩模的位置对准。这样,第2投影型曝光掩模的位置对准变得容易。
另外,优选包含在全息图掩模中的曝光对象区域数为包含在第1投影型曝光掩模和/或第2投影型曝光掩模中的曝光对象区域数的整数倍。这样,能实现各掩模的对准的容易化。
而且,优选第1投影型曝光掩模和/或所述第2投影型曝光掩模为逐次移动式曝光机或扫描仪中使用的光罩。在栅极以外的部件形成时的曝光中,使用逐次移动式曝光机和扫描仪等以前大量使用的曝光装置,能将元件形成工艺的变动控制在最低限度,故较好。
而且,本发明也包括利用上述制造方法制造的半导体装置。另外,本发明还包括具有上述半导体装置的集成电路、电路基板、电光装置以及电子设备。
在这里所谓「集成电路」是指,能起一定功能的半导体装置和相关配线等集成后形成的配线电路。另外,所谓「电路基板」是指,在一方和/或另一方有多个半导体元件,根据相应还具有连接半导体元件互相之间的配线等的基板。例如,可以举出在有机EL显示装置等显示装置中使用的有源矩阵基板。
在这里,所谓「电光装置」一般是指,具有本发明的半导体装置、具有由电作用发光或使来自外部的光的状态发生变化的电光元件的装置,含有自发光的装置和控制来自外部的光的通过的装置。例如,是指作为电光元件而具有液晶元件、具有电泳动粒子分散的分散媒体的电泳动元件、EL(场致发光)元件、和具有使由加载电场产生的电子对着发光板发光的电子发射元件的有源矩阵型的显示装置等。
在这里所谓「电子设备」一般是指,具有本发明的半导体装置并起一定功能的设备,具有例如电光装置和存储器等。对其构成无特别限定,例如,IC卡、手机、摄像机、个人计算机、头盔式显示器、背投式或前投式投影机、以及带显示功能的传真装置、数码相机的取景器、便携式TV,DSP(Digital Signal Processor数字信号处理器)装置、PDA、电子笔记本、电子布告盘、和宣传公告用显示板等。
附图说明
图1为说明一实施方式的制造方法中使用的曝光掩模的图。
图2为说明一实施方式的制造方法中曝光步骤的工序图。
图3为说明一实施方式的制造方法中曝光步骤的工序图。
图4为说明一实施方式的制造方法的曝光步骤的工序图。
图5为说明一实施方式的元件制造工艺的工序图。
图6为说明电光装置的构成例的图。
图7为表示可应用电光装置的电子设备的例子的图。
符号说明
M1、M3-投影型曝光掩模,M2-全息图掩模,DP1、DP2、DP3-曝光图案,10-基板,12、22-绝缘膜,14-半导体膜(元件区域),16-栅极绝缘膜,18-栅极,20-源极/漏极区域,22-沟道形成区域。
具体实施方式
以下,参照附图说明本发明的实施方式。在以下的说明中,首先对有关本发明的曝光方法作概略说明。
图1为说明一实施方式的制造方法中使用的曝光掩模的图。例如,在本实施方式中,假定在含有薄膜晶体管等薄膜元件而构成的半导体装置的制造工艺中,含有至少3次曝光,来进行说明。在本实施方式的该3次曝光处理中,使用作为进行投影型曝光的1个曝光装置的逐次移动式曝光机或用扫瞄器进行第1次和第3次的曝光,而第2次的曝光是用全息图曝光装置进行曝光的。图1(a)和图1(c)分别表示第1次和第3次的曝光用的投影型曝光掩模M1和M3,图1(b)表示第2次的曝光(全息图曝光)用的曝光掩模(全息图掩模)M2。
如图1(a)所示的曝光掩模(光罩)M1具有半导体装置第1层的曝光所需的曝光图案。具体地,曝光掩模M1具有对应于含有薄膜元件而构成的薄膜电路的图案、即曝光图案DP1,在后面的曝光处理中对用于上述曝光掩模M2的对准(位置对准)的对准标记进行曝光用的标记图案HP1,和在后面的曝光处理中对上述曝光掩模M2的位置对准用的对准标记进行曝光的标记图案SP1。
如图1(b)所示的曝光掩模M2具有半导体装置第2层的曝光所需的曝光图案。具体地,曝光掩模M2具有对应于含有薄膜元件而构成的薄膜电路的图案、即曝光图案DP2,和本曝光掩模M2的位置对准用的对准标记H2。
如图1(c)所示的曝光掩模(光罩)M3具有半导体装置第3层的曝光所需的曝光图案。具体地,曝光掩模M3具有对应于至少含有薄膜元件而构成的薄膜电路的图案、即曝光图案DP3。
上述的各曝光图案(曝光对象区域)中,曝光掩模M2包含的曝光图案数为曝光掩模M1和M3包含的曝光图案数的整数倍(在本例为4倍)。
接下来说明,用上述的各曝光掩模、同时使用逐次移动式曝光机与全息图曝光装置、重叠多个图案形成层来进行曝光的步骤。另外,在以下的说明中,主要对曝光处理进行重点说明。
图2至图4为说明本实施方式的制造方法中的曝光步骤的工序图。
首先,用上述的曝光掩模M1、用逐次移动式曝光机对第1层进行曝光。具体地,如图2所示那样,用曝光掩模M1、多次(本例为16次)重复曝光和移动(分步重复),在基板10上形成16处对应于曝光图案DP1的图案D1。而且,分别对应于标记图案HP1标记图案SP1,在基板10上分别形成各对准标记H1、S1。之后,进行必要的显像和蚀刻来完成第1图案形成工序。
接着,用上述的曝光掩模M2,利用全息图曝光装置进行第2层的曝光。具体地,如图3那样,在形成有与第1层对应的图案D1的基板10上,用曝光掩模形成M2形成对应于第2层的曝光图案DP2的图案。以下,将该图案在图案D1上重叠起来形成的图案称为图案D21。此时,全息图曝光装置,用在基板10一侧预先形成的对准标记H1和在曝光掩模M2上设置的对准标记H2、对基板10和曝光掩模M2互相间的位置进行对准后、对曝光图案D2进行曝光。在本例中,4次重复这样的位置对准和曝光的步骤、对全部曝光对象区域进行曝光。之后,进行必要的显像和蚀刻来完成第2图案形成工序。
接下来,用上述的曝光掩模M3、用逐次移动式曝光机对第3层进行曝光。具体地,如图4所示那样,在形成有对应于第1层和第2层的图案D21的基板10上,用曝光掩模M3形成对应于第3层的曝光图案DP3的图案。以下,将该图案在图案D21上重叠起来形成的图案称为图案D321。
此时,逐次移动式曝光机在参照第1层曝光时在基板10上形成的逐次移动式曝光机用的对准标记S1、进行位置对准后,分步重复第3层的曝光图案、在希望的位置进行曝光。之后,进行必要的显像和蚀刻来完成第3图案形成工序。
接下来,具体说明应用上述本发明的曝光方法的元件制造工艺。用一个例子来说明本实施方式中1个半导体元件、即薄膜晶体管的制造工艺。
图5为说明一实施方式的元件制造工艺的工序图。在该图中,薄膜晶体管的制造工艺以剖面图表示。
首先,如图5(a)所示那样,在已形成由氧化硅和氮化硅等组成的基底绝缘膜12的基板10上形成半导体膜14、将该半导体膜14图案化来形成元件区域。在此,半导体膜14使用,用例如PECVD法、LPCVD法、溅射法等各种成膜法,形成的多晶硅膜、和无定形(Amorphous)硅膜等。本实施方式中,在用于将该半导体膜14图案化的抗蚀膜50的曝光时、应用所述的第1曝光处理(参见图2),用曝光掩模M1由逐次移动式曝光机进行曝光。之后,对该曝光后的抗蚀膜50进行显像,用显像后的抗蚀膜50作为蚀刻掩模进行蚀刻、得到希望形状的半导体膜(元件区域)14。之后,在各半导体膜14上形成由氧化硅和氮化硅等组成的绝缘膜16。该绝缘膜16作为栅极绝缘膜而发挥其功能,能用例如电子回旋加速共振PECVD法(ECR-PECVD法)或PECVD法等成膜法来形成。
接着,用溅射法等各种成膜法在半导体膜14上形成导电体膜、将该导电体膜图案化并形成栅极18。在此,可用例如钽和铝等作为栅极18。在本实施方式中,在用于将该栅极18图案化的抗蚀膜52曝光时、应用所述的第2的曝光处理(参见图3),用曝光掩模M2,利用全息图曝光装置进行曝光。之后,对该曝光后的抗蚀膜52进行显像,显像后的抗蚀膜52作为蚀刻掩模进行蚀刻、得到希望形状的栅极18。根据本工序,即使在平整度比较低的、大面积的玻璃基板上也能进行细微图案的曝光,能形成譬如门信号宽度约为0.5μm的栅极18。
接着,将栅极18作为掩模进行构成给体或受体的掺杂元素的注入(所谓自整合离子注入),在半导体膜14上形成源极/漏极区域20和沟道形成区域(活性层)22。
在本实施方式中,在该源极/漏极区域20和沟道形成区域22形成用的抗蚀膜54的曝光时应用所述第3曝光处理(参见图4),并用曝光掩模M3、用全息图曝光装置来进行曝光。这样,如图所示,在对图中右侧的半导体膜14进行离子注入时、对应于覆盖图中左侧的半导体膜14的区域的抗蚀膜54被曝光。之后,对该曝光后的抗蚀膜54进行显像,通过显像后的抗蚀膜54进行离子注入。这样,例如作为掺杂元素将磷(P+)注入图中右侧的半导体膜14。之后,将能量密度调整至氯化氙激发激光(XeClExcimer Laser)为400mJ/cm2左右进行照射来活化掺杂元素,便得到N型薄膜晶体管。另外,也可以代替激光照射而以250℃~400℃温度的热处理来进行掺杂元素的活性化。而且,重复同样的工序,得到P型薄膜晶体管。
接着,如图5(d)所示,在栅极绝缘膜16和栅极18的上表面形成由氧化硅膜等构成的保护绝缘膜22。氧化硅膜使用,例如利用PECVD法等成膜法形成厚度为500nm左右的膜比较合适。接下来,形成各自贯穿栅极绝缘膜16和保护绝缘膜22并到达各源极/漏极区域20的接触孔,通过在这些接触孔内用溅射法等成膜法掺入铝、钨等导电体并形成图案,形成源极/漏极电极24。该工序的曝光宜选用逐次移动式曝光机和全息图曝光装置等进行。经过上述工序之后,便得到如图5(d)所示的薄膜晶体管。
这样,通过至少在对晶体管的尺寸缩小影响最大的栅极的形成中应用全息图曝光技术,即使在平整度低的基板上也能形成微细的图案。而且,在栅极以外的形成工艺中,利用以前大量使用的采用投影型曝光掩模的曝光技术,能最大限度防止并能避免生产效率的降低。这样,既能满足确保微细化和生产效率这两个相矛盾的要求,又能在平整度低的基板上形成微细的晶体管。
接着,说明根据本发明的制造方法制作的薄膜晶体管的应用例。由本发明的制造方法得到的薄膜晶体管能应用于,例如构成EL显示装置、液晶显示装置等中的各像素的像素电路,控制该像素电路的驱动器(集成电路)的形成等。
图6为说明电光装置的构成例的图。本实施方式的电光装置(显示装置)100由含有2个薄膜晶体管、电容器和发光元件而构成的像素电路112在基板上的像素区域111呈矩阵状配置的电路基板(有源矩阵基板),和含有向像素电路112供给驱动信号的驱动器115和116构成。驱动器115,通过发光控制线Vgp向各像素区域供给驱动信号。驱动器116,通过数据线Idata和电源线Vdd向各像素区域供给驱动信号。通过控制扫描线Vsel和数据线Idata,能对各像素进行电流程控,控制发光元件的发光。应用上述实施方式的制造方法形成构成像素电路的各薄膜晶体管和构成驱动器115、116的各薄膜晶体管。另外,虽然作为电光装置的一例而对有机EL显示装置进行了说明,但除此以外也可以同样制造液晶显示装置等各种的电光装置。
接着,说明应用本发明的电光装置100而构成的各种电子设备。
图7为表示能应用电光装置100的电子设备的实例的图。图7(a)为在手机中的应用例,该手机230具有天线部231、声音输出部232、声音输入部233、操作部234、和本发明的电光装置100。这样,本发明的电光装置能作为显示部使用。
图7(b)为摄像机的应用例,该摄像机240具有图像接收部241、操作部242、声音输入部243、和本发明的电光装置100。这样,本发明的电光装置能作为取景器和显示部使用。
图7(c)为便携式个人电脑(所谓PDA)的应用例,该机250具有摄像机部251、操作部252、和本发明的电光装置100。这样,本发明的电光装置能作为显示部使用。
图7(d)为头盔式显示器的应用例,该头盔式显示器260具有皮带261、光学机构容纳部262和本发明的电光装置100。这样,本发明的电光装置能作为图像显示源使用。
图7(e)为背投式投影机的应用例,该投影机270在框体271上具有光源272、合成光学机构273、反射镜274及275、屏幕276、和本发明的电光装置100。这样,本发明的电光装置能作为图像显示源使用。
图7(f)为前投式投影机的应用例,该投影机280在框体282上具有光学机构281和本发明的电光装置100,图像能在屏幕283上显示。
这样,本发明的电光装置能作为图像显示源使用。而且,本发明的电光装置100不仅限于上述例子,可以应用于所有能够应用有机EL显示装置、液晶显示装置等显示装置的电子设备。例如,此外可以充分应用于带显示功能的传真装置、数码相机的取景器、便携式TV、电子笔记本、光电布告盘、和宣传公告用显示板等。
而且,上述实施方式的制造方法也能应用于电光装置的制造以外的各种装置的制造。例如,能应用于FeRAM(Ferro Electric RAM)、SRAM、DRAM、NOR型RAM、NAND型RAM、浮游栅极型非易失性存储器,磁性RAM(MRAM)等各种存储器的制造。而且,在使用微波的非接触型通讯系统中,可以应用于制造搭载有微型电路芯片(IC芯片)的廉价终端。
另外,本发明不局限于上述各实施方式的内容,在本发明思想的范围内可进行各种变形、变更。例如在上述的实施方式中,作为半导体膜的一例,采用硅膜进行了说明,但半导体膜不仅限于此。而且,在上述的实施方式中,作为本发明的半导体元件的一例,采用薄膜晶体管进行了说明,但半导体元件不仅限于此,也可以形成其它元件(例如,薄膜二极管等)。
Claims (12)
1.一种半导体装置的制造方法,该方法为在基板上形成含有栅极、源极/漏极区域及沟道形成区域的晶体管的半导体装置的制造方法,其特征在于,
至少所述栅极利用包括使用全息图掩模的曝光工序的工艺形成,所述源极/漏极区域及所述沟道形成区域利用包括使用投影型曝光掩模的曝光工序的工艺形成。
2.一种半导体装置的制造方法,该方法为在基板上形成一个或多个含有栅极、源极/漏极区域及沟道形成区域的晶体管的半导体装置的制造方法,其特征在于,包括:
将所述基板上的半导体膜图案化、形成应分别形成所述源极/漏极区域及所述沟道形成区域的元件区域的第1工序,
形成包覆各所述元件区域的所述半导体膜的栅极绝缘膜的第2工序,
在所述栅极绝缘膜上的给定位置形成栅极的第3工序,和
在所述元件区域形成所述源极/漏极区域及所述沟道形成区域的第4工序;
至少所述第3工序中的所述栅极利用包括使用全息图掩模的曝光工序的工艺形成,所述第1工序中的所述元件区域和所述第4工序中的所述源极/漏极区域及所述沟道区域的形成利用包括使用投影型曝光掩模的曝光工序的工艺形成。
3.根据权利要求2所述的半导体装置的制造方法,其特征在于,
所述第3工序包括:
在所述栅极绝缘膜上形成导电体膜的工序,
在所述导电体膜上用感光性材料形成第1感光膜的工序,
利用具有对应于所述栅极的曝光图案的所述全息图掩模对所述第1感光膜进行曝光的工序,
对曝光后的所述第1感光膜进行显像、保留该感光膜的与所述栅极相对应的区域并除去其余区域的工序,和
用在所述导电体膜上被保留的所述第1感光膜作为蚀刻掩模、蚀刻所述导电体膜来形成所述栅极的工序。
4.根据权利要求2或3所述的半导体装置的制造方法,其特征在于,
所述第1工序包括:
在所述半导体膜上用感光性材料形成第2感光膜的工序,
使用具有对应于所述元件区域的曝光图案、和对应于在所述第3工序曝光时用于对准所述全息图掩模位置的第1对准标记的曝光图案的第1投影型曝光掩模,对所述第2感光膜进行曝光的工序,
对曝光后的所述第2感光膜进行显像、保留该第2感光膜的与所述栅极相对应的区域及与所述第1对准标记相对应的区域并除去其余区域的工序,和
用在所述导电体膜上被保留的所述第2感光膜作为蚀刻掩模、蚀刻所述导电体膜来形成所述元件区域和所述第1对准标记的工序。
5.根据权利要求4所述的半导体装置的制造方法,其特征在于,
所述第1投影型曝光掩模还具有对应于所述第2工序及以后的工序中应使用的第2对准标记的曝光图案,在所述第1工序中也形成该第2对准标记。
6.根据权利要求5所述的半导体装置的制造方法,其特征在于,
所述第4工序包括:
用感光性材料形成包覆与多个所述晶体管相对应的多个所述元件区域的第3感光膜的工序,
使用具有区分作为所述源极/漏极区域及所述沟道形成区域的形成对象的所述元件区域和不作为该形成对象的所述元件区域的曝光图案的第2投影型曝光掩模来对所述第3感光膜进行曝光的工序,
对曝光后的所述第3感光膜进行显像、保留与不作为该第3感光膜的所述形成对象的所述元件区域对应的区域并除去其他区域的工序,和
在除去所述第3感光膜而露出的所述形成对象的元件区域、向应成为所述源极/漏极区域的部位进行掺杂、形成所述源极/漏极区域及所述沟道形成区域的工序;
用所述第2对准标记进行所述第2投影型曝光掩模的位置对准。
7.根据权利要求6所述的半导体装置的制造方法,其特征在于,
所述全息图掩模中包含的曝光对象区域数为所述第1投影型曝光掩模和/或所述第2投影型曝光掩模中包含的曝光对象区域数的整数倍。
8.根据权利要求6或7所述的半导体装置的制造方法,其特征在于,
所述第1投影型曝光掩模和/或所述第2投影型曝光掩模为逐次移动式曝光机或扫描仪中使用的光罩。
9.一种电光装置,其特征在于,具有利用权利要求1至8中任意一项所述的半导体装置的制造方法制造的半导体装置。
10.一种集成电路,其特征在于,具有利用权利要求1至8中任意一项所述的半导体装置的制造方法制造的半导体装置。
11.一种电路基板,其特征在于,具有利用权利要求1至8中任意一项所述的半导体装置的制造方法制造的半导体装置。
12.一种电子设备,其特征在于,具有利用权利要求1至8中任意一项所述的半导体装置的制造方法制造的半导体装置。
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JP3706951B2 (ja) * | 1995-06-26 | 2005-10-19 | 株式会社ニコン | 露光装置 |
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JP4628531B2 (ja) | 1999-08-31 | 2011-02-09 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
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US6872658B2 (en) * | 2001-11-30 | 2005-03-29 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating semiconductor device by exposing resist mask |
-
2003
- 2003-05-15 JP JP2003137405A patent/JP2004342833A/ja active Pending
-
2004
- 2004-04-19 KR KR1020040026596A patent/KR100614073B1/ko not_active IP Right Cessation
- 2004-04-20 TW TW093111017A patent/TW200501238A/zh unknown
- 2004-04-22 CN CNB2004100353781A patent/CN1315165C/zh not_active Expired - Fee Related
- 2004-05-07 US US10/840,297 patent/US7547589B2/en not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102211446A (zh) * | 2010-04-06 | 2011-10-12 | 株式会社村田制作所 | 丝网印刷版及其制造方法 |
CN102211446B (zh) * | 2010-04-06 | 2013-11-20 | 株式会社村田制作所 | 丝网印刷版的制造方法 |
CN102096328A (zh) * | 2010-12-03 | 2011-06-15 | 深圳市华星光电技术有限公司 | 液晶面板的曝光工序及其掩膜 |
US8592111B2 (en) | 2010-12-03 | 2013-11-26 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | LCD panel photolithography process and mask |
US8758964B2 (en) | 2010-12-03 | 2014-06-24 | Shenzhen China Star Optoelectronics Technology Co. Ltd. | LCD panel photolithography process and mask |
Also Published As
Publication number | Publication date |
---|---|
US7547589B2 (en) | 2009-06-16 |
US20050026340A1 (en) | 2005-02-03 |
KR100614073B1 (ko) | 2006-08-22 |
JP2004342833A (ja) | 2004-12-02 |
TW200501238A (en) | 2005-01-01 |
KR20040098522A (ko) | 2004-11-20 |
CN1315165C (zh) | 2007-05-09 |
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