CN1555559B - 多态非易失性存储系统二进制模式下的选择性运行方法 - Google Patents

多态非易失性存储系统二进制模式下的选择性运行方法 Download PDF

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CN1555559B
CN1555559B CN028181689A CN02818168A CN1555559B CN 1555559 B CN1555559 B CN 1555559B CN 028181689 A CN028181689 A CN 028181689A CN 02818168 A CN02818168 A CN 02818168A CN 1555559 B CN1555559 B CN 1555559B
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CN1555559A (zh
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陈健
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Delphi International Operations Luxembourg SARL
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels

Abstract

一种快速非易失性存储系统，其通常以多存储状态运行其存储器，并且可以在两态模式下运行其部分或所有存储器块。选择的这两种状态是所有状态中距离最远的。因此，在两态模式下运行提供了更大的余量。这使得在两种状态下运行的存储器编程速度更块，使用寿命也更长，而这些优点比多状态运行能提供的增大数据存储密度的优点更吸引人。

Description

多态非易失性存储系统二进制模式下的选择性运行方法
技术领域
本发明涉及一种非易失性存储器及其运行，更具体说，涉及一种多态存储器在少于运行状态能力下的选择性运行技术。
背景技术
本发明的原理适用于各种类型的非易失性存储器，包括现有的和计划采用正在研发的新技术的存储器。然而作为示范，本发明具体实施的描述是关于一种快速电可擦除及可编程只读存储器(EEPROM)，其中存储元件是浮栅。
现有的商业产品中快速电可擦除及可编程只读存储器(EEPROM)阵列的每个浮栅存储元件通常在二进制模式下存储单一比特数据，在这种情况下将两个范围的浮栅晶体管阈值电平定义为存储电平。浮栅晶体管的阈值电平同存储在浮栅上的电荷电平范围相适应。除了缩小存储器阵列的尺寸外，目前的趋势是通过在每个浮栅晶体管内储存不止一比特数据来进一步增加此类存储器阵列的数据储存密度。通过为每个浮栅晶体管将两个以上阈值电平定义为储存状态而实现了这一点；商业产品中目前已经包括了四种这样的状态：每个浮栅存储元件存储二比特数据。更多的存储状态(比如每个存储元件16态)也在计划之中。每个浮栅存储器晶体管有一总的阈值电压范围(窗口)，其在此范围内可以正常运行。因为该范围在各状态间加上余量而允许其相互明确区分，其又被划分给定义过的若干个状态。
随着储存在每个存储器单元中的状态数量的增加，浮栅存储元件已编程的电荷电平中任何偏移的公差减少。由于存储在各存储器存储元件上状态数量的增加使得每种存储状态指定电荷的范围必须减小并且相互更加接近，因此必须增加编程的精确度，而且必须减少存储电荷电平可容许的编程后偏移度，无论是实际偏移还是视在偏移。一个存储在单元中的电荷的实际偏移量可能会受到该单元的状态，以及同其有某种程度电耦合的其它单元(比如位于同一列或同一行的单元和共享同一线路和节点的单元)的读取、编程和擦除操作的干扰。
储存的电荷中产生视在偏移是因为存储元件之间存在场耦合。集成电路制造技术的进步所带来的存储元件阵列体积的减小必定使得这种耦合程度加深。这一问题在两组在不同时间编程的相邻单元之间尤为明显。一组单元的浮栅按程序加上与同一组数据相对应的电荷电平。在第二组单元以第二组数据编程后，从第一组单元浮栅读取的电荷电平通常看起来和编程后的不一样，原因就在于第二组浮栅的电荷效应同第一组相耦合。这被称为Yupin效应，且在美国专利第5,867,429和5,930,167号中有说明，以引用的方式将其全文并入本文中。这些专利描述了或者从物理上将两组浮栅相互隔离，或者在读取第一组浮栅电荷的时候考虑第二组的电荷效应。另外，第5,930,167号专利还说明了在仅仅两种状态下或具有减少的余量的情况下，将一种多态存储器的部分选择性地编程为高速缓冲存储器以缩短最初进行数据编程所需时间的方法。然后数据在两种以上状态下被读入存储器并重新编程，或者说增加余量。
此种效应在各种快速EEPROM单元阵列中都存在。一种设计的“或非”(NOR)阵列将其存储器连在相邻位(列)线间，并且将其控制门同字(行)线相连接。各独立单元或者包含一个浮栅晶体管(带或不带一同其串联的选择晶体管)，或者包含两个被一单独选择晶体管分开的浮栅晶体管。此种阵列及其在存储系统中使用的实例在下列美国专利以及SanDisk公司申请中的申请案中有说明，以引用的方式将其全文并入本文中：第5,095,344，5,172,338，5,602,987，5,663,901，5,430,859，5,657,332，5,712,180，5,890,192和6,151,248号专利，以及2000年2月17日提出的第09/505,555号申请和2000年9月22日提出的第09/667,344号申请。
一种设计的“与非”(NAND)阵列包含众多存储元件，8个，16个甚至32个，在两头中任一头通过选择晶体管以串联的方式在一位线和基准电位间相连。字线与不同串联单元的控制门相连。此种阵列及其运行的相关实例在下列美国专利中有说明，以引用的方式将其全文并入本文中：第5,570,315，5,774,397和第6,046,935号。简要地说，分两步将来自输入数据的不同逻辑页面的两比特数据编入各存储器四种状态中的一种，首先根据一比特数据将一个单元设定成一种状态，如果数据需要，根据输入的第二比特数据将其重新设定成另一种状态。
增加各存储器编程状态数量的另一潜在负面影响是就其可承受的编程/擦除循环的次数而言存储器寿命的减少。这是因为需要更精确的编程能力以在一个单元里提供多态存储。由于重复使用后俘获在介质上的电荷以及其它因素的影响，存储器在经过大量循环后需要更多的时间完成编程而且在必要的高精确度下实现多态运行也更加困难。
发明内容
简要概括地说，本发明提供一种非易失性存储系统及其运行方法，其中各存储器存储元件通常编程了至少四种运行状态，因此每个单元至少存储两比特数据，但是如果有必要或者希望提高编程性能，或者为了就其可承受的编程和擦除循环次数而言延长存储器一部分的寿命，或者为了获得其它利益，每个存储元件可以选择更少的存储状态。通常情况下一个存储器中至少提供四种运行状态，其将单元中的存储元件编程为至少四种阈值电平范围中的一种，这四种范围在阈值电平运行窗口内相互独立。作为采用比正常情况存储较少状态的实例，当转换为存储仅两种状态时，使用至少四个阈值电平范围中相距最远的两个。在上述四态NAND型存储器中，在一时间内只有来自一个页面的比特编入相距最远的两个阈值电平。只要通过为已选定的存储器组编程以省略第二页面的数据比特就可在其中将编程从四态转换成两态。
本发明的其它方面、特性、优点和应用在以下示范性具体实施方式中有说明，这些说明应当同相关图示一起参阅。
附图说明
图1是一非易失性存储系统的方块图，其中描述了本发明所实施的各个方面；
图2所示为当图1中存储器阵列为一个NAND型时的现有线路和组织结构。
图3所示为在一半导体基底上形成的NAND型存储器阵列沿一列的横截面图；
图4所示为图3存储器阵列于其中的4-4部分所取的横截面图；
图5所示为图3存储器阵列于其中的5-5部分所取的横截面图，；
图6所示为图2-图5中NAND型存储器阵列的示范工作电压表1；
图7所示为图2-图5中NAND型存储器阵列的另一特性；
图8所示为图2-图5中NAND型存储器阵列四态运行下阈值电压现有分配的范例；
图9所示为图2-图5中NAND型存储元件阵列中可能会采用的编程电压信号范例；
图10A和图10B是电压阈值电平分布，其展示的是图2-图5中NAND型存储器阵列的多态编程技术；
图11再现了增加读取和确认基准电压后图10A和图10B的多态电压阈值电平分布情况；以及
图12所示为两态情况下图2-图5中存储器阵列的电压阈值电平分布情况。
具体实施方式
非易失性存储系统实例
为提供特定实例，参照图1-图7描述了一特定的非易失性存储系统，其中实施了本发明的各个方面。图1是一快速存储系统的方块图。包含复数个以矩阵方式排列的存储器M的阵列1被一列控制电路2、一行控制电路3、一共源极控制电路4和一c-p-well控制电路5所控制。将列控制电路2连接至存储器阵列1的位线(BL)，以负责读取存储器(M)所储存的数据，确定存储器(M)在一次编程操作中的状态，并且负责控制位线(BL)的电位电平以促进编程或禁止编程。将行控制电路3连接至字线(WL)以选定一字线(WL)，从而施加读取电压，施加与由列控制电路2控制的位线电位电平相结合的编程电压，并且施加一与形成存储器(M)的p型区域(在图3中标为″c-p-well″11)电压相耦合的擦除电压。共源极控制电路4控制一连接至存储器(M)的共源极线(在图2中标为″c-source″)。c-p-well控制电路5控制着c-p-well电压。
存储器(M)内储存的数据由列控制电路2读取并通过一输入/输出线路和一数据输入/输出缓冲器6传输到外部输入/输出线路。存储器储存的程序数据通过外部输入/输出线路输入到数据输入/输出缓冲器6，并传送到列控制电路2。将外部输入/输出线路连接至一控制器20。
用于控制快速存储装置的指令数据被输入一连接至外部控制线路的指令界面，这些外部控制线路同控制器20相连。指令数据通知快速存储器需要采取什么操作。输入的指令被传送到一状态(控制)器8，其控制着列控制电路2、行控制电路3、共源极控制电路4、c-p-well控制电路5和数据输入/输出缓冲器6。状态(控制)器8可以输出快速存储器的状态数据，比如就绪/忙(READY/BUSY)或者通过/失败(PASS/FAIL)。
控制器20同一主机系统或者说可以同一主机系统(比如一个人电脑、一数字照相机或一个人数字助理)相连。主机发起指令，比如向或从存储阵列1存储或读取数据，以及分别提供或接收这样的数据。控制器将指令转换成指令电路7可以识别和执行的指令信号。为了在存储阵列写入或读取用户数据，控制器通常包含缓冲存储器。典型的存储系统包括一带有控制器20的集成电路芯片21，以及一个或一个以上各包含存储阵列及相关控制，输入/输出和状态(控制)器电路的集成电路芯片22。发展趋势当然是将系统的存储阵列和控制器电路纳入一个或多个集成电路芯片。存储系统可以作为主机系统的一部分嵌入主机系统，或者包括在抽取式地插入主机系统插槽的存储卡中。这样的卡可以包括整个存储系统，或者包括控制器和存储阵列，相关外围电路可以由单独的卡提供。
参照图2，其中描述了存储器阵列1的结构范例。作为范例描述了一NAND型的快速EEPROM。在一特定范例中，存储器(M)被分成了1,024块。每一块中存储的数据被同时擦除。因此，块是众多可同时擦除单元的最小单位。在本范例中的每一块中都有8,512列，它们又被分为奇数列和偶数列。位线也被分成偶数位线(BLe)和奇数位线(BLo)。将在各门电极连接至字线(WL0到WL3)的四个存储器以串联的方式形成一NAND单元组。NAND单元组的一端通过第一选择晶体管(S)连接至相应的位线(BL)，该晶体管的门电极同一第一选择门线(SGD)相耦合，而另一端通过第二选择晶体管(S)连接至共源极，该晶体管的门电极同一第二选择门线(SGS)相耦合。尽管为了简单起见，每个单元组只显示了四个浮栅晶体管，但是实际使用了更多的晶体管，例如8、16甚至32个。
在本范例的用户数据的一次读取和编程操作中，同时有4,256个单元(M)被选中。被选中的单元(M)都具有同一字线(WL)，例如WL2和同一位线(BL)，例如从偶数位线BLe0到BLe4255。因此，可以同时读取或编程532字节的数据。同时读取或编程的这532B数据在逻辑上构成一“页”。因此，一块就可以存储至少8个页面。当每个存储器(M)储存两比特的数据，也就是使用一多电平单元时，一块就可以存储16个页面。在此实施例中每个存储器的存储元件(在本案中为各存储器的浮栅)储存两比特的用户数据。
图3是图2所示NAND单元组沿位线(BL)方向所取的横截面图。在一P型半导体基底9的表面形成一个P型区域c-p-well 11，其又被一n型区域10所包围，以实现c-p-well和P型基底电子上的隔离。n型区域10通过一第一接触孔(CB)和一n型扩散层12连接至第一金属MO制造的c-p-well线。P型区域c-p-well 11也通过一第一接触孔(CB)和一p型扩散层13连接至c-p-well线。将c-p-well线连接至c-p-well控制电路5(图1)。
各存储器都有一浮栅(FG)，其根据这个单元所存储的数据储存一定量的电荷，另外还有形成门电极的字线(WL)以及由p型扩散层12构成的汲极源极。借助一隧道氧化膜(14)在c-p-well的表面形成浮栅(FG)。字线(WL)则通过一种绝缘膜(15)堆叠在浮栅(FG)上。源极通过第二选择晶体管(S)和第一接触孔(CB)连接至由第一金属(MO)制成的共源极线路(c-source)。共源极线路又连接至其控制电路(4)。汲极通过第一选择晶体管(S)、第一接触孔(CB)、第一金属(MO)的中间连线以及第二接触孔(V1)连接至由第二金属构成的位线路(BL)。位线连接至列控制电路(2)。
图4和图5显示的分别是以字线(WL2)方向所取的一存储器(图3的4-4部分)和选择晶体管(图3的5-5部分)横截面图。每一列被在基底上形成并填有绝缘材料的沟槽与邻近列相隔离，此被称为浅沟隔离(STI)。浮栅(FG)被STI、绝缘膜15和字线(WL)相隔离。近来，浮栅(FG)的间距将小于0.1um，而浮栅间的电容耦合一直在增加。由于选择晶体管(S)的门电极(SG)和浮栅(FG)及字线(WL)的形成步骤一样，所以它也是一种堆叠的门结构。在线路末端将这两个选择的门线路并联在一起。
图6的表I概括了运行存储器阵列1时所施加的电压，在一个特定的范例中，各存储器的浮栅存储两个比特，处于下列状态之一：“11”、“10”、“01”和“00”。此表显示的是选定字线“WL2”和位线“Ble”用于读取和编程时的情况。通过将c-p-well电压增加到20V擦除电压，将选定块的字线(WL)接地，而擦除其存储的数据。由于未选定块的所有字线(WL)，位线(BL)，选择线(SG)和共源极都在浮动状态下，且它们同c-p-well的电容耦合，所以其电压也升至约20V。因此，只给选定存储器(M)的隧道氧化膜14(图4和图5)施加强大的电场，当隧道电流经过隧道氧化膜14时，选定存储器的数据也被擦除。此范例中已擦除的单元处于四种可能的编程状态之一，即″11″.
为了在编程操作时在浮栅(FG)上存储电子，将所选择的字线WL2连接至一程序脉冲Vpgm，并将选定的位线Ble接地。另一方面，为了阻止一些不发生编程的存储器(M)编程，将相应的位线Ble连接至电源的Vdd(比如3V)，未选择的位线Blo也一样。将未选择的字线WL0，WL1和WL3连接至10V，第一选择门(SGD)连接至Vdd，第二选择门(SGS)接地。因此，将正被编程的存储器(M)的一个信道电压设为0V。信道电压被与字线(WL)耦合的电容所阻止而导致禁止的编程中信道电压上升至6V左右。如上所述，在编程过程中，强大的电场仅施加在存储器的隧道氧化膜14上，隧道电流以与擦除时相反的方向流经隧道氧化膜14，然后逻辑状态从″11″改为其它一种状态″10″，“01”或者″00″。
在读取和确认操作下，选择门(SGD和SGS)和未选择的字线(WL0，WL1和WL3)的电压升至4.5V读取电压，从而成为通道门。将选择的字线(WL2)连接至一定的电压，每次读取和确定操作的电平都是一定的，以便确定有关存储器的阈值电压是否达到了这样的标准。比如，在READ 10操作中，将选择的字线WL2接地，以便检测阈值电压是否高于0V.在此读取情况下，可以说读取电平为0V。在VERIFY01运行下，将选择的字线WL2连接至2.4V，以验证阈值电压是否达到2.4V。在此验证情况下，可以说验证电平是2.4V。
将选择的位线(BLe)预先充电至一高电平，比如0.7V。如果阈值电压高于读取或验证电平，因为有非导电的存储器(M)，相关位线(BLe)则维持其高电位电平。另一方面，如果阈值电压低于读取或验证电平，因为有导电的存储器(M)，相关位线(BLe)则降低至低电位电平，比如小于0.5V。以下将详细解释读取和验证操作。
图7展示的是图1中列控制电路2的一部分。每一对位线(BLe和BLo)耦合至一数据存储部分16，该数据存储部分包括两个数据存储(DS1和DS2)寄存器，每个都可以存储一比特的数据。在一次读取或验证操作中，数据存储部分16检测选定的位线(BL)的电位电平，然后以二进制模式存储数据，并且在编程操作中控制着位线的电压。通过选择″EVENBL″和″ODDBL″信号中的一个，数据存储部分16选择性地连接至所选位线。还将数据存储部分16耦合至输入/输出线路，以输出读取数据并存储程序数据。如上述图1的说明中所述，输入/输出线路又连接至数据输入/输出缓冲6。
各存储元件两种以上状态下存储系统的运行
图8所示为存储器阵列1的每个存储器(M)浮栅存储元件储存两比特数据时，即四种数据状态下的阈值电压分布情况。曲线25代表阵列1中的单元在擦除状态下(″11″数据状态)，亦即负阈值电压电平状态下阈值电平VT的分布情况。分别存储″10″和″00″用户数据的存储器的阈值电压分布26和27如图所示位于0V和1V以及1V和2V之间。曲线28显示的是编程为″01″数据状态的单元的阈值电压分布，设定在2V和4.5V之间的读读通道电压是最高的阈值电压。
在此范例中各存储器(M)存储的两比特数据来自不同的逻辑页面，也就是说两比特中的每一比特具有不同的逻辑页面地址。图8中右边的比特在低页面地址(＝0，2，4，…，16，382)输入时存取。左边的比特在高页面地址(＝1，3，5，…，16，383)输入时存取。
为了提高可靠性，最好缩小单个分布的范围(分布更窄)，因为分布缩小就意味着读取的范围(相互之间的差距)便宽了。根据本发明，分布范围变窄了，但是编程速度没有明显下降。
根据1995超大规模集成电路(VLSI)技术研讨会文摘(129-130页)《多级NAND EEPROM快速精确编程方法》中所述，在此以引用的方式并入本文中，原则上，将分布限定在0.2V范围内需要提供通常的重复编程脉冲，每级之间的增量为0.2V。要把分布限定在0.05V范围内，就需要0.05V的逐级脉冲增量。要使存储器的编程电压达到如此小的逐级增量，编程时间就要增加4倍。然而，按照本发明的主要观点，下面将要讲述减少阈值电压分布并不需要增加如此多的编程时间。
图9所示为一现有的编程脉冲技术。图示了一编程电压Vpgm的波形。编程电压Vpgm被分成多个脉冲，脉冲间的增量是0.2V。在此特定范例中，Vpgm的起始电平为12V。
在脉冲的间隔期实施验证(读取)操作。也就是说，在每个编程脉冲间读取并行的各存储器的电平，以确定其是否等于或大于设定的验证电平。如果给定存储器的阈值电压超出了验证电平，则可以通过将连接至该存储器串联单元组的位线电压从OV提高到Vdd来除去Vpgm。其它同时进行编程的单元继续进行编程，直到其依次达到各自的验证电平。在单元最后一次编程脉冲期间如果阈值电压从验证电平以下移到超出验证电平，阈值电压偏差等于Vpgm的级差也就是0.2V。所以，阈值电压被控制在0.2V范围内。
图10A和图10B展示的是上述阵列类型中对一四态NAND存储器编程的现有技术。在第一编程通道中，单元的阈值电平是根据来自下逻辑页面的比特来设定。如果是个″1″，不采取任何行动，因为这是已擦除的状态。但如果该比特是″0″，则单元的电平被提高到第一编程时的状态34。第一编程通道结束。
在第二编程通道中，单元的阈值电平是根据来自上逻辑页面的比特来设定的。如果是″1″，不进行编程，因为该单元处于33或34状态中的一个，具体取决于下页面比特的编程，但无论哪种状态上页面比特都是″1″。然而如果上页面比特是″0″，该单元将进行第二次编程。如果该单元第一通道的结果仍然处于擦除状态33，则该单元从此状态编程到最高状态36，如图10B上面箭头所示。然而，如果第一编程通道的结果是该单元的状态编程为34，则该单元在第二次编程通道中从此状态进一步编程到状态35，如图10B下面箭头所示。第二次编程通道的结果是将单元编程为指定状态以存储来自上页面的″0″，并且不改变第一编程通道结果。
当然，如果存储器在四种状态以上运行，在存储器指定电压阈值窗口内就会有许多同运行状态一样多的分布状态。此外，尽管各分布都分派有特定的比特样式，但也可能分派不同的样式，在此情况下的编程所发生的状态可能和图10A和图10B所示不同。在此前NAND系统背景的说明中提到的专利对几种此类改变有所阐述。另外，由Jian Chen，Tomoharu Tanaka，Yupin Fong以及Khandker N.Quader在2001年6月27日提出的题为“减小多数据状态下非易失性存储器存储元件间耦合效应的运作技术”的美国专利申请，申请编号09/893,277，中对于减少多状态下NAND和其它类型存储阵列Yupin效应影响的技术作了说明。该申请的全文也以引用的方式并入本文中。
图11所示为用于读取各单元以确定该单元处于四个阈值状态中哪一个的电压。电压VV10，VV00和VV01是在编程期间分别用来读取确认存储器10，00和01存储状态的程序验证基准阈值电压。通常情况下这种确认发生在重复编程脉冲之间。如图所示，导致每个具有这些程序验证基准阈值电压之一的已编程的分布同编程分布情况的较低范围相一致。
大约位于电压分布33-36间相邻范围中段的电压0，VR00和VR01用于从存储器阵列读出数据的读取阈值电压电平。这些都是阈值电压，每个单元所读取的阈值电压状态都要同其对比。分别将存储器测出的电流或电压同基准电流或电压相比较，以完成此项工作。如上所述，在这些读取阈值电压电平和编程阈值电压分布之间存在余量，因此只要分布范围不和读取阈值电平0，VR00和VR01中任一个重合，则允许这些分布从干扰中或类似情况中适当扩大范围。然而，随着存储状态分布数量的增加，这种余量减少，而且为防止这样的扩大，编程应该更精确。
各存储元件两种状态下存储系统的运行
图12显示了上述多态存储器在两种状态下的运行情况。只对图10和图11中的头两种状态33和36进行了编程，在图12中分别标为33′和36′。如果一个单元将存储的一数据比特为″1″，则在编程操作中该单元无任何动作。其阈值电平保持在擦除后的阈值电平分布状态33′下。然而，如果这个单元将存储的数据比特为″0″，这个单元将以图9所述的方式编程，从而把阈值电平移入分布范围36′。如图10B所示，这个完成方法和当把上页面的比特″0″从擦除状态33编至已编程状态36时所用方法一样。基准电压VV01以多状态下同样的方式用来验证编程。此技术的一个优点就是很容易将一些单元编程为两态，而根据上述技术将存储器的大部分编程为多态。或者生产一种存储器集成电路芯片，其可由一熔丝或状态(控制)器8里的固件设置设定，从而以多态或两种状态操作整个存储器阵列。两种状态下的编程和两种以上状态下的编程是一样的，只是在两种状态下的编程时下页面的操作被省略。
各单元的读取采用基准电压VR00来确定其阈值状态是否在已擦除的分布范围33′或已编程的范围36′内。这不同于多态状态下的读取，其中采用较低基准电压0V和较高基准电压VR01(图11)以确定存储器是否编程为状态33或36中的一种。由于两态运行下(图12)没有数据编入多态分布范围34或35(图11)，大概位于分布范围33′和36′中段的非零基准电压VR00被用于读取已编程为两态的存储器。这大大增加了这些分布范围之间的余量，并且读取时使用的基准超过了多状态下读取操作时的量。因此，两态模式下可以允许无论是实际上的还是视在的分布范围进一步扩大和移动。
本技术的一个主要优点就是在编程、读取和/或擦除操作后，编程或擦除单元的电荷电平干扰减少。特别是，使用非零、正读取阈值电平VR00读取数据增加了存储器的对读取干扰的公差。我们知道，由于那些单元和同一行的单元也被读取，擦除分布范围33′的趋势是朝着正向发展。而且随着存储器经受大量的擦除/编程循环，这一效应变得日益突出。在大多数应用中，已擦除状态同时也是已编程状态之一。如图11所示，当把零电压用作负阈值分布范围33′内读取存储器的阈值断点电平时，分布范围随着时间的推移向正向转变可能产生不希望得到的效应：其接近零电压甚至变成正电压。这种情况在现有的两态(二进制)存储系统中也可能发生，在此系统中，在读取过程采用零电压作为存储器编程的两个阈值电平间的断点。作为和VV01验证电平共同编程的结果，图12中第二编程状态分布范围36′同已擦除分布范围33′相差甚远，因此较高的读取阈值断点VR00极大促进了分布范围33′的正向转变，使其存储状态难以被误读。这对于两态及多态运行维持相同的阈值窗口范围十分有利。
使用图12中增加的余量带来的第二个优点是延长了数据保留的时间。分布33′和36′可以在数据电平被阈值VR00误读前转换更多。随着存储器的擦除/编程次数的增加，转换出现的概率也有增加。因此，读取干扰的减少和/或数据保留的增加也使得存储器使用寿命增加了。
因为每个编程单元的最终阈值电平都不需要设定在如此狭窄的范围里，加大的余量也使得两态状况下的每比特编程速度比多比特编程速度快多。可能会使用较高的ΔVpgm(图9)或较高绝对电压以减少单元编程所需的时间，这将导致由于更大余量而被接受的分布范围36′变宽。
多态存储结构有多种用途，该结构还能以上述方式提供二进制运行。可以指定该存储系统的一些存储块1(图2)来用于两态存储，而剩下的块负责多态存储。这些可在状态(控制)器8中设定，其中编程和读取期间存储状态的数量取决于数据编程和读取存储块的物理地址或相关地址。
在一特殊应用中，最频繁写入数据的存储块以两态方式运行而其余重复写入不太频繁的存储块则以多态方式运行。需要频繁重复写入的数据包括存储用户信息的存储块表，比如系统文件分配表(FAT)，块循环统计和其它作为运行快速EEPROM系统一部分所存储的添加信号数据(overhead data)。FAT表的频繁更新可以在主机系统中轻松确认，这些主机系统指定更新文件分配表时要写入的数据要比存储用户添加信号数据时要写入的少。然后，此类确认后的FAT表数据被控制器20传送给两态模式下运行的存储块(图1)。至于存储器块任务统计和其它此类数据，控制器20知道其具体写入存储块的地方，所以这些块的运行设定为两种状态。需要提前将达到使用寿命极限的存储块更换的必要性如果说没有完全消除地话，至少得到很大程度的改善。
本发明的另一应用是，如果在存储器使用寿命内有必要，将存储器阵列中至少部分存储块从多态运行转变为两态运行。比如对于比其它存储块接收数据多得多的存储块而言，这可以动态地实施。另一范例是将在多态下运行的部分达到擦除/编程循环极限的存储块转变为两态运行。尽管存储器的条件可能不允许其继续以多态方式运行，但是可能还可以按照图12中所述技术继续进行两态方式下的运行。当然，如果以两种状态下存储数据，就需要四态运行下两倍数量的存储器。各存储块或存储块组的擦除/编程周期数数量应该被保留，以便向状态(控制)器8提供必要的数据，状态(控制)器可以根据这些数据来决定何时将存储块的运行方式从一种状态调整到另一种状态。美国专利第5,043,940号对于记录此类数据有专门的说明。另外，就像2000年2月17日提交的美国专利申请第09/505,555号所提及的那样，还可以记录不同存储块的循环数。在2000年9月14日提交的美国专利申请第09/662,032号中描述了一种专门进行循环记录的技术。上述专利及专利申请的全文都以引用的方式并入本文中。
在上述本发明的特殊范例描述中，多态运行包括了四态运行。当然，多态运行可以包括四种以上状态，比如8种或16种，其中阈值电压分布范围设定很小，相互间的余量也比图11和图10所示四态运行时的小。另外，尽管描述了作为一种可提供更大范围，延长使用期限和提高编程效率的替代选择的两态模式，但是这种选择还可以采用两种以上且小于正常运行采用的存储状态。比如，如果正常的多状态运行的编程和读取采用16种状态，这种选择方案就可以从这些存储状态中选择4个：间隔最大数量的最低、最高以及其它两个间隔相当的。
选择介质存储元件
上述范例中说明的快速EEPROM存储器都是采用导电的浮栅作为电荷存储元件。然而，本发明还可以应用在将电荷俘获介质作为各存储器的存储元件的系统中。该介质存储元件位于一导电控制门和位于存储器信道内的基底之间。尽管介质可以像浮栅一样以同样的大小和位置分入各元件，但因为电荷能被这样的介质现场俘获，通常并不需要这样做。电荷俘获介质范围可以在整个阵列上延伸，除了被选择晶体管或类似元件占据的区域。
在下列技术文章和专利中大体描述了介质存储元件存储器，在这些文章和专利的全文都以引用的方式并入本文中：1987年3月出版的IEEE电子设备刊物，Vol.EDL-8，No.3，pp.93-95中Chan等人“真正的单晶体管——氧化物-氮化物-氧化物EEPROM装置”；1991年4月出版的IEEE固体电路期刊，Vol.26，No.4，pp.497-501中Nozaki等人″A 1-Mb EEPROM withMONOS Memory Cell for Semiconductor Disk Application，″；2000年11月出版的IEEE电子设备刊物，Vol.21，No.11，pp.543-545中Eitan等人，″NROM：A Novel Localized Trapping，2-BitNonvolatile Memory Cell，″，以及美国专利第5,851,881号。
目前有两种具体的电荷俘获介质材料和配置可实际使用。一个是一种三层的介质，其包括基底上生成的硅二氧化物，然后是一层布置在其之上的硅氮化物，再是一层生成和/或布置在硅氮层(″ONO″)之上的硅二氧化物。另一种是在门和半导体基底表面之间单独一层硅富硅二氧化物(silicon rich silicon dioxide)。后一种材料在下列两篇文章中有说明，两篇文章的全文以引用的方式并入本文中：1981年7月出版的J.Appl.Phys.52(7)，p.4825-4842中DiMaria等人″Electrically-alterable read-only-memory using Si-rich SI02 injectors and a floating polycrystallinesilicon storage layer，″；1992年4月出版的IEDM 92，p.469-472中Hori等人″A MOSFET withSi-implanted Gate-SiO2 Insulator for Nonvolatile Memory Applications，″.
结论
此外，尽管以特殊范例及变化阐述了本发明，应明白的是本发明在附录权利要求的范围内将受到完全的保护。

Claims (5)

1.一种可以以2n种阈值电平状态或两种阈值电平状态运行复数多个非易失性存储单元块的方法，其中所述2n种阈值电平状态在存储单元运行阈值窗口上间隔开来，而且所述两种阈值电平状态包括所述2n种阈值电平状态中运行阈值窗口内相距最远的两种，且所述复数多个非易失性存储单元块中至少一块最初运行在所述2n种阈值电平状态下，直到所述复数多个非易失性存储单元块中所述至少一块的擦除/编程周期达到事先设定的数量，在这种情况下，所述复数多个非易失性存储单元块中所述至少一块存储块随即在所述两种阈值电平状态之间运行，其中n是大于等于2的正整数。
2.根据权利要求1所述的方法，其中所述复数多个非易失性存储单元块中至少一个的存储单元运行于所述的两种阈值电平状态，并且所述复数多个非易失性存储单元块中至少另一个的存储单元运行于所述2n种阈值电平状态。
3.根据权利要求2所述的方法，其中将存储有用户数据的存储块表格写入所述复数多个非易失性存储单元块的至少一个中运行在所述两种阈值电平状态下的所述存储单元，并且把用户数据存储在所述复数多个非易失性存储单元块的至少另一个中运行于所述2n种阈值电平状态下的所述存储单元中。
4.在一具有多个存储单元的NAND快闪非易失性存储系统内，一种以第一模式或第二模式运行的方法，所述方法包括：
当以所述第一模式运行时：
将来自至少两个不同数据页面的至少两比特编入多个存储单元中的各存储单元，所述至少两比特被编程为2n种阈值电平状态，且所述2n种阈值电平状态在所述多个存储单元运行阈值窗口上间隔开来，其中n是大于等于2的正整数；
当以所述第二模式运行时：
将来自所述至少两个不同数据页面中的所述至少两比特中的一比特编入所述多个存储单元中某些存储单元中的各存储单元，而没有将来自所述至少两个不同数据页面中的所述至少两比特中的另一比特编程；
只使用所述2n种阈值电平状态中相距最远的两个来编程所述至少两个不同数据页面中的所述至少两比特中的所述一比特。
5.一种可以以2n种阈值电平状态或两种阈值电平状态运行复数多个非易失性存储单元块的方法，其中所述2n种阈值电平状态在存储单元运行阈值窗口上间隔开来，而且所述两种阈值电平状态包括所述2n种阈值电平状态中运行阈值窗口内相距最远的两种，将各存储块的存储单元擦除至运行阈值窗口范围内所述2n种阈值电平状态的一最低阈值电平状态，然后在所述2n种阈值电平状态运行时，通过所述运行阈值窗口范围内的验证电平将已擦除的所述存储单元的一部分编程，使其从所述2n种阈值电平状态的所述最低阈值电平状态转换成所述2n种阈值电平状态中的其它状态，而且在所述两种阈值电平状态下运行时，通过从所述极端阈值电平状态下最大限度移动的验证电平，将已擦除的所述存储单元的所述部分编程，使其从所述2n种阈值电平状态的所述最低阈值电平状态转换成所述2n种阈值电平状态中的另一种，其中n是大于等于2的正整数。
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US6717847B2 (en) 2004-04-06
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