CN1556996B - 导电制品、组合件和导电轨线 - Google Patents
导电制品、组合件和导电轨线 Download PDFInfo
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- CN1556996B CN1556996B CN02818506.4A CN02818506A CN1556996B CN 1556996 B CN1556996 B CN 1556996B CN 02818506 A CN02818506 A CN 02818506A CN 1556996 B CN1556996 B CN 1556996B
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- nanotube
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
揭示了纳米管膜和制品及其制造方法。一种导电制品(1800)包括纳米管段的聚集,其中纳米管段(1802)和其它纳米管段(101)相互接触,形成沿着制品的许多导电通路。这些纳米管段(1802)可以是单壁的碳纳米管,也可以是多壁的碳纳米管。不同的段可以有不同的长度,同时其长度还可以短于制品的长度。如此形成的制品可沉积在基片上,并可在所述制品内部形成纳米管的导电网络。
Description
相关申请的交叉引用
本申请与下列申请相关,它们全部转让给本申请的受让人,而且它们全部为参考结合于此:
使用纳米管带子的电子机械存储器阵列和其制造方法(美国专利申请系列号09/915093,2001年7月25日提交);
用纳米管技术制造的具有存储单元选择电路的电子机械存储器(美国专利申请系列号09/915173,2001年7月25日提交);
具有纳米管电子机械存储器的混合电路(美国专利申请系列号09/915095,2001年7月25日提交)。
背景
1.技术背景
本发明总体上与碳纳米管膜、织物、层和制品相关,具体是与从碳纳米管膜、织物、层或制造导电制品用于不同的电路等相关。
2.相关技术的讨论
小于10nm范围的导电超薄金属层和电极的可靠制造是有问题的,例如可见S.Wolf的《VLSI时期的硅加工》,卷II—“过程整合”(LATTICE出版社,SunsetBeach1990)。在此尺寸范围内的金属膜通常是不连续的,而且在宏微距离上不导电。还有,这样小于10nm的膜易于受到电流的热损坏,而不适于应用在如半导体器件的电路内部连线中。因低电导率而产生的薄膜金属内部连线热损伤是阻碍高集成半导体器件显著小型化和性能提高的主要因素之一。
常规的连接技术有受到热损伤和金属扩散而使电气性能下降,使半导体器件的性能降低的趋势。当尺寸缩小到目前的0.18-0.13um水平时,这些因素的影响就更明显了,例如在超薄的门氧化物层中金属的扩散所导致的影响。
这样,在本领域中就需要在高电流密度或严峻的热条件下可以良好运行的导电元件。这包括特征尺寸小的电路,但也包括其它更大电流密度和严峻热环境的情况。也需要一种导电元件,它不大会将不合适数量的污染物扩散到另外的电路元件中。
发明简述
本发明提供了纳米管膜和制品以及其制造方法。本发明的一方面,是一种包含纳米管段聚集体的导电制品,其中一个纳米管段和其它纳米管段相接触形成沿制品中的许多导电通道。
本发明的另一方面,该纳米管段可以是单壁的碳纳米管,或是多壁的碳纳米管。不同的段可以有不同的长度,还可以包括有小于制品长度的段。
这样形成的制品可以置于一基片上,并在制品本身内部形成纳米管的电网络。
在本发明的另一方面,通过在基片上形成一层纳米管织物,在该织物内形成线路图,该线路图对应于导电制品,来在基片上生成导电制品。
在本发明的另一方面,通过使用一种催化剂,如气相催化剂、气相金属催化剂,使纳米管在基片上生长而形成纳米管织物。
在本发明的另一方面,将悬浮有纳米管的溶液涂覆在基片上来形成纳米管织物。要涂覆溶液可以旋转来实现溶液的旋转涂覆。
在本方面的另一方面,可将基片浸入溶液中而用该溶液涂覆。
在本发明的另一方面,是在基片表面上喷射含纳米管的气溶胶来生成纳米管织物。
本方面提供了一种制造导电纳米管薄膜的方法。在本发明的一个方面,提供一个基片,引入一种蒸气相催化剂来促进纳米管的生长。也引入一种碳源物质用来生长纳米管层,它基本上与基片的主表面平行。
在本发明的另一方面,该蒸汽相催化剂是金属茂。
在本发明的另一方面,导电制品在基片上生成,是通过在基片上形成一层纳米管织物;在织物内形成线路图,此线路图对应于导电制品;除去织物的一部分,使得有线路图的织物留在基片表面形成导电制品。
在本发明的另一方面,在基片上形成导电制品,是先提供一个基片,引入蒸汽相催化剂以促进纳米管的生长,并引入一种碳源物质用来生长一层纳米管,该层与基片的主要主表面基本上平行。
在本发明的另一方面,在基片上形成导电制品,是先提供一个基片,提供一层有线路图的材料,引入蒸汽相催化剂以促进纳米管的生长,并引入一种碳源物质用来在线路图限定的范围内生长一层纳米管,该层与基片的主表面基本上平行。
在本发明的另一方面,该有线路图的材料层是绝缘体或是半导体,而纳米管在 该有线路图的材料层上面生长。
在本发明的另一方面,该有线路图的材料层是金属的,而纳米管在该有线路图金属层以外的范围中生长。
附图简述
在附图中,
图1显示依据本发明的某些实施方式,一种纳米管带子纵横制存储装置;
图2A-B显示依据本发明的某些实施方式,一种存储单元的两种状态;
图3显示依据本发明的某些实施方式,制造存储装置的方法;
图4-11显示依据本发明的某些实施方式,产生一种中间结构用于制造忆体装置的几种形式;
图12显示用来制造本发明的某些实施方式的非织造纳米管织物或毡合的纳米管层;
图13显示与本发明的某些实施方式中毡合的纳米管层与隐藏的、下面的轨线的关系;
图14显示本发明某些实施方式的寻址逻辑;
图15显示本发明实施方式的一种混合技术,其中记忆核心使用了纳米管技术;
图16显示本发明实施方式的一种混合技术,其中记忆核心和寻址线使用了纳米管带子技术;
图17显示依据本发明某些实施方式制造导电制品的步骤;
图18显示依据本发明某些实施方式的导电器件如何与电气元件连接;
图19显示依据本发明某些实施方式来制造一个中间层结构的方法;
图20显示用来制造本发明某些实施方式的非织造纳米管织物和毡合纳米管层。
详细描述
揭示了新的电子机械存储器阵列和其制造方法,其中电子机械存储单元按照类似于WO01/03208中所述NTWCM装置的操作生成,该文献全文参考结合于此。但是,和WO01/03208中所述的NTWCM装置不同,用毡合的纳米管层或非织造纳米管织物所制成的新带子被用来作为导电元件。在本发明中,这种带子被称为导电元件的轨线。在有些情况下,带子是悬置的,在其他情况下,带子是在基片上的。在有些情况下,它们用来在电控制下转向某些特定的状态,而在其他情况下,它们并不移动, 而只是用来承载电流或电压。这种新的纳米管带子被认容易以所需的集成度和规模(所生产的装置数)制造,而且其几何形状也较易控制。此新的纳米管带子被认为能够容易承载大电流密度,而没有前述的金属轨线所产生的问题。
依据本发明的某些实施方式,导电制品可从纳米管织物、层或薄膜制成。直径小至1nm的碳纳米管是可承载极大电流密度的导电体,参见如:Z.Yao,C.L.Kane,C.Dekker,《Phys.Rev.Lett.》84,2941(2000)。它们也有已知最高的导热率,参见如S.Berber,Y-K.Kown,D.Tomanek,《Phys.Rev.Lett.》84,4613(2000),并且是热稳定和化学稳定的,参见如P.M.Ajayan,T.W.Ebbesen,《Rep.Prog.Phys.》60,1025(1997)。但是,使用单根的纳米管是有问题的,因为使它们以合适的受控取和长度等生长是困难的。由纳米管织物生成轨线,能使轨线保留单根纳米管的很多即使不是全部的优点。而且用纳米管织物生成的轨线有单根纳米管所没有的优点。例如,因为轨线由很多纳米管聚集组成,当其当单根纳米管失效损坏或破损后,轨线都不会失效。而是,在给定的轨线中有很多交错的路径能让电子在轨线中运行。在效果上,由纳米管织物生成的轨线,在所形成的轨线中中产生了一根根纳米管组成的自身电网络,其中每根纳米管均能传导电子。还有,使用纳米管织物,层或薄膜,使用现有技术就能制造这样的轨线。
纳米管带子纵横制存储器(NTRCM)
因为新型的纳米管纵横制存储器器件的运行和NTWCM相似,它们的结构描述和运行原理在此从略,其描述和背景可参见WO01/03208。
图1显示依据本发明优选实施方式的原理所构建的一个典型的电子机械存储器阵列100。
该阵列有很多非易失性存储单元103,可置于“开”或“关”的状态。这样的单元的确切数目对于理解本发明并不重要,但是,有关技术可支持其信息存储容量与现代非易失性电流装置的容量相当或更大的器件。
每个存储单元103包括一根纳米管带子101,它通过一个或多个支撑层102悬置在电路轨线或导线104上方。
每根带子101和导线如104的交叉,形成了一个交叉结,形成了一个存储单元。在有些实施方式中,各个单元通过对电极112(该电极与带子101电路连通施加电流或电压,或通过与轨线或导线104连通的电极(未显示)可被读写。支撑层102是氮化硅(Si3N4)层108。在层108的下面是门氧化物层109,它将n—掺杂的硅轨 线与下面的硅晶片110分隔。
试联合参见图1-2B,结106显示了在第一种物理和电学状态的单元,其中纳米管带子101和对应的轨线104分隔。结105显示了在第二种物理和电学状态的单元,其中纳米管带子101转向对应的轨线104。在第一种状态中,结是开路的,当就这样寻址时,它可在带子101子或轨线104上被探测到。在第二种状态中,结是个整流结(如Schotty或PN结),当就这样寻址时,它可在带子101或轨线104上被探测到。
在某些实施方式中,纳米管带子101可通过摩擦固定在支撑层上,在其它的实施方式中,带子可用其它方法来固定,如使用任何其它的技术将带子锚定在支撑层上。通过化学相互作用可使摩擦增强,包括通过例如芘或其它化学活性物质的碳化合物来进行共价结合。蒸发或旋涂的材料如金属、半导体或绝缘体,尤其是硅、钛、二氧化硅或聚酰亚胺也可加入用以提高锚定的强度。纳米管带子或单个的纳米管也可使用晶片结合在表面上。参见R.J.Chen等。“用于蛋白质固定化的单壁碳纳米管的非共价边壁功能化”美国化学会杂志。,123,2001,3838-39和Dai等,《应用化学通讯》77,2000,3015-17,其中描述了用金属锚定和涂布纳米管的典型技术。也可参见WO01/03208中的技术。
在图2A-B显示的某些优选的实施方式中,纳米管带子101的宽度约为180nm,它锚定在优选由氮化硅制成的支撑层102上。在带子101下面的轨线104的局部区域形成n—掺杂的硅电极,且在接近支撑层102的位置,其优选的宽度不超过带子如180nm的宽度。从支撑层102的顶部到带子101连接电极206的下弯位置(见图2B)的相互间距208应为5-50nm。此间距208的大小的设计应与存储器的电子机械开关性能适应。对于此实施方式,5-50nm的间距对于使用纳米管制成的带子101的某些实施方式是优选的,但对其他材料,其他间距也可能较好。这个间距大小是由下弯的纳米管带子的应变能和附着能的相互作用而产生的。这些特征尺寸是现代制造技术所提出的。在其它实施方式中,根据制造设备的能力,该下弯尺寸或大或小。
某些实施方式的纳米管带子101是由一种缠绕或毡合的纳米管非织造织物形成的(下面将详述)。这个带子的开关参数单个的纳米管相似。这样,预计的带子的开关时间和电压大约和纳米管的开关时间和电压相同。和先前依赖于单个纳米管的定向生长和化学自组装的技术不同,本发明的优选的实施方式中,使用薄膜和平版印刷的制造技术。这种制造方法能产生超大的表面,尤其是至少6英寸的晶片。(与 此相反,让纳米管生长超过毫米级的尺寸现在还不可能)带子与单个纳米管相比,应有更好的缺陷容忍性,这是因为在带子中提供了许多导电通路的缘故。(如果带子中一根纳米管损坏了,其它纳米管还能提供其它导电通路,而如果使用单根纳米管,存储单元就损坏了)。还有,带子的电阻应比单根的纳米管小得多,这样就减少了阻抗,因为纳米管带子可比单个纳米管制成更大的截面积。
图3显示某些实施方式的NTRCM装置100的制造方法。先制造或提供第一中间结构层302。在所示的实施方式中,结构层302包括一个硅基片110,它具有一个绝缘层109(如二氧化硅)和一个氮化硅层108,后者形成很多支撑层102。在此例中,支撑层102是由图案化的氮化硅排形成,但是其它的排列也可能,例如很多纵列。导电轨线104在支撑层102之间延伸。在此例中,轨线104与支撑层102是基本互相接触的,但其它的排列以及另外的几何形状也有可能,例如:轨线104和支撑层102之间可以有空间,轨线104可以是导线的形状或是非矩形的纵截面或横截面,包括三角行或梯形。牺牲层304位于轨线104上方,和支撑层102的上表面形成一个平表面306。此平坦的表面,下面将要叙述,有助于形成一层毡合的纳米管层。
一旦结构302制成或提供了后,其上表面306上施加一种催化剂308。例如,某些实施方式中,一种含铁(Fe)、钼(Mo)、钴或其它金属的金属催化剂,用旋涂或其它技术施加上去形成一个第二中间结构层310。
然后,一个毡合的纳米管层312在单壁纳米管非织造织物中生长以形成第三中间结构层314。例如,第二中间结构层可置于一加热炉中,加热至高温(如800-1200℃),同时将含有碳源物质、氢气和惰性气体如氩气或氮气的气体吹过上表面。此气氛使得单壁碳纳米管的毡合层或膜312有可能产生或生长。312层主要是一个纳米管的厚度,不同的纳米管之间通过范德华力相互连接。偶而会有一个纳米管在另一个纳米管的上面生长,但是因为此材料的生长特性,这种生长是不常见的。在一些实施方式中(图中显示),催化剂308的分布可以图案化,使得纳米管以某些密度生长,可比要求的密度高或低。当催化剂组成和密度、生长气氛和时间条件适当地控制,在一指定区域内纳米管可以均匀地分布,且主要是单层。合适的生长要求控制的参数包括但不限于催化剂的组成和浓度、下面表面的功能化、旋涂参数(长度和每分钟转数)、生长时间、温度和气体浓度。
一层光致抗蚀剂可施加在层312上,且可以是图案化分布的,用以形成在毡合纳米管层312形式的带子。该带子的图案穿过(例如垂直)下层的轨线104。去除 光致抗蚀剂后,留下非织造的纳米管织物带子101在306平面上,形成第四中间层318。
第四中间层318中有一些部分320,露出其下在的牺牲层304。结构318然后用酸如HF处理,除去牺牲层304,包括带子101下面的部分。这样就形成了悬置在轨线104上面并由支撑层102支撑的带子101的阵列322。
接下来的金属化可用来形成寻址电极,如图1所示的112。
上述技术的一个方面是不同的生长、图案化和腐蚀操作可以使用常规技术。如平版印刷图案化。目前,它可以产生的特征尺寸(如带子101的宽度)为约180nm到小至130nm。但如制造技术容许,元件的物理性能可使其特征尺寸更小。
下面将要进行解释,有很多可能的方法用来生成上述中间结构层或相似的结构层。图4,就显示了一种生成第一中间结构结构层302的方法。
一个硅晶片400带子有氧化物层402。该氧化物层优选地是有几个纳米厚,也可厚至1微米。一层氮化硅(Si3N4)层404沉积在氧化物层402的上面,氮化硅层优选至少有30nm厚。
氮化硅层然后经图案化和腐蚀产生凹穴406,形成支撑结构407。使用现代技术,凹穴的宽度可以是180nm或更小。剩下的氮化硅材料则形成支撑层102(例如成排或纵列)。
然后将n—掺杂的硅覆盖层408沉积上去,填满凹穴406。典型的覆盖层408的厚度是1微米,但可薄至30nm。
覆盖层408然后经过加工,例如用厚硅层的自平化或退火,形成平表面306,如上所讨论的,形成结构411。若用的是自平化,可以使用带子终点探测(EPD)的反应性离子腐蚀(RIE)进行,直至达到经腐蚀的氮化硅的上表面410。
结构411然后进行氧化以形成二氧化硅牺牲层304,它在平表面306以下10-20nm深。
未转化的余下的硅则形成轨线104。
图5显示出另一种制造方法可用来形成NTRCM器件100。先提供一个如图4中所示的一个支撑结构407,然后用CVD、溅射或电镀的方法加上一层n—掺杂硅层514。在某些实施方式中,所加的层514的厚度是氮化硅支撑层102厚度的一半。
层514加上以后,使用退火操作以生成一平表面306,形成如上所述的结构411。该退火操作使层514中的硅流入到凹穴406中。
如就图4所述的,结构411然后经过氧化,形成二氧化硅牺牲层304,它深入 平表面306以下10-20nm。
图6显示形成另一种第一中间结构层302’的另一种方法。在此实施方式中,一个硅基片600上覆盖有一层氮化硅层602,其厚度604至少为30nm。
氮化硅层602然后经图案化和腐蚀以产生凹穴606并形成支撑层102。该腐蚀操作暴露出硅基片600表面的一部分608。
暴露的硅表面608经氧化以产生一个二氧化硅(SiO2)层610,其厚度为几个纳米。这些层610最终绝缘了轨线104,其方式与上述结构302中的绝缘层109相似。
一旦绝缘层610形成后,轨线104可用多种方法制备。图6显示了图4-5中的制造步骤,用来生成这样的轨线进行说明。
图7显示另一种形成第一中间结构层302的方法。一个硅基片700上具有一个二氧化硅层702和一个氮化硅层704,其上面再有图案化的光致抗蚀剂层706。例如,一个光致抗蚀剂层可旋涂在层704上,再经曝光和光刻显影。
反应性离子腐蚀(RIE)等方法可以用来腐蚀氮化硅层704,形成凹穴708而并形成支撑102。
然后,n—掺杂的硅710可沉积进入凹穴708中,在某些实施方式中,硅的沉积高度大约与氮化硅支撑层102的高度712相同
然后揭去光致抗蚀剂706和在光致抗蚀剂706上的硅710,形成如上所述的中间结构层411。
结构411然后经氧化生成二氧化硅牺牲层304。
图8显示生成第一中间结构层302的另一种方法。在这种方法中,提供一起始结构800,它具有最低的硅层802,其上有最低的二氧化硅层804。第二硅层806置于层804上,而第二个二氧化硅(SiO2)层808又置于第二硅层806之上。
顶部的二氧化硅层808经光刻图案化,生成RIE掩模810。此掩模用来腐蚀第二硅层806的外露部分812,直到第一二氧化硅层804。该腐蚀操作生成凹穴814并形成轨线104。
凹穴814用氮化硅(Si3N4)816填满和覆盖之。
此氮化硅覆盖层经RIE背腐蚀达到高度818,和覆盖着n—掺杂硅电极104的二氧化硅层806余下部分一致(形成牺牲层304)。
图9显示形成另一第一中间结构层302”的方法。在此方法中,先提供类似407的结构(在图4中显示,图9中未显示)。在此例子中,Si3N4支撑层102的高度约为30nm。一金属薄层902沉积在Si3N4支撑层102的上面,并沉积在凹穴904底部 的SiO2外露的部分上,此沉积的部分标为903。金属902和903形成暂时的电极。然后,用电镀方法沉积或生长一层n—掺杂硅层906,覆盖着电极903,直至硅层906的高度908达到支撑102层顶部,并和电极902接触。此生长过程可通过起动上下金属电极902,903之间的电流而加以控制。
外露的金属电极902可用湿化学方法或干化学方法加以去除。这就形成了中间结构层411’,和上述411结构相似。但具有一个埋入的电极903,作为硅生长过程的结果。
结构411’然后经氧化形成。位于硅的外露部分的牺牲层304,如上所述。例如,牺牲片层304可生长至厚度为10nm。
图10显示形成第一中间结构层302的另一方法,将一个硅基片1002用作起始材料,其上有一个二氧化硅层1004,而在层1004上有第二硅(n-掺杂的)1006。在1006上有经光刻图案化的掩模1008。
使用氮化技术,使n—掺杂硅层1006的外露部分1010化学转化为氮化硅支撑层102。1006层的未转化的部分形成轨线104。
将掩模1008除去形成一个如上所述的结构411。
硅表面外露的部分1012经氧化形成二氧化硅牺牲层304。
图11显示生成又一个第一中间结构层302”’的方法。在此方法中,覆盖有氮化硅薄膜1104的硅基片1102作为起始材料,在氮化硅层1104的顶部,施加上n—掺杂硅,RIE并光刻图案化,形成轨线104。
轨线104的表面经氧化以形成二氧化硅层1106,作为牺牲层304’的另一种形式。
此结构的的上面再生长氮化硅层1108,背腐蚀以形成平面306,从而形成又一种第一中间结构结构层302”’。如本领域中有经验的人士所熟知的,在此方法中,当牺牲层304后来去除后,轨线104会和支撑层102分离。此技术的一些变体可用来生成轨线104另一种横截面形状。例如,轨线104可制成上部圆形的,或有三角形或梯形的横截面。另外,横截面还可以有其它形状,如带子有渐缩边的三角形。
如上所述,第一中间结构层如302形成后,使一个毡合的纳米管层312生成在层302的平表面306上。在优选的实施方式中,此非织造织物层312生长在此结构上,此时使用催化剂308并通过生长环境的控制。其它实施方式可另行先提供毡合的纳米管层312,然后直接施加在结构302之上。虽然结构302,运用此方法优选地包括牺牲层来提供一个平表面来接受先行生长的织物,但在此方法中,牺牲层可以是非必需的。
因为此生长过程导致这种纳米管的下面与中间结构层302的平表面306相接触,它们显示出一种“自组装”的特点,如图12所示。具体是,一个个纳米管会在其生长的表面上附着,只要在能量上是有利的,这样它们就基本形成一个“单层”。有些纳米管会在其它纳米管上面生长,从而此单层并不是完善的。单个的纳米管并不和其它纳米管互相毡合起来,而是靠范德华氏力相互附着。图12大致显示了一种实际的非织造纳米管织物。因为纳米管的特征尺寸很小,即使现代的扫描电镜SEM也不能将真实的织物拍摄下来而不损失精度;纳米管的特征尺寸为1-2nm,小于SEM的精度。例如,在图12中,显示了织物的毡合特性;图中并不清晰,织物中可能有小范围的间断,其中不存在纳米管。每个纳米管的直径典型的是1-2nm(这样就确定了织物的厚度也是1-2nm),但长度是几个纳米,有些甚至是200nm。纳米管可以是弯曲的,偶而也会互相叉。纳米管之间通过范德华氏力相互附着。
在某些实施方式中,纳米管在X-轴和Y-轴方向上基本上不受限制地生长,但在Z-轴方向上(垂直于图12的纸面)生长受到限制,这是因为有自组装的特性。其它实施方式可以补充上述方法,用场定向或流定向的方法生长技术来生长毡合物312。这样的补充可用来对生长人为设定,如阻止沿一个方向(如X-轴)的生长。这样能以可控的密度形成一层平坦单层的相互交织的纳米管层,更均匀地覆盖所需要的表面。
图13显示了毡合的纳米管层312和其下面的硅轨线104。
如上所解释的,在表面306上有了毡合的纳米管层312以后,将层312图案化和腐蚀,形成纳米管织物带子101,它跨越在支撑层102之上。然后除去牺牲层(如用酸),形成阵列322,如上面图3所示。因为纳米管毡合层312形成的非织造的织物是不连续的,所以腐蚀剂或其它化学试剂可能渗透至纳米管“纤维”之间,并很容易地达到下面的部件,如牺牲层。
接着的金属化可用来形成寻址电极,如图1中所示的112。其它实施方式使用纳米管技术来实现存储单元的寻址,而不使用金属化电极112和寻址线(未显示)。
更具体的,在上述某些实施方式中,纳米管可用来形成NTRCM阵列。某些实施方式使用纳米管技术,不管是单根的导线还是带子的形式,用来执行寻址逻辑来选择存储单元进行读写操作。此方法还整合了纳米管技术和系统设计,有利于更高级别的系统设计。例如,在此方法中,存储器结构不仅能以非易失性电流的方式存储记忆内容,还能存储过去的记忆地址。
基于纳米管的存储单元是双稳态的,其特点是“0”和“1”状态的高电阻比。 这两个状态的转换是将某些电压加到纳米管导线或带子和下面的轨线上,其中至少一个存储单元是纳米管或纳米管带子。在一个方法中,加上一“读出电流”并用一个“读出放大器”测出此结上的电压。读是非破坏性的,意思是破碎器单元仍保持其状态,不必象DRAM那样需要回写操作。
图14显示纵横制对分选择系统或解码器1400。下面还将说明,解码器1400可由纳米管或纳米管带子技术形成。还有,解码器可以建立在如用一个纳米管存储单元阵列如NTRCM或NTWCM的相同电路元件上。
两根线1404和1406的垂直相交点1402,表示两根纳米管或纳米管带子的结。在此方面,其相互作用和CMOS和其它技术中发现的“通过半导体”相似,其中,此交叉可以是敞开或封闭的。
如1420的那些位点,在该处一个纳米管或纳米管带子和别的纳米管或纳米管带子相交,但不拟生成一个交叉结可以用元件之间光刻图案化的绝缘体来互相绝缘。
为清晰起见,所显示的解码器是用于一个3位的两进行地址,承载在寻址线1408上。根据编码的值,交叉(点)会转换来产生仅仅一条通路,传感电流可以通过该道路来选择线1418。
使用这个技术,两进制地址的每个位的一个“双轨”表示1408均在外部形成。这样地址位1410的每一个均以真和补充的形式表示。这样,线1406可以是地址线1408a的逻辑上真空的形式,而线1407可以是地址线1408a的逻辑补充。表示1408的电压值与上述将纵横制结转换到“1”或“0”状态所必需的电压是一致的。
这样,一个地址1408可以用来对一个阵列中的位或一排位例如纳米管或纳米管带子提供传感电流I。相似地,同样的方法也能用来感受一给定的轨线,例如,结合选择一个排选择由其读取感受的特定纵列。因此这样的方法可能用于X和/或Y解码,用于读或写的操作。
本发明的某些实施方式提供一种混合技术,电路1500,如图15所示,一个用NTWCM或NTRCM构建的核心存储单元阵列,该核心被一个半导体电路包围形成X和Y地址解码器1504和1506;X和Y缓冲器1508和1510;逻辑控制1512和输出缓冲器1514。包围NTWCM或NTRCM核心的电路可用于常规的接口功能,包括提供读取电流和读取输出电压。
在其他实施方式中,X和Y地址解码器可被上述的纳米管导线或带子寻址技术所替代。在这些实施方式中,核心会包括存储单元和寻址逻辑。
在某些实施方式中,可用一个纳米管核心(只具有存储器单元或具有储存器单元和寻址逻辑)和用一个场可编程门阵列实现周围电路来形成混合电路1500。核心和门阵列电路如果需要,可在一个物理包装内,也可分别包装。例如,一个密闭包装的纳米管电路(具有存储器或存储器和寻址逻辑)可以与一个PLD/FPGA/ASIC组合,其中I/O接口也在内。所得的完整的芯片组对于产品的用户而言,可以获得纳米管存储器带来了好处,同时能最大限度地使用现有的技术,该技术可被制造厂家以基于需求的方式使用。
图16显示混合技术的一个可能的执行方式。一个含有缓冲和控制逻辑(如上所述)的FPGA芯片1602通过在一个(也许是多层)印刷线路板(PCB)1604上的导电轨线连接到一个含有存储单元和寻址逻辑的纳米管芯片(NT)1606上。
这个具体的实施方式提出能符合当今个人电脑通用的PCI总线标准。其它无源线路,如电容、电阻、变压器等(未不出)也需要符合PCI标准。一个为200MHz~400MHz正面总线速度已作了标示,表明这样的芯片可以这样的外部时钟速度运行。此速度受到PCB内部连线和FPGA/PLD/ASIC的速度以及芯片包装的限制,而不是受纳米管存储单元速度的限制。
碳纳米管薄膜、层、织物和制品
上述NTRCM的实施方式和寻址线使用从纳米管层312制得的轨线或导电制品,如图3和12中所示的。层的厚度为1nm或更小,也就是一个给定纳米管的厚度。纳米管层312是在一个表面上生长或沉积上去的,如硅晶片那样,形成一层给定密度的连续膜。此二维的膜然后可以加以图案化产生导电线或称轨线,其宽度从1nm(纳米管最小的本征尺寸)至几百个纳米或更厚,依据应用和情况而定。此图案可以生成多种长度和宽度范围,使不同大小的半导体器件如晶体管或记忆元件最终相互连接,而且可以展开成为接合垫或其它连接材料或结构。如果有必要,纳米管的连接结构可以金属化,便于和金属或半导体材料相连接,因为金属化后,它容易与金属或半导体材料接触。
此轨线和导电制品可用于其它形式的电路中,例如通常在尺寸非常小的轨线中(如小于10nm的范围)可以使用纳米管轨线,因其能承受大电流密度的特性。使用它们也可减少对其它电路特征的污染。
在图17,例如,显示了在基片上的纳米管带子、轨线或导电制品的典型用途。(经检查,人们可见图17与图3相似,但在这个例子中,膜312是直接生长在基 片上的,而不是将其先生长在中间结构层310表面上的。)在此例子中,硅基片110有一个和图3所示类似的氧化层109。为便于膜312的生长或沉积,可生成一个平坦的表面(在图3中表示为306,而在图17中未表示)。具有单壁/或多壁纳米管的膜312可以使用CVD或旋涂施加在上述这个组合上。如果是使用单壁纳米管,膜312则主要是一个纳米管的厚度,而如果使用多层壁纳米管,厚度则明显增加,如厚达1000nm。
如果要将膜生长上去,则可以使用催化剂,如上所述。但是,催化剂(在图3中表示为308,而在图17中未加表示)不需要直接沉积在基片的表面;代替或附加地催化剂可以以气态的形式并作为CVD过程的一部分。例如,可以使用如二茂铁的气相金属类。二茂铁和其它气相金属物质可生长纳米管,象其它含铁、钼、钨、钴和其它过渡金属的气相物质一样。这些都适合于形成气相中的催化剂。使用气相金属催化剂时,可以对温度、压力、表面准备和生长时间进行优化,来产生纳米管层312。
如果要将膜沉积上去,可以使用预先生长的纳米管。例如,在本发明的某些实施方式中,纳米管可以以溶解或不溶解的形式悬浮在溶剂中,然后经旋涂在表面上,生成纳米管膜312。在这样的排列中,膜的厚度相当于一个或多个纳米管厚度,依据旋涂情几何配置和其它过程参数而异。合适的溶剂包括二甲基甲酰胺、N—旋涂吡咯烷酮,N-甲基甲酰胺,邻二氯苯,对二氯苯,1,2二氯乙烷,乙醇,水,并加有合适的表面活性剂如SDS或TritonX-100或其它。纳米管的浓度和沉积参数如表面官能度、旋涂速率、温度、pH值和时间可加以调节,用以控制按要求纳米管沉积单层或多层的纳米管。
纳米管膜312还能通过将晶片或基片浸入到溶解或悬浮有纳米管的溶液中进行沉积。此膜还可以通过将纳米管以气溶胶的方式喷射到表面上而形成。
当催化剂组成和密度,生长环境,和时间等条件经过适当的控制,纳米管就可以均匀地分布在一个给定的区域上,而且主要是单层纳米管。
在形成纳米管膜312后,一种光致抗蚀剂可以旋涂在纳米管膜312上面,并通过曝光或相似的方法图案化,形成导电轨线。在图17的例子中,轨线显示为平行且直的轨线,但是轨线可形成为其它形式。形成的轨线宽度可为1nm到100nm或更大,取决于所要连接的器件的类型。
形成了轨线后,已曝光的光致抗蚀剂加工除去其一些层,但留下轨线101。接下来可使用金属化形成寻址电极或一个展开的连接结构,如图17中所示的1706。
参见图18,纳米管带子图案1802可和其它带子101、金属带子(未显示)或电子器件1806相连。例如,就中间结构层1800而言,纳米管轨线101可以和有不同特征尺寸如宽度,的纳米管轨线1802相连。轨线101还可以与元件112相连,此元件可为金属接点或结合垫。(但本图中未按尺度显示)。就中间结构层1804而言,轨线1010可和例如1804中的储存元件相连,后者的形式可为NTRCM单元或带有半导体位点。就中间结构层1808而言,轨线可和电子处理位点或逻辑1806相连轨线101还可以和结合垫112相连,但图中该结合垫的显示并未按其尺寸。
虽然这些相互连接主要是单层纳米管的形式,在合适的生长条件下,也可以是多层纳米管带子和纳米管层。这要求控制参数,包括但不限于催化剂组成和密度,其片表面的官能化,旋涂参数(长度和转速,如40秒,50-5000rpm)、生长时间、温度和气体浓度。
上述技术的一个方面,是可以使用不同的生长、沉积、图案化和腐蚀操作,可使用常规技术,如光刻图案化。用了现有的技术,所制得的轨线的宽度可以是从180nm小至130nm。但是,轨线101的物理特性可制成更小的特征尺寸,如果制造条件容许的话。
常规的互连技术有受到热损伤和因金属扩散而使半导体器件性能特别是其电气性能受损的危险。当尺寸缩小到目前的0.18-0.13um水平时,这些因素的影响就更为明显,例如由于超薄门氧化物层中金属的渗透。相反,碳纳米管带子101则不会有这些问题。碳纳米管一般较强,具有已知最高的导热率,不易于受到热损坏。还有,没有金属和掺杂物扩散的情况发生,因为它们是完全由共价连接的碳原子构成的。
图19显示用另一种方法生成第一中间结构层302。一块硅基片1900上面具有一层二氧化硅层1902,再附上一层图案化的光致抗蚀剂层1904。例如:光致抗蚀剂层可以旋涂在1902层上,再经曝光和光刻显影,产生凹穴1906和掩模图案1908。
接下来,n—空穴的硅或金属如钼、钨或钽1910和一个牺牲层1912如氧化铝层可沉积于凹穴1906中,形成所对应的结构1914和1916。
光致抗蚀剂1912以及在光致抗蚀剂1912上面的的材料1914氧化铝1916然后除去,生成一个中间结构层1918,其上面有电极104和牺牲层304。一种可在玻璃上旋涂的(SOG)如可流动氧化物(FOX)旋涂在结构1918的上面,然后使用一种标准的升温步骤在600℃进行退火,生成一个二氧化硅层1920,其在牺牲层1912顶上的高度为200-2000nm。
然后使用反应性离子腐蚀或相似技术来腐蚀二氧化硅层1920,生成带有支撑层102的结构302。
电极材料的选择受到将纳米管施加在基片表面上方法的限制,。上述三种方法包括旋涂基于催化剂的生长,气相催化剂辅助CVD和旋涂或直接沉积。在基于催化剂的生长的情况下,如上所述,催化剂是通过旋涂或将基片浸入到催化剂材料中再用标准的方法进行清洗的方法分布在表面上的。然后,如上所述,纳米管接着通过CVD过程在800℃条件下使用氢气和含碳气体前体组合物来让纳米管生长。此时电极材料应足够稳定能经受这些温度的优选是钼、钨、钽、镉、铜或它们的合金。电极材料可以构建成单层或堆叠的结构,材料是硅、钨、钼、钽、铜或其它。堆叠的电极结构可足以产生Schottky势垒隔,用于每个存储器位的整流。
在使用气相催化剂如二茂铁使纳米管生长的情况下,可以预见到,对于此生长,所需的温度可显著降低,可以使用在比800℃低得多,如低至400℃熔化的材料。某些可用的气相催化剂可包括含5个六元环的钴、钨、钼、或铼的金属茂。这些化合物可用适当的无机化学知识加以合成,并在使用时,在气相中用一起泡器导入,作为基片上的成核位点用于纳米管的生长。当然,这些材料应与文献中已知的典型CMOS过程相适应,并以标准的工业制造设备使用。
如果是在室温条件下通过旋涂纳米管溶液或悬浮液将纳米管沉积在一个表面上,电极材料的选择范围明显变宽。在此情况下,没有高温步骤,任何适合于标准CMOS金属化条件的金属,尤其是铝或其合金,都可以用。
牺牲层304可以用氧化铝,金属氧化物,盐,金属或其它材料。可通过使用不同的材料包括SOG,二氧化硅等生成支撑层102,来形成中间结构层302。在选用低温条件下旋涂纳米管的步骤中,适合作牺牲层的材料范围明显变宽,包括如PMMA或其它聚合物,金属如钨、铬、铝、铋和其它过渡和主族金属这些材料。还可以是其它半导体材料如锗和绝缘体材料如盐,氧化物和其它硫属化物。
支撑层层材料的选择很大程度上取决于纳米管生长所选择的条件和其它因素。在使用低温过程将纳米管生成在表面上时,人们可预见使用这样的材料如氧化铝、一氧化硅、半导体、绝缘体和聚合物如聚酰亚胺。
材料选择的过程受到适合于上述制造过程的材料的限制。本领域中的有经验人士可以明白。选择了一具体电极材料后,牺牲层和支撑层材料也自然受到的半导体制造中通常操作步骤限制。相似的,如果先选定了牺牲层,电极和牺牲层材料的选择也受到限制。同样还有,支撑层材料先选定后,电极和牺牲层材料的选择也类似 地受到限制。
图20显示了一个典型纳米管织物312的原子力显微镜(AFM)的图像。在图中,每个纳米管的直径约为1.5nm(图像的模糊是因为显微镜的本身限制,而不是因为给定纳米管的实际结构)。此图像已是AFM侧向分辨率能力的极限了。
虽然上文所揭示的是当作由纳米管制成的织物是同一类型的,例如全为单壁的纳米管,但织物也可全部由多层壁的纳米管形成,或由单壁和多层壁的纳米管的组合形成。
其它实施方式
为了便于互相连接线或电极材料的生长,有用的是,先用标准的光刻方法形成一个线路图案以形成一个区域,在此区域内纳米管要以水平方式生长在基片表面上。这样的方法已用来形成图案化的SiO2结构,用以生长厚多层壁竖直的纳米管。在一个相似的方法中,图案化的SiO2结构还用来生长水平的纳米管膜,其厚度为1-1000nm,产生如上所述的结构101。当与适当选择气态金属茂或其它可蒸发的金属前体配合生成预定图形的纳米管带子的时候,能提供用于纳米管生长的支撑层和成核位点的其他材料如绝缘体和金属氧化物也是有用的。下面的图案化的层也可用作牺牲层,当其去除后,就生成悬置的纳米管。这种生长方式是一种“阳文”生长的方式,此时纳米管将预先图案化的表面作为成核位点。
在另一个实施方式中,可以设想使用“阴文”的生长方式,昆经光刻图案化的基片含有一种不支撑层纳米管生长的金属或其它材料。当适当的气相前体如金属茂或相似化合物提供时,纳米管只在没有图案化材料的表面上生长。当除去图案化的金属材料后,去除下面的材料就可以得到悬置的纳米管101或互连结构。
在另一个实施方式中,不用湿化学方法去除牺牲层来将纳米管以一特定高度悬置在电极上,而是使用受控的电极腐蚀(即0.18微米宽的电极腐蚀15nm),例如金属(如铜)和半导体(如硅)电极可被腐蚀,其腐蚀速率为每秒几个纳米。
在又一个实施方式中,使用一层覆盖性的薄涂层来将纳米管固定在支撑层上,以防止在操作中纳米管的滑动。这样就能恰在存储单元的上方开一个窗口。
通过控制纳米管带子的截面积,各层和导电制品的电性能可以配合。例如:在给定宽度和纳米管密度的条件下,纳米管的厚度可以增加。截面积越高,就有越多的导电通路得以提高电性能。
上述纳米管的制造方法使得在粗糙形貌的表面上也有连续的导电性。而典型的 金属蒸发方法会产生结构缺陷,因而产生电缺陷。
除了碳纳米管以外,其它电子和机械性能适于做电子机械开关的材料也是可用的。这些材料有和纳米管相似的性能,但是有不同可能和更小的拉伸强度。材料拉伸应变和附着能量必需在一个范围内,能使得结的二稳态性和电子机械开关性能是可以接受的。
为了整合CMOS逻辑用来寻址,可以使用两种方法。在第一种方法中,纳米管阵列在在金属化以前,但在CMOS逻辑器件的离子注入和平面化之后进行融合。第二种方法是在CMOS器件制造(涉及离子注入和高温退火)之前生长纳米管阵列。一旦这些步骤完成后,纳米管带子和CMOS器件的金属化就用广泛使用的标准方法进行。
在某种金属或半导体线上放置含n—空穴硅的电极也是可以设想的。这样会在开的状态时产生整流结,以致不存在多重的电流通路。
除整流结以外,还有其它广泛接受和采用的方法来防止在交叉阵列中电串话现象的发生(也就是多重电流通路的缘故)。在静态的,光刻制成的电极顶部的隧道垫垒能防止形成电阻性“开”的状态。在零偏电压时无漏电流发生,但一个小的偏电压以使载流子克服此在交叉线之间的垫垒隧道效应。
可以设想采用离子的,共价的或其它力来提高附着能量的方法以改变与电极表面的相互作用。这些方法可用于扩展这些结二稳态性的范围。
纳米管可通过平面共轭的碳氢化合物如芘进行功能化,然后能提高带子内纳米管之间的内部附着力。
上述的某些方面,如用于寻址的混合电路和纳米管技术,可用于单个的纳米管(如使用直接生长技术等)和纳米管带子。
本发明的范围并不被上述实施方式所限制,而由所附的权利要求所限定,这些权利要求可以包括对所描述的进行修正和改进。
Claims (15)
1.一种包含纳米管段聚集体的导电制品,其中一个个纳米管段和其它纳米管段接触,形成沿该制品的许多导电通道,所述纳米管段是非织造纳米管织物或毡合的纳米管层,所述纳米管段的图案化是用平板印刷进行的;
其中所述导电制品与至少两个电极元件电连接,形成存储单元;和
其中所述存储单元通过对所述电极元件施加电流或电压可被读写。
2.权利要求1中所述的制品,其中纳米管段包括单壁的纳米管。
3.权利要求1中所述的制品,其中纳米管段包括多层壁的纳米管。
4.权利要求1中所述的制品,其中纳米管段有不同的长度。
5.权利要求1中所述的制品,其中纳米管段包括长度小于制品长度的段。
6.一种组合件,包括一个基片和一个在基片上的导电轨线,此轨线包括相互接触的纳米管段,形成许多沿轨线的导电通路,所述纳米管段是非织造纳米管织物或毡合的纳米管层,所述纳米管段的图案化是用平板印刷进行的,其中所述导电轨线与至少两个电极元件电连接,形成存储单元;和
其中所述存储单元通过对所述电极元件施加电流或电压可被读写。
7.权利要求6中所述的组合件,其中纳米管段包括单壁的纳米管。
8.权利要求6中所述的组合件,其中纳米管段包括多层壁的纳米管。
9.权利要求6中所述的组合件,其中纳米管段有不同的长度。
10.权利要求6中所述的组合件,其中纳米管段包括长度小于轨线长度的段。
11.一种导电轨线,所述导电轨线包括相互接触的纳米管段形成许多沿轨线的导电通路组成的电网络,所述纳米管段是非织造纳米管织物或毡合的纳米管层,所述纳米管段的图案化是用平板印刷进行的,其中所述导电轨线与至少两个电极元件电连接,形成存储单元;和
其中所述存储单元通过对所述电极元件施加电流或电压可被读写。
12.权利要求11中所述的导电轨线,其中纳米管段包括单壁的纳米管。
13.权利要求11中所述的导电轨线,其中纳米管段包括多层壁的纳米管。
14.权利要求11中所述的导电轨线,其中纳米管段有不同的长度。
15.权利要求11中所述的导电轨线,其中纳米管段包括长度小于轨线长度的段。
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- 2002-07-25 EP EP11160083.9A patent/EP2343709A3/en not_active Withdrawn
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- 2002-07-25 AU AU2002353771A patent/AU2002353771A1/en not_active Abandoned
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EP1410397B1 (en) | 2018-07-04 |
KR100899587B1 (ko) | 2009-05-27 |
US20050101112A1 (en) | 2005-05-12 |
WO2003022733A3 (en) | 2003-07-24 |
WO2003027003A2 (en) | 2003-04-03 |
US20030199172A1 (en) | 2003-10-23 |
CN1556996A (zh) | 2004-12-22 |
WO2003027003A3 (en) | 2003-10-30 |
US7335528B2 (en) | 2008-02-26 |
EP2286929B1 (en) | 2018-07-18 |
AU2002357641A1 (en) | 2003-04-07 |
AU2002353771A1 (en) | 2003-03-24 |
EP1410397A4 (en) | 2007-08-29 |
US7264990B2 (en) | 2007-09-04 |
US6835591B2 (en) | 2004-12-28 |
JP2005503007A (ja) | 2005-01-27 |
CA2454845C (en) | 2013-10-01 |
EP1409156B1 (en) | 2012-05-30 |
JP5068921B2 (ja) | 2012-11-07 |
US20070141746A1 (en) | 2007-06-21 |
EP1410397A2 (en) | 2004-04-21 |
EP2343709A2 (en) | 2011-07-13 |
EP2343709A3 (en) | 2013-12-04 |
WO2003022733A2 (en) | 2003-03-20 |
KR20050012707A (ko) | 2005-02-02 |
EP1409156A4 (en) | 2007-08-29 |
EP2286929A1 (en) | 2011-02-23 |
CA2454895C (en) | 2013-06-18 |
EP1409156A2 (en) | 2004-04-21 |
CA2454845A1 (en) | 2003-03-20 |
CA2454895A1 (en) | 2003-04-03 |
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