CN1568551A - 多层相变存储器 - Google Patents

多层相变存储器 Download PDF

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CN1568551A
CN1568551A CN02816937.9A CN02816937A CN1568551A CN 1568551 A CN1568551 A CN 1568551A CN 02816937 A CN02816937 A CN 02816937A CN 1568551 A CN1568551 A CN 1568551A
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CN100470869C (zh
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S·J·赫金斯
T·A·劳里
P·J·克莱尔斯
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Intel Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8615—Hi-lo semiconductor devices, e.g. memory devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Patterning of the switching material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/861—Thermal details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Abstract

可以利用通过阻挡层(24)分隔开的至少两个相变材料层(22，26)形成一种相变存储器(10)。使用多于一个相变材料层(22，26)能够减少编程体积，同时还可以提供充分的热绝缘。

Description

多层相变存储器
背景
本发明通常涉及使用相变材料的存储器。
相变材料可以呈现至少两种不同状态。这些状态可以称为非晶态和晶态。例如，可以通过温度变化来选择启动在这些状态之间的转换。这些状态可以被区别，是因为非晶态通常显示出比晶态更高的电阻率。非晶态包括更无序的原子结构，晶态包括更有序的原子结构。通常，可以使用任何相变材料；然而，在一些实施例中，薄膜硫族化物合金材料特别适合。
可以可逆地引起相变。因此，存储器可以从非晶态变化到晶态并且随后可以回复到非晶态，反之亦然。实际上，每一个存储器单元可以被认为是可编程电阻器，其根据温度变化在高电阻和低电阻之间可逆变化。可以由电阻加热来引起温度变化。
在一些情况中，单元可以具有大量的状态。也就是说，因为每一个状态可以通过其电阻来被区别，多个电阻确定的状态是可能的，允许在一个单一单元中保存多位数据。
各种相变合金是公知的。通常，硫族化物合金包括周期表的第VI族的一个或多个元素。合金的一个特别适合组是GeSbTe合金。
相变材料可以在通过电介质材料定义的通道或者细孔里形成。相变材料可以在通道的其中一端上连接电极。接触可以使电流通过该通道以便通过电阻加热对该单元编程或者读取该单元的已编程状态。
当前相变存储器根据硫族化物相变存储器材料自身的低热导率将可编程体积与上电极热损耗进行热绝缘。因此，为了得到更好的热绝缘，以及由此的可编程体积的更多有效能量编程，不得不增加硫族化物层的厚度。然而，层厚度的增加还增加了在编程期间能够经历相变的材料体积。增加经历相变的材料的体积对存储器的可靠性、稳定性和循环寿命都产生不利影响。
因此，需要具有改善特征和性能的相变存储器。
附图说明
图1是本发明的一个实施例的放大剖面图；
图2是结合本发明的一个实施例制造图1所示器件的早期的放大剖面图；
图3是在结合本发明的一个实施例制造的后期的图2所示的实施例的放大剖面图；
图4是在结合本发明的一个实施例制造的更后期的图3所示的实施例的放大剖面图；
图5是在结合本发明的一个实施例制造的更后期的图4所示的实施例的放大剖面图；
图6是在结合本发明的一个实施例制造的更后期的图5所示的实施例的放大剖面图。
具体实施方式
参考图1，相变存储器10可以在集成电路衬底12上形成。相变存储器10可以包括下电极14，其在一个实施例中由含钴的硅化物形成。上电极28夹在下面的可编程相变层22和上面的相变层26之间。在相变层22和26之间是化学性阻挡层24。
相变存储器10的细孔可以被侧壁隔片20限定。也就是说，在下电极14和相变层22之间的接触区域可以是通过覆盖圆柱形侧壁隔片20所确定的尺寸。在一个实施例中，包括相变层22和26的细孔可以被限定在以成对绝缘体层形成的开口内，例如上绝缘层18和低绝缘层16。在一个实施例中上绝缘层28可以是二氧化硅，在一个实施例中低绝缘层16可以是氮化硅。
尽管示出了其中使用了两层相变材料的结构，但在其它实施例中可以使用更多层。第一相变层22的厚度可以在300-500埃的范围。可以选择该层的厚度以减少可编程体积的垂直尺寸。可以在通过侧壁隔片20形成的杯子形状的开口内淀积相变层22，产生杯子形状的相变层22。因此对阻挡层24和上面的相变层26定义了类似形状。在一个实施例中，可以使用汽相淀积来形成相变层22和26。
阻挡层24提供了在下面的可编程相变层22和上面的相变层26之间的化学阻挡。在一些实施例中，可以首要给上面的相变层26提供热绝缘。阻挡层24可以具有足够的电导率，使得通过可编程相变层22的编程电流在热绝缘相变层26的任何电阻区周围横向流动，并且可以接触远离编程区域的该层的传导区。
阻挡层24的典型厚度可以在50-200埃的范围内。热绝缘相变材料层26也可以在原位置被汽相淀积到阻挡层24的上面。热绝缘相变材料层26可以用和可编程相变层22相同的成分形成或者它也可以从具有低热导率的可获得硫族化物材料的范围中选择。在一个实施例中，层26具有小于1E-2W/cm.K的热导率和例如大于40Ω-1cm-1的良好电导率是很有优势的。层26的厚度可以在从100到多于1000埃的范围。
参考图2，可以在包括衬底12的叠层上定义掩膜30，该衬底12覆盖有下电极14、第一绝缘层16、第二绝缘层18。
下面参考图3，可以通过绝缘层16和18腐蚀开口32，该腐蚀中止于下电极14。在一个实施例中，可以使用一种蚀刻剂，其被选择针对层16和18，而对电极14几乎无效。随后，如图4所示，可以将绝缘材料20淀积到细孔内和层18上。可以使用多种绝缘层，包括氧化物。在一个实施例中，可以使用原硅酸四乙酯(TEOS)氧化物淀积工艺。然后对淀积层20进行各向异性腐蚀以便形成圆柱形侧壁隔片20，如图5所示。
然后可以用可编程相变层22覆盖侧壁隔片20和绝缘层18。然后可以用阻挡层24和绝缘相变层26覆盖层22。最后，可以淀积上电极28。因为侧壁隔片20的覆盖，在某种程度上，层22、24、26和28的每一层都被限定为杯子形状的配置。在一些实施例中，然后可以对图6所示的结构进行构图和腐蚀以便形成图1中所示的结构。
通过使用多层的硫族化物层，存储器单元10受益于增强的热绝缘。同时，在编程期间经历相变的材料体积可以相对受限。换句话说，组合的层22和26的绝缘效果可以减少来自存储器10的热损失，提高编程性能。同时，对绝缘层26编程不是必须的，这样减少了在编程期间必须经历相变的材料体积。在一些实施例中，这可以提高存储器10的可靠性、稳定性和循环寿命。
尽管结合受限的多个实施例描述了本发明，但是本领域的技术人员根据其会理解多个修改和变型。附属的权利要求书其意图在于覆盖落入本发明的真实精神和范围内的所有修改和变型。

Claims (36)

1.一种方法，包括：
形成第一层相变材料；
在所述第一层上形成非相变材料；和
在所述非相变材料上形成第二层相变材料。
2.根据权利要求1的方法，包括形成相同材料的第一层和第二层。
3.根据权利要求1的方法，包括形成不同材料的第一层和第二层。
4.根据权利要求1的方法，包括形成导电的非相变材料。
5.根据权利要求1的方法，包括在衬底上形成细孔。
6.根据权利要求5的方法，包括在所述细孔上形成侧壁隔片。
7.根据权利要求6的方法，包括在所述侧壁上形成所述第一层和第二层以及所述非相变材料。
8.根据权利要求7的方法，包括在所述衬底上形成接触并且在所述接触上形成所述侧壁隔片。
9.根据权利要求8的方法，包括将所述接触和所述第一层进行接触。
10.一种存储器单元，包括：
第一层相变材料；
第二层相变材料；和
在所述第一层和第二层之间的非相变材料，所述非相变材料使得所述第一层与所述第二层完全隔离。
11.根据权利要求10的单元，其中所述第一层相变材料是由硫族化物材料形成的。
12.根据权利要求10的单元，其中所述第一层和第二层是不同的相变材料。
13.根据权利要求10的单元，其中所述第一层和第二层相变材料是相同材料。
14.根据权利要求10的单元，其中所述非相变材料是导体。
15.根据权利要求10的单元，包括半导体衬底和在所述衬底内形成的电接触。
16.根据权利要求15的单元，包括在所述衬底上形成的绝缘层，和通过所述绝缘层形成的通道。
17.根据权利要求16的单元，其中所述第一层和第二层至少部分地在所述通道中形成。
18.根据权利要求17的单元，包括在所述接触上的所述通道内形成的侧壁隔片。
19.根据权利要求10的单元，其中所述第一层和第二层是杯子形状。
20.根据权利要求10的单元，其中配置所述第二层相变材料以提供热绝缘。
21.一种存储器单元，包括：
第一层相变材料；和
第二层相变材料，所述第一层相变材料和第二层相变材料中仅其中一层是可编程的。
22.根据权利要求21的单元，包括在所述第一层和第二层之间的非相变材料。
23.根据权利要求21的单元，其中第一层相变材料是可编程的，第二层相变材料用作所述第一层相变材料的绝缘体。
24.根据权利要求21的单元，其中所述第一层相变材料是由硫族化物材料形成的。
25.根据权利要求21的单元，其中所述第一层和第二层是不同相变材料。
26.根据权利要求21的单元，其中所述第一层相变材料和第二层是相同材料。
27.根据权利要求22的单元，其中所述非相变材料是导体。
28.根据权利要求21的单元，包括半导体衬底和在所述衬底上形成的电接触。
29.根据权利要求28的单元，包括所述衬底上形成的绝缘层和通过所述绝缘层形成的通道。
30.根据权利要求29的单元，其中所述第一层和第二层至少部分地在所述通道中形成。
31.一种存储器单元，包括：
第一层相变材料；
不同于所述第一层的相变材料的第二层相变材料；和
在所述第一层和第二层之间的非相变材料。
32.根据权利要求31的单元，其中所述非相变材料是导电体。
33.根据权利要求31的单元，其中配置所述第二层相变材料以提供热绝缘。
34.一种存储器单元，包括：
第一层相变材料；
第二层相变材料；和
在所述第一层和第二层之间的导电非相变材料。
35.根据权利要求34的单元，其中所述第一层和第二层是不同相变材料。
36.根据权利要求34的单元，其中所述第一层和第二层是相同材料。
CN02816937.9A 2001-08-31 2002-08-20 用于形成多层相变存储器的方法和存储器单元 Expired - Fee Related CN100470869C (zh)

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