CN1643545A - 优化图形处理的系统和方法 - Google Patents
优化图形处理的系统和方法 Download PDFInfo
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- CN1643545A CN1643545A CNA038057204A CN03805720A CN1643545A CN 1643545 A CN1643545 A CN 1643545A CN A038057204 A CNA038057204 A CN A038057204A CN 03805720 A CN03805720 A CN 03805720A CN 1643545 A CN1643545 A CN 1643545A
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- 238000000034 method Methods 0.000 title claims abstract description 237
- 238000012545 processing Methods 0.000 title claims abstract description 33
- 238000004891 communication Methods 0.000 claims abstract description 34
- 230000008569 process Effects 0.000 claims description 173
- 239000000872 buffer Substances 0.000 claims description 68
- 238000004458 analytical method Methods 0.000 claims description 20
- 230000015654 memory Effects 0.000 claims description 16
- 230000008859 change Effects 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 238000007689 inspection Methods 0.000 claims 1
- 238000005457 optimization Methods 0.000 description 7
- 230000009466 transformation Effects 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 230000014509 gene expression Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 238000004364 calculation method Methods 0.000 description 3
- 241001269238 Data Species 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000026676 system process Effects 0.000 description 1
- 230000004304 visual acuity Effects 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5083—Techniques for rebalancing the load in a distributed system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
- G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T15/00—3D [Three Dimensional] image rendering
- G06T15/005—General purpose rendering architectures
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/393—Arrangements for updating the contents of the bit-mapped memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/501—Performance criteria
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2210/00—Indexing scheme for image generation or computer graphics
- G06T2210/52—Parallel processing
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/12—Frame memory handling
- G09G2360/121—Frame memory handling using a cache memory
Abstract
Description
Claims (25)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/095,213 US6919896B2 (en) | 2002-03-11 | 2002-03-11 | System and method of optimizing graphics processing |
US10/095,213 | 2002-03-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1643545A true CN1643545A (zh) | 2005-07-20 |
CN1317682C CN1317682C (zh) | 2007-05-23 |
Family
ID=27788216
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB038057204A Expired - Lifetime CN1317682C (zh) | 2002-03-11 | 2003-03-11 | 优化图形处理的系统和方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US6919896B2 (zh) |
EP (2) | EP1662441B1 (zh) |
JP (2) | JP2005520234A (zh) |
KR (1) | KR100959468B1 (zh) |
CN (1) | CN1317682C (zh) |
AU (1) | AU2003212649A1 (zh) |
DE (1) | DE60331482D1 (zh) |
WO (1) | WO2003077120A2 (zh) |
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CN103946823A (zh) * | 2011-11-18 | 2014-07-23 | 英特尔公司 | 棋盘多gpu配置内的可缩放几何形状处理 |
CN105549929A (zh) * | 2008-07-30 | 2016-05-04 | 英特尔公司 | 用于改善图形性能的方法、装置和计算机程序产品 |
CN108694151A (zh) * | 2017-04-09 | 2018-10-23 | 英特尔公司 | 通用图形处理单元内的计算集群抢占 |
US10217270B2 (en) | 2011-11-18 | 2019-02-26 | Intel Corporation | Scalable geometry processing within a checkerboard multi-GPU configuration |
CN108228337B (zh) * | 2016-12-22 | 2021-08-27 | 财团法人工业技术研究院 | 中央处理单元的配置方法及适用此方法的服务器 |
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-
2002
- 2002-03-11 US US10/095,213 patent/US6919896B2/en not_active Expired - Lifetime
-
2003
- 2003-03-11 EP EP05077391A patent/EP1662441B1/en not_active Expired - Lifetime
- 2003-03-11 DE DE60331482T patent/DE60331482D1/de not_active Expired - Lifetime
- 2003-03-11 KR KR1020047014308A patent/KR100959468B1/ko active IP Right Grant
- 2003-03-11 CN CNB038057204A patent/CN1317682C/zh not_active Expired - Lifetime
- 2003-03-11 AU AU2003212649A patent/AU2003212649A1/en not_active Abandoned
- 2003-03-11 JP JP2003575269A patent/JP2005520234A/ja active Pending
- 2003-03-11 WO PCT/JP2003/002823 patent/WO2003077120A2/en active Application Filing
- 2003-03-11 EP EP03708537A patent/EP1499962A2/en not_active Ceased
-
2007
- 2007-02-16 JP JP2007035802A patent/JP4413936B2/ja not_active Expired - Lifetime
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
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CN105549929A (zh) * | 2008-07-30 | 2016-05-04 | 英特尔公司 | 用于改善图形性能的方法、装置和计算机程序产品 |
CN105549929B (zh) * | 2008-07-30 | 2019-11-15 | 英特尔公司 | 用于改善图形性能的方法、装置和计算机可读介质 |
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CN1317682C (zh) | 2007-05-23 |
DE60331482D1 (de) | 2010-04-08 |
JP2007179563A (ja) | 2007-07-12 |
WO2003077120A2 (en) | 2003-09-18 |
EP1662441A1 (en) | 2006-05-31 |
KR100959468B1 (ko) | 2010-05-25 |
JP2005520234A (ja) | 2005-07-07 |
EP1662441B1 (en) | 2010-02-24 |
KR20040104510A (ko) | 2004-12-10 |
US6919896B2 (en) | 2005-07-19 |
WO2003077120A3 (en) | 2004-11-25 |
US20030169269A1 (en) | 2003-09-11 |
JP4413936B2 (ja) | 2010-02-10 |
EP1499962A2 (en) | 2005-01-26 |
AU2003212649A1 (en) | 2003-09-22 |
AU2003212649A8 (en) | 2003-09-22 |
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