CN1643691A - 含侧向电气连接的半导体管芯的半导体管芯封装 - Google Patents

含侧向电气连接的半导体管芯的半导体管芯封装 Download PDF

Info

Publication number
CN1643691A
CN1643691A CNA038065819A CN03806581A CN1643691A CN 1643691 A CN1643691 A CN 1643691A CN A038065819 A CNA038065819 A CN A038065819A CN 03806581 A CN03806581 A CN 03806581A CN 1643691 A CN1643691 A CN 1643691A
Authority
CN
China
Prior art keywords
semiconductor element
semiconductor
recess
circuit substrate
edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA038065819A
Other languages
English (en)
Other versions
CN100409443C (zh
Inventor
M·C·B·埃斯塔西奥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Publication of CN1643691A publication Critical patent/CN1643691A/zh
Application granted granted Critical
Publication of CN100409443C publication Critical patent/CN100409443C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/32105—Disposition relative to the bonding area, e.g. bond pad the layer connector connecting bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33183—On contiguous sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10156—Shape being other than a cuboid at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Abstract

揭示了一种半导体管芯封装。在一个实施例中，半导体管芯封装包括含导电区的电路基板。半导体管芯在电路基板上。半导体管芯包括边缘和边缘处的凹口。焊点通过凹口将半导体管芯和导电区耦合。

Description

含侧向电气连接的半导体管芯的半导体管芯封装
相关申请的对照
本申请要求2001年1月22日提交的美国临时专利申请No.60/351587的申请日的权利。该美国临时专利申请在此全文并入以供参考。
发明背景
存在许多半导体管芯封装。在半导体管芯封装的一个实例中，半导体管芯用引脚安装在引脚框架上。导线将半导体管芯耦合到引脚。导线、半导体管芯和多数引脚框架(除了延伸在外面的引脚)随后被封装在模制材料中。随后，使该模制材料成形。成形后的半导体管芯封装包括模制体，它具有在侧面延伸离开该模制体的引脚。随后，该半导体管芯封装被安装到电路板上。
虽然这种半导体管芯封装很有用，但可以进行改进。例如，作为消费电子产品(例如，蜂窝电话、膝上型电脑等)的尺寸继续减小，越发需要降低电子装置的厚度同时增加装置的密度。此外，需要改善常规半导体管芯封装的散热属性。从芯片散热是半导体封装领域中持续的问题。需要解决的其它问题包括降低电路板上元件的“开态电阻”(RDSon)和减小电路板上元件的定着点。对于这种部件的定着点，在以上的模制封装实例中，在侧面延伸离开模制体的引脚增加了封装的定着点。希望减少这种元件的定着点，从而更多的元件可以置于电路板上。例如，对于包括含源极区、栅极区和漏极区的功率MOSFET的半导体管芯，期望最终实现约1∶1的芯片与封装尺寸的比率而不降低半导体管芯中的有效源区。
本发明的实施例单独和共同地解决了这些和其它问题。
发明内容
本发明的实施例涉及半导体管芯封装。
本发明的一个实施例涉及一种方法，它包括：(a)形成包括由划线限定的多个半导体管芯的半导体晶片；(b)在划线附近半导体晶片中形成多个空腔；以及(c)沿所述划线切割晶片以分开半导体管芯，其中每个被分开的半导体管芯包括垂直晶体管并包括半导体管芯的边缘处的至少一个凹口。
本发明的另一个实施例涉及一种半导体管芯封装，它包括：(a)包括导电区的电路基板；(b)所述电路基板上包括垂直晶体管的半导体管芯，其中该半导体管芯包括边缘和边缘处的凹口；以及(c)通过凹口将半导体管芯和导电区耦合的焊点。
以下将进一步描述本发明的这些和其它实施例。
附图概述
图1(a)示出半导体晶片的背侧的示意性平面图。
图1(b)示出限定于图1(a)所示的半导体晶片的背侧中的漏极连接位置。
图1(c)示出在进一步处理后图1(b)所示的半导体晶片的背侧处的漏极连接位置。
图1(d)示出半导体管芯的背侧上的被溅射的可焊接背部金属。
图1(e)和1(f)示出半导体管芯的侧视图。
图1(g)示出形成凸起的半导体管芯的前侧的透视图。
图1(h)示出沿线A1-A1的图1(g)所示的形成凸起的管芯的一部分。
图2(a)示出半导体晶片中形成凸起的半导体管芯的阵列的平面图。
图2(b)示出切割后芯片支架上多个形成凸起的半导体管芯的透视图。
图3(a)示出形成凸起的半导体管芯的阵列的平面图。
图3(b)示出切割后芯片支架上形成凸起的半导体管芯的阵列的平面图。
图3(c)-3(f)示出贴附散热片时半导体管芯的阵列。
图3(g)-3(j)示出具有散热片的半导体管芯的各种示图。
图3(k)示出沿线A2-A2的图3(h)所示的半导体管芯的一部分的剖视图。
图4(a)-4(d)示出安装在电路基板上时的半导体管芯。
图4(e)是电路基板上半导体管芯的平面图。
图4(f)-4(h)示出被安装到电路基板上时形成凸起的半导体管芯的一部分的剖视图。
图5(a)-5(b)示出安装后回流前电路基板上半导体管芯的透视图。
图5(c)-5(e)示出被安装到电路基板上时半导体管芯的一部分的侧剖视图。
图6(a)-6(b)示出被安装到电路基板上时半导体管芯的一部分的侧剖视图。
图6(c)示出半导体管芯的边角区的放大部分。
图6(d)示出电路基板上半导体管芯的平面图。
图1(a)-6(d)中，相同的标号表示相同的元件。
具体实施方式
在本发明的实施例中，大量漏极位置连接形成于半导体晶片的后侧划线附近。划线限定半导体晶片中半导体管芯的边界。在较佳实施例中，漏极位置连接是半导体晶片的后部形成的圆锥形空腔。这些空腔可以部分或整体地延伸通过半导体晶片。每个圆锥形空腔的外形被选择为使得通过毛细作用的焊点的形成最大化。存在许多不同的封装配置，但在将半导体管芯安装到电路基板时可以产生这些配置中的每一个的最终漏极连接。在板安装过程期间源极和栅极凸起被焊接到电路基板上的各接合区上。
如这里所使用的，半导体管芯封装可以包括安装到任何合适尺寸的任何合适电路基板上的任何合适数量的半导体管芯。本发明的实施例优选是“芯片比例封装”，其中半导体管芯封装的尺寸接近于半导体管芯本身的尺寸。
本发明的实施例具有许多优点。首先，本发明的实施例具有每定着点区的高RDSon。其次，在本发明的实施例中，在管芯周长上通过圆锥形漏极连接使得漏极触点最大化，因此提升了半导体管芯封装的热性能。第三，半导体管芯可以具有贴附到它们背部的散热片。这些散热片可以采取铜条的形式。在使用约4密耳厚的半导体管芯(具有背侧凹槽)时在半导体管芯的背部上提供铜条是实际的方法。第四，在本发明的实施例中，半导体管芯中MOSFET的源极区被直接连接到电路板上的源极触点。这使得到MOSFET的源电流最大并降低了MOSFET的开态电阻(RDSon)。第五，半导体管芯中焊接触点的整个截面积在栅极、源极和漏极上都较大，从而本发明的实施例可用于高电流应用中。第六，在本发明的实施例中，半导体管芯边缘处的凹口促进了焊料在回流(reflow)期间的毛细流动以基本自动形成焊点。从而，可以可重复和准确地形成焊点。
在本发明的实施例中，形成半导体晶片，它包括由划线限定的多个半导体管芯。随后，在划线附近半导体晶片中形成多个空腔。随后，沿划线切割晶片，将半导体管芯分开。每个被切割并被分开的半导体管芯包括半导体管芯的边缘处的至少一个凹口。在某些实施例中，每个边缘可以包括一个或多个凹口。例如，在某些实施例中，半导体管芯的全部四个边缘都可以包括至少一个凹口。
半导体管芯可以包括垂直功率晶体管。垂直功率晶体管包括VDMOS晶体管和垂直双极功率晶体管。VDMOS晶体管是MOSFET(金属氧化物半导体场效应晶体管)，它具有两个或更多通过扩散形成的半导体区。它具有源极区、漏极区和栅极。在源极区中该装置是垂直的且漏极区位于半导体管芯的相对表面处。栅极可以是沟槽的栅极结构或者平面的栅极结构，并形成于与源极区相同的表面处。在操作期间，VDMOS装置中从源极区到漏极区的电流基本垂直于管芯表面。在其它实施例中，半导体管芯中的晶体管可以是双极晶体管。在这种实施例中，半导体管芯的一侧可以具有发射极区和基极区。管芯的另一侧可以具有收集极区。
图1(a)示出半导体晶片20的背侧，其中形成了多个半导体管芯24。半导体管芯24由划线22限定。半导体晶片20可以包括任何合适的半导体材料，包括硅和砷化镓。半导体晶片20的背侧可以对应于半导体管芯24中MOSFET的漏极区。
如图1(b)所示，多个空腔28形成于半导体晶片20内划线22附近。每个空腔28都可以部分延伸通过半导体晶片20或者整体通过半导体晶片20。每个空腔28也都可以是圆锥形，其中圆锥形空腔的较大的部分接近晶片20的背侧而圆锥形空腔的较窄部分接近晶片20的前侧。
可以以任何合适的方式形成任意数量的空腔28。例如，可以通过光刻和蚀刻工艺形成多个空腔28。光刻和蚀刻工艺是本技术领域内公知的。湿法蚀刻和干法蚀刻可用于形成空腔28。在另一个实例中，可以使用激光蚀刻或喷水蚀刻工艺形成多个空腔28。
图1(c)示出附加处理后半导体晶片20的背侧的示意图。可以执行的附加处理的步骤包括背磨半导体晶片，和执行应力消除蚀刻处理。也可以执行背部金属化处理。
在背部金属化处理中，金属被沉积于半导体晶片的背侧。在该处理期间，金属也可以涂覆多个空腔28中的空腔的内壁和下部。可以使用各种工艺将金属沉积到半导体晶片20的背侧上。实例性的工艺包括溅射、离子辅助沉积和汽相沉积。在背部金属化处理期间沉积的金属优选是可用焊接湿化的。实例性的背部金属化金属包括铝、铜、镍、钨等等。
在使半导体晶片20背部金属化后，可以切割半导体晶片以使单个半导体管芯24相互分开。可以以任何合适的方法进行切割。例如，可以使用切割锯或激光来切割半导体晶片20。
图1(d)-1(f)示出被切割和形成凸起后的半导体管芯24。图1(d)-1(f)示出半导体管芯24的背侧示图，其上具有被溅射的可焊接背部金属30。半导体管芯24的边缘在存在之前形成的空腔的位置具有许多凹口34。在该实例中，每边有两个凹口34，半导体管芯24有四个边。但在其它实施例中，每边可以有更多或更少的凹口。
图1(e)-1(f)示出半导体管芯24的前侧上的多个焊料凸起32。焊料凸起32可以用作半导体管芯24中MOSFET的源极和栅极连接。可以在切割过程中该半导体管芯24与其它半导体管芯24分开之前或之后在其上沉积焊料凸起32。可以使用任何合适的焊料沉积工艺将其沉积，包括拾放(pick and place)、模板印刷和电镀。
图1(g)示出放大的形成凸起后的半导体晶片24。如图1(g)所示，半导体管芯24的侧面具有许多凹口34。每个凹口34具有接近半导体管芯24的背侧的较大部分和接近半导体管芯24的前侧的较小部分。如图1(g)和1(h)所示，凹口34在半导体管芯24的背侧开始，并部分延伸通过半导体管芯24。在其它实施例中，凹口34可整体延伸通过半导体管芯24。每个凹口34的深度都可以大于半导体管芯厚度的一半。
每个凹口34都可以是用于漏极触点的齿状位置，并可以类似于半圆锥形状。每个凹口34都可足够深，从而在焊料回流之前凹口34的下部处的焊料可与电路基板上导电接合区上的焊料接触，因此通过凹口34形成侧向电连接。通常，凹口34的基部34(a)上的焊料(未示出)将与电路基板的导电接合区上的焊料形成电连接。该电连接可以是到半导体管芯24的背侧的漏极连接。
参考图1(h)，当半导体管芯24被安装到诸如电路板的电路基板上时，凹口34提供用于焊料流动和接触的位置。倾斜角(θ)确保在形成背部金属层30期间背部金属的全部和一致覆盖到圆锥状凹口的基部。倾斜角的合适角度约60度到约45度。较低的倾斜角(例如，小于约60度)会增加最后和部分形成于凹口34内部的焊点与管芯边缘隔开的可能性。例如，如图4(h)(以下将描述)所示，焊点68下的至少多数导电区64(b)可以在半导体管芯24的周边之外，以确保所形成的焊点68从管芯24延伸离开。可以使用本技术领域内已知的技术形成特殊的倾斜角，这些技术包括激光蚀刻或者化学蚀刻(干法或湿法)。
管芯边缘和焊点处的接触面可以是应力点。优选布置符合漏极触点的电路基板(例如，电路板)上的导电接合区图案，以确保焊点和管芯边缘之间的间隔。管芯中部分形成而非一直穿过半导体管芯的凹口也可以有助于使得所形成的焊点与半导体管芯边缘隔开。
图2(a)-2(b)示出形成半导体管芯的过程，在各管芯上没有散热片。图2(a)示出未被切割的半导体晶片20，它包括多个半导体管芯24和这些半导体管芯24上的多个焊料凸起32。在该实例中，在切割前半导体管芯用焊料形成凸起。在其它实施例中，半导体管芯24可以在切割后形成凸起。在切割半导体晶片20以使半导体管芯24相互分开后，它们被置于芯片支架40上，如图2(b)所示。随后，可以电气测试半导体管芯24。测试后，半导体管芯24可以被置于带上，随后被绕在卷轴上。
可以参考图3(a)-3(k)描述形成在背部上具有散热片的半导体管芯的过程。管芯封装可以呈现改善了的热性能。在以上实例中，散热片具有平面、铜条的形式。但是，在其它实施例中，可以使用具有垂直定向的散热翼片的散热片。
图3(a)示出在切割前具有形成凸起的半导体管芯24的半导体晶片20。在切割后，如图3(b)所示，半导体管芯24被置于芯片支架40中。但与图2(b)不同，半导体管芯24被置于芯片支架40(例如陶瓷芯片支架)中，从而其上的焊料凸起朝下入芯片支架40。如图3(c)所示，焊料糊46可以沉积于半导体管芯24的背侧上。焊料糊46可以包括Pb-Sn焊料或其它合适的焊接材料。随后，如图3(d)和3(e)所示，散热片48被贴附到半导体管芯24的背侧上，随后加热半导体管芯24以回流焊料糊。可使用单个装置来执行图3(c)-3(e)所示的处理步骤。
在某些实施例中，散热片48可以被作标记，以识别半导体管芯。在将散热片48贴附到半导体管芯24上后，可以测试半导体管芯。测试后，半导体管芯24可以被置于带和卷上。图3(i)-3(h)示出从各种方向观察的其上具有散热片48的半导体管芯24。
图3(k)示出凹口34附近半导体管芯的放大部分。凹口34具有基部34(a)。在基部34(a)处可以具有焊料(未示出)。
可以参考图4(a)-4(h)描述半导体管芯的安装。
图4(a)示出具有多个导电区64的电路基板62。电路基板62可以是电路板或者用于半导体管芯的载体。电路基板62可以包括一个或多个绝缘层，其包括聚合或陶瓷材料。导电区64可以是可焊接金属轨迹的形式，诸如导电接合区、导电线路等。
图4(b)示出导电区64上形成的多个焊料凸起66。这多个焊料凸起66可以通过电镀、型板喷刷、拾放、丝网印刷等方式形成。
如图4(c)所示，在侧边具有凹口34的半导体管芯24可以安装于电路基板62上。半导体管芯24的侧面处的凹口34与导电区64上的焊料凸起66接触。拾放过程可用于在电路基板62上安装半导体管芯24。安装后，可以执行回流处理以使得焊料66回流。如图4(d)和4(e)所示，回流的焊料凸起形成焊点68，它至少部分存在于凹口34中。这些焊点68可以用作到半导体管芯24的背侧的漏极连接。
在安装前，在该实例中，半导体管芯24在其上没有焊料凸起。因此，在该实例中，在安装前，半导体管芯24可以被认为是安装到电路基板62上的“无凸起”管芯。与具有凸起管芯相比，这使得焊接更方便。当然，在其它实施例中，管芯可以用焊料形成凸起。
图4(f)-4(h)示出在被安装到电路基板62上时半导体管芯24的近示图。电路基板62包括许多含焊料凸起66(a)、66(b)导电区64(a)、64(b)。焊料凸起66(a)耦合到半导体管芯24上的焊料凸起32。焊料凸起66(b)耦合到半导体管芯24的侧边处的凹口34。如图4(h)所示，回流后，形成焊点68，其顶部与凹口34的壁接触。焊点68的基部位于导电区64(b)上，该导电区可以是印刷电路板(PCB)的金属轨迹。
可以理解，为了在图4(f)-4(h)和其它附图中说明，简化了半导体管芯24和其它元件的描述。可以理解，本技术领域内的普通技术人员可以提供半导体管芯24中合适的边缘端接结构，以便使得焊料凸起32和焊点68电绝缘。例如，感光BCB(苯基环丁烷)或聚酰亚胺可用于涂覆管芯的边缘或下面以使得焊料凸起32和焊点68电绝缘。
图5(a)和5(b)示出在用较大的焊点形成时的半导体管芯封装。以图4(a)-4(c)所示的方式在电路基板上安装管芯。随后，如图5(a)所示，在将半导体管芯24安装在电路基板62上后，附加的焊料86可以沉积在凹口34上。图5(b)示出回流后的半导体管芯封装。回流后，形成更大的焊点86。这些焊点86将凹口耦合到电路基板62的导电区。
如图5(c)所示，以前述方式处理的焊料凸起的半导体管芯24被安装在具有导电区64(a)、64(b)的电路基板62上。导电区64(a)、64(b)具有其上的焊料凸起66(a)、66(b)。如图5(d)所示，半导体管芯24上的焊料凸起32与导电区64(a)上的焊料凸起66(a)接触。焊料凸起66(b)与半导体管芯24的边缘处的凹口34接触。随后，将附加焊料88沉积到焊料凸起66(b)上以提供到背侧金属30和到半导体管芯24中MOSFET中的漏极区的更好的电气连接。如图5(e)所示，回流后，焊料66(b)、88形成焊点86。
在图5(c)-5(e)所示的实施例中，第二焊料糊印刷或分配步骤将允许到凹口34中金属的更多漏极接触，它连接到半导体管芯24中MOSFET中的漏极。这导致回流后更高、更宽的焊点。
以与图5(c)-5(e)中的半导体管芯24类似的方式安装图6(a)和6(b)中半导体管芯24。但是，在图6(a)和6(b)中，散热片48和焊料层46在半导体管芯24上。
图6(c)中示出半导体管芯24的边角的放大示图。如这里所示的，绝缘层92存在于半导体管芯24的前侧。绝缘层92可以包括诸如苯基环丁烷(BCB)的材料。绝缘层92可以具有约8到约10微米之间的厚度。其覆盖可以延伸到半导体晶片中的划线并将在回流后与焊点接触。该绝缘确保到硅边缘的触点断开，它可以是影响焊点可靠性的应力点。图6(d)中示出半导体管芯24的平面顶视图。
这里采用的术语和表达用作描述的术语而非限制，并非旨在使用所示和所述特点的排除等效物的这些术语和表达，或者其部分，可以理解，各种修改也可能在所要求的本发明的范围内。此外，本发明的一个或多个实施例的一个或多个特点可以与本发明的其它实施例的一个或多个特点组合而不背离本发明的范围。

Claims (16)

1.一种方法，其特征在于，包括：
(a)形成包括由划线限定的多个半导体管芯的半导体晶片；
(b)在划线附近在半导体晶片中形成多个空腔；以及
(c)沿所述划线切割晶片以分开半导体管芯，其中每个被分开的半导体管芯包括垂直晶体管并包括半导体管芯的边缘处的至少一个凹口。
2.如权利要求1所述的方法，其特征在于，所述多个空腔中的每个空腔都部分延伸穿过半导体晶片。
3.如权利要求1所述的方法，其特征在于，使用蚀刻工艺形成所述多个空腔。
4.如权利要求1所述的方法，其特征在于，进一步包括：
(d)将被分开的管芯贴附到电路基板上，其中对于每个半导体管芯，焊接材料通过所述半导体管芯边缘处的至少一个凹口将所述半导体管芯耦合到电路基板中的一个。
5.如权利要求1所述的方法，其特征在于，每个被分开的半导体管芯都包括半导体管芯的每一侧上的至少一个凹口。
6.如权利要求1所述的方法，其特征在于，多个空腔中的每一个都延伸通过半导体晶片。
7.如权利要求1所述的方法，其特征在于，半导体晶片包括前侧和背侧，其中多个空腔中的每一个都形成于半导体晶片的背侧。
8.如权利要求1所述的方法，其特征在于，进一步包括将散热片贴附到每个被分开的半导体管芯上。
9.如权利要求1所述的方法，其特征在于，进一步包括：
d)将至少一个被分开的管芯贴附到电路基板上，其中至少一个半导体管芯具有多个可焊接区而不是焊料凸起，且其中电路基板具有接合区盘。
10.一种半导体管芯封装，其特征在于，包括：
(a)包括导电区的电路基板；
(b)所述电路基板上包括垂直晶体管的半导体管芯，其中该半导体管芯包括边缘和边缘处的凹口；以及
(c)通过凹口将半导体管芯和导电区耦合的焊点。
11.如权利要求10所述的半导体管芯封装，其特征在于，半导体管芯包括垂直MOSFET。
12.如权利要求10所述的半导体管芯封装，其特征在于，凹口部分延伸穿过半导体管芯。
13.如权利要求10所述的半导体管芯封装，其特征在于，半导体管芯包括背侧，其中该背侧被金属化。
14.如权利要求10所述的半导体管芯封装，其特征在于，半导体管芯包括背侧，其中将散热片贴附到该背侧上。
15.如权利要求10所述的半导体管芯封装，其特征在于，凹口是半圆锥的形式。
16.如权利要求10所述的半导体管芯封装，其特征在于，所述边缘是半导体管芯的第一边缘，其中半导体管芯包括在半导体管芯的第二边缘处的第二凹口。
CNB038065819A 2002-01-22 2003-01-21 含侧向电气连接的半导体管芯的半导体管芯封装 Expired - Fee Related CN100409443C (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US35158702P 2002-01-22 2002-01-22
US60/351,587 2002-01-22
US10/346,682 US6830959B2 (en) 2002-01-22 2003-01-17 Semiconductor die package with semiconductor die having side electrical connection
US10/346,682 2003-01-17

Publications (2)

Publication Number Publication Date
CN1643691A true CN1643691A (zh) 2005-07-20
CN100409443C CN100409443C (zh) 2008-08-06

Family

ID=26994967

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB038065819A Expired - Fee Related CN100409443C (zh) 2002-01-22 2003-01-21 含侧向电气连接的半导体管芯的半导体管芯封装

Country Status (6)

Country Link
US (1) US6830959B2 (zh)
JP (1) JP2005516402A (zh)
CN (1) CN100409443C (zh)
AU (1) AU2003210637A1 (zh)
DE (1) DE10392228T5 (zh)
WO (1) WO2003063248A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102938383A (zh) * 2008-06-30 2013-02-20 万国半导体股份有限公司 标准芯片尺寸封装
WO2020220643A1 (zh) * 2019-04-30 2020-11-05 华南理工大学 一种具有毛细微槽结构的去金属化陶瓷基板及其焊接方法

Families Citing this family (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3813079B2 (ja) * 2001-10-11 2006-08-23 沖電気工業株式会社 チップサイズパッケージ
US7122884B2 (en) * 2002-04-16 2006-10-17 Fairchild Semiconductor Corporation Robust leaded molded packages and methods for forming the same
US6861337B2 (en) * 2002-05-10 2005-03-01 General Semiconductor, Inc. Method for using a surface geometry for a MOS-gated device in the manufacture of dice having different sizes
JP3972813B2 (ja) * 2002-12-24 2007-09-05 セイコーエプソン株式会社 半導体装置の製造方法
DE10334634B3 (de) * 2003-07-29 2005-01-13 Infineon Technologies Ag Verfahren zum seitlichen Kontaktieren eines Halbleiterchips
US7690551B2 (en) * 2003-12-31 2010-04-06 Chippac, Inc. Die attach by temperature gradient lead free soft solder metal sheet or film
US7196313B2 (en) * 2004-04-02 2007-03-27 Fairchild Semiconductor Corporation Surface mount multi-channel optocoupler
US7524701B2 (en) * 2005-04-20 2009-04-28 International Rectifier Corporation Chip-scale package
US20060258051A1 (en) * 2005-05-10 2006-11-16 Texas Instruments Incorporated Method and system for solder die attach
CN101213663B (zh) * 2005-06-30 2010-05-19 费查尔德半导体有限公司 半导体管芯封装及其制作方法
US7838977B2 (en) * 2005-09-07 2010-11-23 Alpha & Omega Semiconductor, Ltd. Packages for electronic devices implemented with laminated board with a top and a bottom patterned metal layers
US7285849B2 (en) * 2005-11-18 2007-10-23 Fairchild Semiconductor Corporation Semiconductor die package using leadframe and clip and method of manufacturing
US20090057852A1 (en) * 2007-08-27 2009-03-05 Madrid Ruben P Thermally enhanced thin semiconductor package
US7371616B2 (en) * 2006-01-05 2008-05-13 Fairchild Semiconductor Corporation Clipless and wireless semiconductor die package and method for making the same
US20070164428A1 (en) * 2006-01-18 2007-07-19 Alan Elbanhawy High power module with open frame package
US7868432B2 (en) * 2006-02-13 2011-01-11 Fairchild Semiconductor Corporation Multi-chip module for battery power control
US7768075B2 (en) 2006-04-06 2010-08-03 Fairchild Semiconductor Corporation Semiconductor die packages using thin dies and metal substrates
US7618896B2 (en) * 2006-04-24 2009-11-17 Fairchild Semiconductor Corporation Semiconductor die package including multiple dies and a common node structure
US7656024B2 (en) 2006-06-30 2010-02-02 Fairchild Semiconductor Corporation Chip module for complete power train
US8293584B2 (en) * 2006-08-04 2012-10-23 Stats Chippac Ltd. Integrated circuit package system with filled wafer recess
US7564124B2 (en) * 2006-08-29 2009-07-21 Fairchild Semiconductor Corporation Semiconductor die package including stacked dice and heat sink structures
US8106501B2 (en) 2008-12-12 2012-01-31 Fairchild Semiconductor Corporation Semiconductor die package including low stress configuration
US7768105B2 (en) 2007-01-24 2010-08-03 Fairchild Semiconductor Corporation Pre-molded clip structure
US7821116B2 (en) * 2007-02-05 2010-10-26 Fairchild Semiconductor Corporation Semiconductor die package including leadframe with die attach pad with folded edge
KR101391925B1 (ko) * 2007-02-28 2014-05-07 페어차일드코리아반도체 주식회사 반도체 패키지 및 이를 제조하기 위한 반도체 패키지 금형
KR101489325B1 (ko) 2007-03-12 2015-02-06 페어차일드코리아반도체 주식회사 플립-칩 방식의 적층형 파워 모듈 및 그 파워 모듈의제조방법
US7659531B2 (en) * 2007-04-13 2010-02-09 Fairchild Semiconductor Corporation Optical coupler package
US7683463B2 (en) * 2007-04-19 2010-03-23 Fairchild Semiconductor Corporation Etched leadframe structure including recesses
US7902657B2 (en) 2007-08-28 2011-03-08 Fairchild Semiconductor Corporation Self locking and aligning clip structure for semiconductor die package
US7737548B2 (en) 2007-08-29 2010-06-15 Fairchild Semiconductor Corporation Semiconductor die package including heat sinks
US20090057855A1 (en) * 2007-08-30 2009-03-05 Maria Clemens Quinones Semiconductor die package including stand off structures
US20090115026A1 (en) * 2007-11-05 2009-05-07 Texas Instruments Incorporated Semiconductor device having through-silicon vias for high current,high frequency, and heat dissipation
US7589338B2 (en) * 2007-11-30 2009-09-15 Fairchild Semiconductor Corporation Semiconductor die packages suitable for optoelectronic applications having clip attach structures for angled mounting of dice
US20090140266A1 (en) * 2007-11-30 2009-06-04 Yong Liu Package including oriented devices
KR20090062612A (ko) * 2007-12-13 2009-06-17 페어차일드코리아반도체 주식회사 멀티 칩 패키지
US7781872B2 (en) * 2007-12-19 2010-08-24 Fairchild Semiconductor Corporation Package with multiple dies
US7791084B2 (en) 2008-01-09 2010-09-07 Fairchild Semiconductor Corporation Package with overlapping devices
US8106406B2 (en) * 2008-01-09 2012-01-31 Fairchild Semiconductor Corporation Die package including substrate with molded device
US7626249B2 (en) * 2008-01-10 2009-12-01 Fairchild Semiconductor Corporation Flex clip connector for semiconductor device
US20090194857A1 (en) * 2008-02-01 2009-08-06 Yong Liu Thin Compact Semiconductor Die Packages Suitable for Smart-Power Modules, Methods of Making the Same, and Systems Using the Same
KR101524545B1 (ko) * 2008-02-28 2015-06-01 페어차일드코리아반도체 주식회사 전력 소자 패키지 및 그 제조 방법
US8018054B2 (en) * 2008-03-12 2011-09-13 Fairchild Semiconductor Corporation Semiconductor die package including multiple semiconductor dice
US7768108B2 (en) 2008-03-12 2010-08-03 Fairchild Semiconductor Corporation Semiconductor die package including embedded flip chip
KR101519062B1 (ko) * 2008-03-31 2015-05-11 페어차일드코리아반도체 주식회사 반도체 소자 패키지
US20090278241A1 (en) * 2008-05-08 2009-11-12 Yong Liu Semiconductor die package including die stacked on premolded substrate including die
US8193618B2 (en) 2008-12-12 2012-06-05 Fairchild Semiconductor Corporation Semiconductor die package with clip interconnection
US7973393B2 (en) 2009-02-04 2011-07-05 Fairchild Semiconductor Corporation Stacked micro optocouplers and methods of making the same
US8222718B2 (en) * 2009-02-05 2012-07-17 Fairchild Semiconductor Corporation Semiconductor die package and method for making the same
US20120080749A1 (en) * 2010-09-30 2012-04-05 Purtell Robert J Umos semiconductor devices formed by low temperature processing
US9402319B2 (en) 2011-05-11 2016-07-26 Vlt, Inc. Panel-molded electronic assemblies
US8966747B2 (en) 2011-05-11 2015-03-03 Vlt, Inc. Method of forming an electrical contact
US8421204B2 (en) 2011-05-18 2013-04-16 Fairchild Semiconductor Corporation Embedded semiconductor power modules and packages
US9105533B2 (en) * 2011-07-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure having a single side recess
US10833033B2 (en) 2011-07-27 2020-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Bump structure having a side recess and semiconductor structure including the same
JP5995596B2 (ja) * 2012-08-06 2016-09-21 株式会社ディスコ ウエーハの加工方法
JP5995597B2 (ja) * 2012-08-06 2016-09-21 株式会社ディスコ ウエーハの加工方法
CN106663673A (zh) 2013-08-28 2017-05-10 坤佰康有限责任公司 半导体晶片和封装拼板式基台
US9967984B1 (en) 2015-01-14 2018-05-08 Vlt, Inc. Power adapter packaging
US9936580B1 (en) 2015-01-14 2018-04-03 Vlt, Inc. Method of forming an electrical connection to an electronic module
US10264664B1 (en) 2015-06-04 2019-04-16 Vlt, Inc. Method of electrically interconnecting circuit assemblies
JP2019004117A (ja) * 2017-06-19 2019-01-10 力祥半導體股▲フン▼有限公司ＵＢＩＱ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｃｏｒｐ． 半導体装置および電力変換回路

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1047652A (en) * 1975-07-31 1979-01-30 National Semiconductor Corporation Monolithic integrated circuit transistor having very low collector resistance
US4717641A (en) * 1986-01-16 1988-01-05 Motorola Inc. Method for passivating a semiconductor junction
US5016080A (en) * 1988-10-07 1991-05-14 Exar Corporation Programmable die size continuous array
JPH04276645A (ja) * 1991-03-04 1992-10-01 Toshiba Corp 化合物半導体ウエーハのダイシング方法
JPH05206314A (ja) * 1991-11-12 1993-08-13 Nec Corp 半導体装置
US5455385A (en) * 1993-06-28 1995-10-03 Harris Corporation Multilayer LTCC tub architecture for hermetically sealing semiconductor die, external electrical access for which is provided by way of sidewall recesses
JP2755131B2 (ja) * 1993-10-27 1998-05-20 日本電気株式会社 半導体装置
US6028348A (en) * 1993-11-30 2000-02-22 Texas Instruments Incorporated Low thermal impedance integrated circuit
DE4415374A1 (de) * 1994-05-02 1995-11-09 Trw Repa Gmbh Gassack-Modul
DE19580604T1 (de) * 1994-06-09 1997-05-07 Chipscale Inc Widerstandsfabrikation
US5786280A (en) * 1994-06-23 1998-07-28 Eduard Kusters Maschinenfabrik Gmbh & Co. Kg Molded part and method of its production
US5767578A (en) * 1994-10-12 1998-06-16 Siliconix Incorporated Surface mount and flip chip technology with diamond film passivation for total integated circuit isolation
JP3496347B2 (ja) * 1995-07-13 2004-02-09 株式会社デンソー 半導体装置及びその製造方法
US5785280A (en) * 1995-07-20 1998-07-28 Space Systems/Loral, Inc. Hybrid solar panel array
US5637916A (en) * 1996-02-02 1997-06-10 National Semiconductor Corporation Carrier based IC packaging arrangement
US5861667A (en) * 1997-03-11 1999-01-19 Texas Instruments Incorporated Single end in out arrangement
JPH10284935A (ja) * 1997-04-09 1998-10-23 Murata Mfg Co Ltd 電圧制御発振器およびその製造方法
TW480713B (en) * 1998-03-03 2002-03-21 Mosel Vitelic Inc Method for forming different thickness of field oxide in integrated circuit and the structure of the same
AUPP328398A0 (en) * 1998-04-30 1998-05-21 De Boer, Barry R. Remove-a-line
US6423623B1 (en) * 1998-06-09 2002-07-23 Fairchild Semiconductor Corporation Low Resistance package for semiconductor devices
KR100338983B1 (ko) * 1998-11-30 2002-07-18 윤종용 웨이퍼분리도구및이를이용하는웨이퍼분리방법
US6560382B1 (en) * 1999-02-18 2003-05-06 The United States Of America As Represented By The Secretary Of The Navy System for alternately directing optical energy through multiple optical modulation channels
JP2000243900A (ja) * 1999-02-23 2000-09-08 Rohm Co Ltd 半導体チップおよびそれを用いた半導体装置、ならびに半導体チップの製造方法
US6309943B1 (en) * 2000-04-25 2001-10-30 Amkor Technology, Inc. Precision marking and singulation method
US6580150B1 (en) * 2000-11-13 2003-06-17 Vram Technologies, Llc Vertical junction field effect semiconductor diodes
KR20010044277A (ko) * 2001-01-31 2001-06-05 김영선 방열지붕이 몰딩된 플라스틱 패캐지(피피엠시)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102938383A (zh) * 2008-06-30 2013-02-20 万国半导体股份有限公司 标准芯片尺寸封装
CN102938383B (zh) * 2008-06-30 2015-12-16 万国半导体股份有限公司 标准芯片尺寸封装
WO2020220643A1 (zh) * 2019-04-30 2020-11-05 华南理工大学 一种具有毛细微槽结构的去金属化陶瓷基板及其焊接方法

Also Published As

Publication number Publication date
JP2005516402A (ja) 2005-06-02
WO2003063248A1 (en) 2003-07-31
DE10392228T5 (de) 2005-02-24
US20030139020A1 (en) 2003-07-24
AU2003210637A1 (en) 2003-09-02
CN100409443C (zh) 2008-08-06
US6830959B2 (en) 2004-12-14
WO2003063248A8 (en) 2005-02-03

Similar Documents

Publication Publication Date Title
CN1643691A (zh) 含侧向电气连接的半导体管芯的半导体管芯封装
CN1311548C (zh) 具有改进的散热能力的半导体器件封装
US7256479B2 (en) Method to manufacture a universal footprint for a package with exposed chip
CN102308383B (zh) 半导体管芯封装件及其制造方法
US6350633B1 (en) Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint
JP4729244B2 (ja) 半導体デバイス用非モールドパッケージ
CN101807533B (zh) 半导体管芯封装及其制作方法
US6562709B1 (en) Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint
US8324739B2 (en) Semiconductor device
WO2015157845A1 (en) Embedded packaging for devices and systems comprising lateral gan power transistors
US20090194856A1 (en) Molded package assembly
JP2005506691A5 (zh)
KR20170086828A (ko) 메탈범프를 이용한 클립 본딩 반도체 칩 패키지
US6403460B1 (en) Method of making a semiconductor chip assembly
CN1213487C (zh) 半导体组件及其制造方法
US20210249334A1 (en) Semiconductor device including an embedded semiconductor die and a method for fabricating the same
US7632712B2 (en) Method of fabricating a power semiconductor module
US7088004B2 (en) Flip-chip device having conductive connectors
CN1282241C (zh) 半导体装置
US20230411250A1 (en) Power converter and power converter manufacturing method
TW586169B (en) Semiconductor die package with semiconductor die having side electrical connection
US20230352378A1 (en) Semiconductor package and method for fabricating the same
JP2019140334A (ja) 半導体装置および半導体装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080806

Termination date: 20170121