CN1645599A - 电子元件的封装结构及其制造方法 - Google Patents

电子元件的封装结构及其制造方法 Download PDF

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CN1645599A
CN1645599A CNA2004100686987A CN200410068698A CN1645599A CN 1645599 A CN1645599 A CN 1645599A CN A2004100686987 A CNA2004100686987 A CN A2004100686987A CN 200410068698 A CN200410068698 A CN 200410068698A CN 1645599 A CN1645599 A CN 1645599A
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electronic building
building brick
resilient coating
substrate
encapsulating structure
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CN1300843C (zh
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黄钰同
吴志雄
徐永政
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TAI SAW TECHNOLOGY Co
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TAI SAW TECHNOLOGY Co
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Abstract

本发明在基板上先形成一缓冲层，再将电子组件封装于其上，可避免公知技术中气密性不佳或制程繁杂等问题，因此本发明可提供较佳的气密性及较简单的制程步骤的封装结构与方法。尤其在进行封装时，缓冲可以改善覆晶的平坦度，并减少封装过程的负作用。

Description

电子元件的封装结构及其制造方法
技术领域
本发明是有关于具有缓冲层的电子组件结构及制造方法，特别是利用缓冲层来改善覆晶的平坦度及减少封装过程的负作用的封装结构与方法。
背景技术
传统的封装技术是采用导线架封装方式，需要导线架(Leadframe)或是基板(Substrate)、黏芯片(Die Attach)、打线、灌膜(Molding)、成型(Trim and Form)等制程，封装后的集成电路(Integrated Circuit，IC)大小是芯片(Chip)的好几倍。但随着讯号输出脚数快速增加，再加上电子组件的技术趋势朝着轻薄短小发展，传统的导线架封装方式已不符合所需。各种新封装技术如卷带式自动接着封装(Tape AutomatedBonding，TAB)、球栅数组封装(Ball Grid Array，BGA)以及覆晶封装(Flip Chip)等技术相继被推出，以改善或弥补传统封装技术的不足之处。
在上述中的覆晶封装技术是一种将芯片与基板相互连接的先进封装技术。在封装过程中，芯片会被翻覆过来，让芯片上面的接合点(Pad)与基板的接合点相互连接。而一般覆晶技术所使用的基板包括了有陶瓷、硅芯片、高分子积层板以及玻璃等，而其应用的范围也相当广泛，包括计算机、PCMCIA卡、军事设备、个人通讯产品、钟表、液晶显示器以及表面声波组件等这些领域。
使用覆晶封装技术主要有两大好处，第一：可降低芯片与基板间的电子讯号传输距离，因此适合应用于高速组件的封装；第二：可缩小芯片封装后的尺寸，使得芯片封装前后大小差不多，适合需要较小封装面积的集成电路组件。
覆晶技术虽然有不少的优点，但相对地带来了一些先天上的缺点或限制，例如：需要高装配精度、填充材料的固化时间、对某些基板的可靠度较低等。不少致力于覆晶技术的人为了解决及改善这些先天上缺点或限制，也发展出不同的覆晶技术以求克服这些先天缺点或限制，一些不同的覆晶技术将于下面做简短的描述与说明。
在美国专利号码6310421及美国专利申请号20030009864中公开了一种气隙(air gap)封装技术。如图1A所示，为美国专利号码6310421所公开的封装结构。气隙(air gap)封装技术为在电子组件110的主动区域105上形成由气隙层115及116所为成的气隙117；然后在覆晶于基板120之上。气隙封装技术所形成的结构的气密性相当好，但其需要至少两道的光罩制程，故其制程较为复杂，而且其形成的封装结构的高度也较高。
薄膜封装技术，如美国专利号码6,492,194、WO 99/43084或WO03/012856，所公开的技术，是利用于薄膜形成于电子组件与基板上方，并施压使薄膜紧贴于电子组件与基板。如图1B所示，为WO 03/012856所揭露的结构图，薄膜240紧贴于电子组件210及基板220之上。但是这样的结构的气密性不佳，尤其当薄膜240时被施压并形成时，于电子组件210侧边的部分薄膜270会因拉力而变薄，如图1C所示，造成气体可能容易穿透薄膜240，再者，其部分薄膜270与基板的接触点附近的空隙形状类似乳滴管，在制程中会经过多次升、降温的过程，造成水气等入侵，而使组件特性改变或组件受损。因此须于薄膜240上再形成另一层薄膜260，以加强气密效果，使得封装结构的制程上较为复杂。
在美国专利号码6078229所公开的封装方法是具有树酯薄膜330的封装结构与方法，如图1D所示。其优点是不需形成金属层，因此其重量及成本较低。但是由于树酯薄膜330必须有数个开口，使其不覆盖表面声波组件314的振动腔317及凸块316(Bump)，因此其制程上所要求的精确度较高及较为复杂。
另一种封装技术为底部密封(underfill)的封装技术。图1E为美国专利号码5969461中所公开的底部密封封装技术的结构。注入具有流动性的树酯440后到树酯440固化这段时间，树酯440会流入电子组件410及基板420之间，故需增加屏障(dam)480以防止树酯440碰触到电子组件410的主动区域而影响电子组件(如：表面声波组件)的特性受到影响。且对多余的树酯需再加以清除，因此，整体的制程上较为复杂，其制程成本也会较高。
在美国专利号码6262513公开了封装树脂封合(encapsulation resin)的封装方式，如图1F所示，在电子组件510及基板520的上覆盖一层树脂540。这树脂层540必须无流动性树脂，以避免如底部密封的技术所使用的树酯，会流进电子组件510与基板520间的空隙，使电子组件的特性受到影响。但是树脂层540在加热固化过程有热膨胀的问题，为了减少因热膨胀系数而产生的热应力，可以在树脂层540中添加SiO2颗粒，但会造成与线路590间的连接力下降，而使之封装结构的气密性不佳。
发明内容
鉴于上述发明背景中，公知技术中覆晶技术方法会遭遇到制程方法复杂度高或者封装气密气不佳的问题。本发明的主要目的在于利用形成缓冲层于电子组件及基板之间，以达到良好的气密性。而且这样的结构的制程也相当的简单。
本发明的另一目的为，利用于电子组件及基板之间的缓冲层，可以有效改善电子组件及基板间的平坦度。
本发明的又一目的为，利用封装过程挤压缓冲层，使缓冲层更密及延展，使空气不论是经缓冲层与电子组件的连接面或穿透缓冲层的逸出路径都变长及困难，因此可提供一良好气密性的结构，使水气、氧气及二氧化碳等气体不易侵蚀此结构。
根据上述目的，本发明提供了一种电子组件的封装结构，包含：
一基板，该基板的一第一表面具有一第一复数个接触点及一第二复数个接触点、一第二表面具有复数个接合点，且该基板具有复数个介层洞，用以连接该第一复数个接触点及该复数个接合点；以及
一缓冲层，位于该基板与该电子组件之间，而该电子组件的具有电极的一表面与该基板的该第一表面相对，该缓冲层上有一开口，使该第一表面的该第一复数个接触点露出，其中该缓冲层围绕于该电子组件的周边，且该电子组件周边与该缓冲层的一接触面为非平面。
其中该基板材质选自于由铝、陶瓷、硅芯片、高分子积层板及玻璃所组成的族群。
其中上述缓冲层选自于由有机薄膜层及聚合物薄膜层所组成的族群。
其中上述缓冲层的材质具有导电性。
其中上述缓冲层的该开口经微影制程、激光或预先开口方式所形成。
还包含一导电层，该导电层形成于该电子组件上。
其中上述缓冲层的厚度为30-200微米。
上述电子组件与该缓冲层该接触面具有一折角。
其中上述电子组件与该基板经一选自于由热压接合、超声波接合、热超声波接合、点焊接合或灌封接合所组成的族群的贴合制程来贴合。
本发明还提供了一种电子组件的封装方法，包含：
形成一缓冲层于一基板的一第一表面，该缓冲层上有一第一开口，使该基板的该第一表面的一第一复数个接触点露出，其中该基板的该第一表面具有该第一复数个接触点及一第二复数个接触点、一第二表面具有复数个接合点，且该基板具有复数个介层洞，用以连接该第一复数个接触点及该复数个接合点；以及
安装一第一电子组件于该缓冲层上，使该第一电子组件对应该缓冲层上的该第一开口，其中该复数个电极具有电极的一表面与该基板的该第一表面相对，该缓冲层围绕该第一电子组件的周边，且该电子组件周边与该缓冲层的一接触面为非平面。
相较于公知技术的缺点，本发明是利用形成缓冲层于电子组件及基板之间来克服公知技术的缺点。缓冲层除可以作为一自我平坦化缓冲层，改善电子组件与基板之间的平坦度。而且增加了气体逸出的路径长度及困难度，使结构的气密性更良好，更能有效防止水气、氧气及二氧化碳等气体的侵蚀。而且，此结构的制程十分简单，有助于改善产品的良率。
附图说明
图1A-F为公知技术中的电子组件封装技术的示意图；
图2A-C为本发明的一较佳实施例的制程步骤的示意图；
图3A-E为本发明的晶圆等级组件的制程步骤的示意图；以及
图4为为本发明的另一较佳实施例的结构示意图。
具体实施方法
本发明的一些实施例会详细描述如下。然而，除了详细描述外，本发明还可以广泛地在其它的实施例施行，且本发明的范围不受限定，其以申请的专利范围为准。
再者，为提供更清楚的描述及更易理解本发明，附图内各部分并没有依照其相对尺寸绘图，某些尺寸与其它相关尺度相比已经被夸张；不相关的细节部分也未完全绘出，以求附图的简洁。
由于目前的覆晶技术方法会遭遇到制程方法复杂度高或者封装气密气不佳的问题。本发明针对此而提供了一种封装于缓冲层上的电子组件的结构。本发明的覆晶的结构与方法除在其制程十分容易外，也能达到提升封装的气密性的作用。再者，覆晶的技术是将芯片翻覆过来，使芯片上面的接触点与基板的接触点相互连接的技术，其平坦度(芯片是否与基板平行)是直接影响到覆晶的良率(尤其是金对金的覆晶)，接触点数目越多，对平坦度的要求越严格。因此，由缓冲层，可以达到封装过程自我平坦化(Self-Planarization)的作用，改善覆晶平坦度的问题。本发明上述的优点将于下面做详细地描述与说明。
本发明的一较佳实施例的封装结构的制程步骤如图2A到图2C所示。在图2A中，基板20第一表面具有第一复数个接触点11及第二复数个接触点40，第二表面具有复数个接合点21，第一复数个接触点11与复数个接合点21透过介层洞(Via holes)31来彼此连接。然后形成一缓冲层30于基板20之上，并移除第二复数个接触点40之上以外部分的缓冲层30，形成复数个开口90，如图2B所示。此移除部分缓冲层30的步骤可以是经微影制程或激光开口来达成，或者在缓冲层30上先预先开口然后形成于基板20上。而缓冲层较佳的厚度范围为30-200微米。然后，将每个电子组件10对应着一个开口90置于缓冲层30上，使缓冲层30支撑着电子组件10的周边，如图2C所示。最后，执行贴合制程，使电子组件10可以与基板20紧密连接在一起。
在此再对经上述封装制程所形成的封装结构，做详细的描述：基板20上有第一复数个接触点11、第二复数个接触点40、复数个接合点21及复数个介层洞31。其中第一复数个接触点11及第二复数个接触点40位于基板20的第一表面；复数个接合点21位于基板的第二表面，且第一复数个接触点11及复数个接合点21由复数个介层洞31来连接。缓冲层30上有复数个开口90，使第一复数个接触点11露出。因此，当电子组件10置于缓冲层30上时，每个电子组件10对应缓冲层的一开口90，且电子组件10周边与缓冲层30接触。
一般而言，在电子组件10、基板20、缓冲层30及第二复数个接触点40之间的气体若要逸出，主要从电子组件10及缓冲层30的接触面或穿过缓冲层30逸出。而在本发明中，缓冲层30经挤压后会变的密实及沿着电子组件10及基板20间的空间延展。所以，气体逸出所需穿透缓冲层30的厚度增加。再者电子组件10及缓冲层30的接触面经挤压后也变成为非平面，其距离长度较长而且带有一转角。因此与公知技术相比，本发明结构的气密性十分良好。再者，电子组件10上与缓冲层30的接触表面也可以是非平面，而是具有高低起伏的表面(例如锯齿状的表面)，如此，也可以增加气体的逃逸距离，而达到增加气密度的效果。
电子组件10与缓冲层30的贴合制程，可结合传统技术上的贴合制程，例如：热压接合、超声波接合、热超声波接合、点焊接合或灌封接合等，来使电子组件10与缓冲层30紧密贴合。在贴合过程，可施力60于电子组件10上，在这过程，缓冲层30在与电子组件10的接合部分会因挤压而使结构更密实，增加对水气、氧气或二氧化碳等会侵蚀或影响组件可靠性的气体抗渗透性。再者，在挤压过程，缓冲层30会沿着电子组件10与基板20的空隙延展，而增加气体的逃逸路径，使气体更不易穿透缓冲层30。另一个气体可逃逸的路经为缓冲层30与电子组件10的接触面，这接触面会因挤压过程而形成具有弯角的非平面，且气体的逃逸路经长度也因挤压而增长，因此，气体也不易由接触面逃逸。所以，本发明的结构的气密性明显比公知技术的结构好。另外，贴合过程可以在真空中、或者特定的气体或混合气体环境下进行，例如：氮气、氢气、氦气等惰性气体或其混合气体。特定的气体或混合气体不可包含如水气、氧气或二氧化碳等会侵蚀或影响组件可靠性的气体，使封装组件完成的内部气体并不会影响封装组件。
电子组件10、基板20之间的缓冲层30的另一个优点为，可以改善贴合制程时，电子组件10、基板20之间的平坦度。尤其当贴合制程为超声波接合或热超声波接合时，缓冲层30可以有效吸收传至电子组件10周围的超音波能量，但传至中间导体16的超音波能量不受缓冲层30所影响而损失，故改善其平坦度的效果尤其明显，特别是对金的封装而言，平坦度一直是最大的问题。本发明利用缓冲层30介于电子组件10之间基板20之间，而达到自我平坦化的功能，因此克服可公知技术中的平坦度问题。
本发明并不限制可应用的电子组件的种类，例如：射频组件、感应器、可抹除且可程序只读存储器、电荷耦合组件、半导体激光、发光二极管及表面声波组件等均可应用于本发明的封装结构及方法。而本发明可使用的基板的材质种类也相当的多，例如：铝、高温共烧陶瓷(HTCC)、低温共烧陶瓷(LTCC)等，而硅芯片、高分子积层板或玻璃等一般传统使用的基板也适用于本发明。虽然在挤压过程，缓冲层30变的密实，可以使缓冲层30变的更不易吸水气或氧气、二氧化碳不易渗透，但缓冲层30的材质若选择性质较不易吸收水气，或者氧气、二氧化碳不易渗透的材质，例如：PET、PEN、PVC、OPP、PI等有机物或聚合物，可以更加强封装组件的可靠性。而且缓冲层也可以为具有导电性的材质，以加强接地的效果。
本发明也适用于晶圆等级的制程，如图3A到图3E所示。在图3A中，基板20第一表面具有一第一复数个接触点11及一第二复数个接触点40，第二表面具有复数个接合点21，第一复数个接触点11与复数个接合点21透过介层洞31来彼此连接。然后形成一缓冲层30于基板20的上，并移除第二复数个接触点40的上以外部分的缓冲层30，形成复数个开口90，如图3B所示。再来，如图3C，将晶圆等级的复数个电子组件10置于缓冲层30的上。如图3D所示，缓冲层30支撑着各个电子组件10的周边。也可以执行一切割制程，使各个电子组件10可以彼此分割出来，如图3E。当然，切割制程也可以是半切割的方式，以便配合后续制程的需求。
如图4所示为本发明的另一实施例的结构示意图。相较于上述的结构，此实施例的结构多形成一导电层50于电子组件10、缓冲层30及第二复数个接触点40上。而此导电层50可达到电磁波屏蔽及增加气密性的作用。
因此，相较于公知技术的上述缺点，本发明利用形成缓冲层于电子组件及基板之间，缓冲层除可以作为一自我平坦化缓冲层，改善电子组件与基板之间的平坦度。而且增加了气体逸出的路径长度及困难度，使结构的气密性更良好，更能有效防止水气、氧气及二氧化碳等的侵蚀。而且，此结构的制程十分简单，有助于改善产品的良率。
以上所述仅为本发明的较佳实施例而已，并非用以限定本发明的申请专利范围；凡其它为脱离本发明所揭示的精神下所完成的等效改变或修饰，均应包含在申请的专利范围。

Claims (10)

1.一种电子组件的封装结构，包含：
一基板，该基板的一第一表面具有一第一复数个接触点及一第二复数个接触点、一第二表面具有复数个接合点，且该基板具有复数个介层洞，用以连接该第一复数个接触点及该复数个接合点；以及
一缓冲层，位于该基板与该电子组件之间，而该电子组件的具有电极的一表面与该基板的该第一表面相对，该缓冲层上有一开口，使该第一表面的该第一复数个接触点露出，其中该缓冲层围绕于该电子组件的周边，且该电子组件周边与该缓冲层的一接触面为非平面。
2.如权利要求1的电子组件的封装结构，其特征在于，其中该基板材质选自于由铝、陶瓷、硅芯片、高分子积层板及玻璃所组成的族群。
3.如权利要求1的电子组件的封装结构，其特征在于，其中上述缓冲层选自于由有机薄膜层及聚合物薄膜层所组成的族群。
4.如权利要求1的电子组件的封装结构，其特征在于，其中上述缓冲层的材质具有导电性。
5.如权利要求1的电子组件的封装结构，其特征在于，其中上述缓冲层的该开口经微影制程、激光或预先开口方式所形成。
6.如权利要求1的电子组件的封装结构，其特征在于，还包含一导电层，该导电层形成于该电子组件上。
7.如权利要求1的电子组件的封装结构，其特征在于，其中上述缓冲层的厚度为30-200微米。
8.如权利要求1的电子组件的封装结构，其特征在于，其中上述电子组件与该缓冲层该接触面具有一折角。
9.如权利要求1的电子组件的封装结构，其特征在于，其中上述电子组件与该基板经一选自于由热压接合、超声波接合、热超声波接合、点焊接合或灌封接合所组成的族群的贴合制程来贴合。
10.一种电子组件的封装方法，包含：
形成一缓冲层于一基板的一第一表面，该缓冲层上有一第一开口，使该基板的该第一表面的一第一复数个接触点露出，其中该基板的该第一表面具有该第一复数个接触点及一第二复数个接触点、一第二表面具有复数个接合点，且该基板具有复数个介层洞，用以连接该第一复数个接触点及该复数个接合点；以及
安装一第一电子组件于该缓冲层上，使该第一电子组件对应该缓冲层上的该第一开口，其中该复数个电极具有电极的一表面与该基板的该第一表面相对，该缓冲层围绕该第一电子组件的周边，且该电子组件周边与该缓冲层的一接触面为非平面。
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