CN1665027A - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
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- CN1665027A CN1665027A CN2004100818011A CN200410081801A CN1665027A CN 1665027 A CN1665027 A CN 1665027A CN 2004100818011 A CN2004100818011 A CN 2004100818011A CN 200410081801 A CN200410081801 A CN 200410081801A CN 1665027 A CN1665027 A CN 1665027A
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- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
课题在于提供可以降低动作时的温度上升的半导体器件。把接口芯片2叠层到叠层起来的多个半导体元件1的上面。在多个半导体元件1的下面,配置Si内插板3和树脂基板内插板4。Si内插板3配置在树脂内插板4与多个半导体元件1之间,厚度比半导体元件1的厚度更厚,而且,具有小于树脂内插板4的线膨胀系数,大于等于多个半导体元件1的线膨胀系数的线膨胀系数。
Description
技术领域
本发明涉及半导体器件,特别是涉及适合于叠层安装多个半导体元件的半导体器件。
背景技术
半导体器件,特别是半导体存储器,已在大型计算机、个人计算机、便携设备等各种各样的信息设备中使用,被认为必要的容量逐年不断增加。另一方面,半导体存储器的安装面积也随着大容量化而增大,成为妨碍设备小型化的主要因素。于是,人们一直在开发高密度地安装半导体存储器的技术。作为用有限的安装面积实现大容量的存储器的技术,人们熟知:例如,就如在特开平11-40745号公报、特开平8236694号公报、特开2000-286380号公报所讲述的那样,把半导体封装叠层到安装基板上面的技术,和例如美国专利第3648131号说明书、美国专利第6141245号说明书、美国专利第5229647号说明书、特开昭59-222954号公报、特开昭61-88546号公报、特开昭63-156348号公报所讲述的那样,在1个半导体封装中叠层多个半导体元件,用设置在元件上的贯通孔把所叠层的半导体元件连接起来的技术。
但是,在要把多个DRAM叠层安装到1个半导体封装内的情况下,由于封装全体的发热量比装载1块DRAM的封装大,故存在着因动作时的温度上升而产生的动作故障或破损的悬念。
发明内容
本发明的目的在于提供可以降低动作时的温度上升的半导体器件。
(1)为了实现上述目的,本发明,在具有叠层起来的多个半导体元件,这些半导体元件中的至少一方用贯通电极与别的半导体元件形成导通的半导体器件中,其特征在于:具备接口芯片,该芯片被叠层到上述叠层起来的多个半导体元件的上面或下面,同时成为外部与上述半导体元件之间的接口。
倘采用该构成,则可以缩短叠层起来的多个半导体元件与接口芯片之间的布线,可以降低动作时的温度上升。
(2)在上述(1)中,理想的是把上述接口芯片配置在上述叠层起来的多个半导体元件的最上层。
(3)在上述(1)中,理想的是具备树脂内插板(interposer)和第2内插板,该第2内插板配置在上述树脂内插板与上述叠层起来的多个半导体元件之间,厚度大于等于上述半导体元件的厚度且线膨胀系数小于上述树脂内插板的线膨胀系数大于等于上述叠层起来的多个半导体元件的线膨胀系数。
(4)在上述(3)中,理想的是还具备配置在上述叠层起来的多个半导体元件的最上层,厚度大于等于上述半导体元件的厚度且线膨胀系数大于等于上述叠层起来的多个半导体元件的线膨胀系数的第2内插板;和树脂内插板,上述接口芯片配置在上述树脂内插板与上述叠层起来的多个半导体元件之间。
(5)在上述(3)或(4)中,理想的是上述第2内插板用Si构成。
(6)在上述(1)中,理想的是上述半导体元件中的至少2个是存储器。
倘采用本发明,则可以降低半导体器件的动作时的温度上升。
附图说明
图1的侧面剖面图示出了本发明的实施形态1的半导体器件的全体构成。
图2的底视图示出了本发明的实施形态1的半导体器件的全体构成。
图3的主要部分剖面图示出了本发明的实施形态1的半导体器件的主要部分构造。
图4A、4B是要在本发明的实施形态1中使用的贯通电极的说明图。
图5A到5K的工序图示出了本发明的实施形态1的半导体器件的制造方法。
图6A到6J的工序图示出了本发明的实施形态1的半导体器件的第2制造方法。
图7A、7B的构成图示出了本发明的实施形态2的半导体器件的全体构成。
图8A、8B的构成图示出了本发明的实施形态3的半导体器件的全体构成。
图9的侧面剖面图示出了本发明的实施形态4的半导体器件的全体构成。
图10的侧面剖面图示出了本发明的实施形态5的半导体器件的全体构成。
图11的侧面剖面图示出了本发明的实施形态6的半导体器件的全体构成。
图12的侧面剖面图示出了本发明的实施形态7的半导体器件的全体构成。
图13的侧面剖面图示出了本发明的实施形态8的半导体器件的全体构成。
图14的侧面剖面图示出了本发明的实施形态9的半导体器件的全体构成。
图15的侧面剖面图示出了已装载上本发明的实施形态9的半导体器件的存储器模块的构成。
具体实施方式
以下,用图1到图6J,对本发明的实施形态1的半导体器件的构成进行说明。下面的半导体器件以叠层了DRAM的半导体存储器为例进行说明。
首先,用图1和图2对本实施形态的半导体器件的全体构成进行说明。
图1的侧面剖面图示出了本发明的实施形态1的半导体器件的全体构成。图2的底视图示出了本发明的实施形态1的半导体器件的全体构成。
如图1所示,半导体器件10由叠层起来的8块DRAM1、配置在其上部的接口芯片2、作为配置在叠层起来的DRAM1的下部的第2内插板的Si内插板3和配置在其更下部的树脂基板内插板4构成。这些构件1、2、3、4,用模制树脂5密封起来。此外,还设置有作为用来进行与模块基板之间的连接的外部端子的焊料球6。如果设各个DRAM1的存储容量例如为512Mbit,则借助于图1所述的8层的DRAM1,就可以实现0.5Gbyte的半导体器件。
用多块的DRAM1构成存储单元。接口芯片2,总括地控制所有的存储单元,起着外部与作为半导体元件的DARM的接口的作用。多块的DRAM芯片与接口芯片2,用图2所述的贯通电极7连接起来。至于贯通电极的构成,将用图3在后边讲述。在现有的存储器模块中,在模块基板的上面,另外安装多个半导体器件和控制这些半导体器件的接口芯片,用布线把两者连接起来,相对于此,采用在叠层起来的DRAM1的上面安装接口芯片2的办法,可以缩短接口与存储单元的物理距离。此外,比起现有的存储器模块来还会减少接口的个数。结果是可以减少因接口芯片与存储单元之间的通信而产生的发热量,减少接口自身的发热量。
此外,由于要进行叠层的DRAM1不具有接口功能,故可以减少各个DRAM1的发热量。再有,采用把发热量大的接口芯片2设置在要进行叠层的半导体芯片的最上层的办法,由于可以借助于从半导体器件的上表面进行的散热使在接口芯片2中产生的发热效率良好的逃逸,故可以抑制动作时的半导体器件的温度上升。得益于这些温度降低的效果,就可以使内置多块的DRAM芯片的大容量的半导体器件动作而不会因热而产生误动作或破损。
在这里,DARM1、接口芯片2、Si内插板3的平面尺寸是相同的,例如是每边7mm的正方形形状。各个芯片的厚度,采用把DRAM1做成为50微米,把接口芯片2和内插板3做成为60微米的办法,就可以把叠层有多个芯片的半导体器件做成为低的安装高度。
此外,采用把接口芯片2和Si内插板3的厚度做成为大于等于DRAM1的厚度的办法,可以减小因在组装时或动作时的温度变化等而在DRAM1中产生的热应力,同时,还可以防止DRAM1被周边的树脂污染而使元件特性恶化。
就是说,当给DRAM芯片加上外力,在芯片内部产生了大的应力时,就存在着刷新性能的恶化等的性能降低或芯片破裂等的破损的可能性。特别是在为了进行叠层而使Si的厚度薄到数十微米左右的情况下,因芯片的刚性降低,要连接的树脂基板或要被模制的树脂之间的线膨胀系数差的影响就要起很大的作用。归因于此,在动作时的芯片的内部就要产生大的热应力。此外,还存在着由与DRAM芯片相邻的树脂的污染而产生的DRAM的性能的降低的可能性。相对于此,如上所述,采用在要进行叠层的DRAM芯片的上下层上,设置接口芯片2和内插板3的办法,就防止了DRAM芯片1直接与树脂基板或树脂平面性地连接。由于借助于此在动作时产生的Si与周边树脂之间的线膨胀系数差所产生的热变形量的差异被接口芯片2或内插板3吸收,故可以减小在DRAM1上所产生的应力。此外,可借助于接口芯片2或内插板3保护DRAM1的背面免受树脂影响,故可以防止污染。
作为第2内插板的Si内插板3,配置在具有Si衬底的DRAM芯片1和树脂基板内插板4之间。由于具有Si衬底的DRAM芯片1和树脂基板内插板4的线膨胀系数不同,故也可以把作为第2内插板的Si内插板3用作阻止在树脂基板内插板4上发生的应力向具有Si衬底的DRAM芯片1传导的缓冲构件。在这里,作为第2内插板,由于使用的是Si内插板3,故虽然第2内插板与具有Si衬底的DRAM芯片1的线膨胀系数是相同的,但是,并不限于此。作为第2内插板,只要是大于等于具有Si衬底的DRAM芯片1的线膨胀系数,而且,小于树脂基板内插板4的线膨胀系数的内插板都可以使用。具体地说,例如,可以使用氮化铝或氧化铝之类的陶瓷。
贯通电极7,如图2所示,配置在DRAM1的芯片中央部分的十字形状14上。由于用这样的形状来配置贯通电极,故即便是在归因于芯片的收缩或容量的变更等使得芯片尺寸变更了的情况或者混合载置不同尺寸的芯片的情况下,也可以进行叠层而无须变更电极配置。
树脂基板内插板4是平面尺寸18mm的正方形形状,是具有4层布线层的FR-4。在树脂基板内插板4的下表面上,作为用来与模块基板进行连接的外部端子设置有直径300微米左右的焊料球6。焊料球6,如图2所示,在树脂基板内插板4的周边部分上配置有每边各4列,在DRAM1的芯片正下面则不配置。如上所述,由于要配置焊料球6而可以防止因动作时的温度变化而产生的DRAM1或接口芯片2、Si内插板3等的Si与模块基板之间的热变形量差作为焊料球6的剪切变形直接发生作用,故可以确保焊料连接可靠性。
在半导体器件的上表面上,设置有金属制的散热板12。散热板的平面尺寸与树脂基板内插板相同,是每边18mm的正方形形状,厚度为0.3mm。另外,散热板12,用厚度0.2mm的热导电性树脂13与模制树脂5接合起来。在本实施形态中,半导体器件的动作时的发热部位主要是接口芯片2和DRAM1。就是说,对于半导体器件全体的平面尺寸18×18=324mm2来说发热部位为7×7=49mm2,是全体的15%左右。因此,可借助于散热板12使在DRAM1或接口芯片2中所发的热平面性地扩展,可以大大地降低动作时的温度上升。采用把热导率高的铜合金用于散热板12的办法,就可以效率良好地使在芯片中产生的热向平面方向上扩散。
其次,用图3对本发明的半导体器件的主要部分剖面图进行说明。
图3的主要部分剖面图示出了本发明的实施形态1的半导体器件的主要部分构造。另外,与图1和图2相同的标号表示同一部分。
在要进行叠层的Si芯片中,接口芯片2被设置在最上层。接口芯片2,由Si衬底2A、用集成电路技术在Si衬底2A的表面上形成的具有接口功能的电路层2b构成。由于把接口芯片2设置在最上层,故在接口芯片2内就不需要设置贯通电极7。
在接口芯片2的下部,叠层有8块DRAM1。8块的DRAM1都是同一构造。DRAM1,由Si衬底1A、用集成电路技术在Si衬底1A的表面上形成的构成存储单元的电路层1B构成。
在每一个DRAM1上,都设置贯通Si的贯通电极7,使得DRAM1与接口芯片2的通信成为可能。贯通电极7,采用在设置在Si上的直径约30微米的贯通孔内设置绝缘层,填充多晶硅的办法构成,各个贯通电极间的步距约为70微米。由于用多晶硅构成贯通电极7,故比起用与Si的线膨胀系数差大的Cu等构成贯通电极7的情况来,可以更进一步地减少DRAM1的贯通电极附近的热应力集中。为此,即便是在配置在贯通电极7附近的存储单元所产生的应力也小,可以防止起因于应力的存储器元件的特性变化。由于因此而可以把存储单元配置在贯通电极7附近,故可以更为有效地运用芯片面积。
在各个芯片1的贯通电极7之间,用已用底层填充树脂8密封起来的突点9接合起来,形成各个DRAM1芯片与接口芯片2的导通。在这里,采用突点9使用Au,底层填充树脂8使用与Au的线膨胀系数接近的树脂的办法,减少在温度变化时在突点8上产生的热应力,确保连接可靠性。接合后的突点9的高度约20微米。
在叠层起来的DRAM1的下部,配置有Si内插板3。Si内插板3,由Si衬底3A和用集成电路技术在Si衬底3A的表面上形成的布线层3B构成。贯通Si内插板3地设置有贯通电极7B。相对于设置在DRAM1上的贯通电极7的步距为70微米,设置在Si内插板3上的贯通电极7B的步距为200微米。布线层3B,把用来与DRAM1进行连接的70微米的步距的突点9B和200微米的步距的贯通电极7B连接起来,借助于布线层3B,布线步距被扩大到200微米。因此,Si内插板3的贯通电极7B与DRAM1的贯通电极7的场所不同。
在Si内插板3的下部设置有树脂基板内插板4,Si内插板3与树脂基板内插板4之间,已用设置在Si内插板3的贯通电极7B的下部的焊料球15接合起来。焊料球15已用底层填充树脂11密封起来。这时,采用把线膨胀系数与焊料球接近的材料用做底层填充树脂的办法,防止由温度变化引起的连接部分的可靠性的降低。树脂基板内插板4具有4层的布线层,在最上层上的布线步距,为了与Si内插板3之间的连接,是200微米,采用使用内部的布线层扩大布线步距的办法,使最下层上的突点步距变成为800微米。在各个突点上,如图1和图2所示,设置有用来与模块基板之间进行连接的直径300微米左右的焊料球6。
在本实施形态的构造中,由于在不同的半导体元件内已形成了存储单元和接口芯片,故在各个DRAM芯片上就需要1000条左右的贯通电极。为此,各个贯通电极间的步距就变成了约70微米。由于在这些电极之内,那些仅仅在DRAM芯片与接口芯片的通信中使用的电极没有必要与外部模块基板进行连接,故要与模块基板进行连接的半导体器件的外部端子数约为256条左右。这时,人们认为如果考虑在模块基板上的布线步距,则就产生了在大于等于DRAM芯片的平面尺寸的平面面积上配置半导体器件的外部端子的必要。此外,从安装后的连接部分对温度变化的可靠性的观点来看,把半导体器件的外部端子配置在芯片的周边部分而不是DRAM芯片的正下面是理想的。于是,在本发明中,采用设置与Si制的内插板3分开的树脂基板(FR-4)的内插板4的办法,在大于等于芯片平面尺寸的平面尺寸上引绕布线,把半导体器件的外部端子设置在DRAM芯片的周边部分上。此外,由于使用多块的内插板3、4,故使得在各个芯片间的贯通电极与模块基板的端子这样的步距差异大的布线间的引绕变得容易起来。此外,由于Si制的内插板3与树脂基板的内插板4之间用刚性低的焊料球和底层填充树脂进行接合,故可以减少起因于Si与模块基板的线膨胀系数差而在DRAM芯片中产生的热应力。
其次,以图4A、4B,对本实施形态的半导体器件所使用的贯通电极的配置进行说明。
图4A、4B是要在本发明的实施形态1中使用的贯通电极的说明图,图4A与图2同样,是本发明的实施形态1的半导体器件的底视图,图4B的图4A的A部分的扩大图。另外,与图1到图3相同的标号,表示同一部分。
在DRAM1的内部,如图4A所示,十字形状地配置贯通电极7,此外,如图4B所示,每组各6列地分别并排配置起来。其中,中心2列的突点32,是目的为进行用来提高散热特性的热传导的突点,不接受电信号的通信。此外,外侧的各2列(合计4列)用于信号或电源的布线。由于采用像这样地把用来进行热传导的突点配置在中心2列上的办法,而使得只要在突点9之间通1条布线31就可以进行信号或电源的布线,故布线的引绕比把这些部分用做信号管脚来更为容易。另外,在本实施形态中,虽然设置有用来进行热传导的贯通电极,但是,在半导体元件的发热量小的情况下,也可以仅仅设置用于信号或电源的贯通电极。在该情况下,贯通电极7就可以每组各4列地排列起来构成十字形状。
其次,用图5A到5K,对本实施形态的半导体器件的制造方法进行说明。
图5A到图5K的工序图示出了本发明的实施形态1的半导体器件的制造方法。另外,与图1到图4相同的标号,表示同一部分。
如图5A所示,首先,准备实施背研磨之前的充分地厚的接口芯片2’和已加工成厚度50微米的具有贯通电极的1块DRAM芯片1。这时,在DRAM芯片1上已设置有贯通电极7。此外,在贯通电极7的上面和接口芯片2’上,设置有突点9。
其次,如图5B所示,向接口芯片2’与DRAM1的接合面上涂敷底层填充树脂8,如图5C所示,把两芯片2’、1的突点9接合起来。这时,要采用升温为使得用做两芯片的突点9的Au进行金属间结合,同时,提供超声波振动的办法,实现牢固的接合。此外,还可以采用借助于该升温工序使底层填充树脂8硬化的办法,使之变成为更加牢固的接合。在接合前的厚度薄到50微米的DRAM1芯片上虽然会产生挠曲,但是,采用使得被推压到具有充分的厚度的接口芯片2’上那样地进行接合的办法,由于可以矫正DRAM1芯片的挠曲,故可以减小接合后的挠曲。
另外,在本实施形态中,虽然是在把接口芯片2’和DRAM1接合起来之前涂敷底层填充树脂8,然后进行芯片间的接合的,但是在使用浸透性高的底层填充树脂8的情况下,也可以在芯片间接合结束后,再使底层填充树脂8向接合突点间浸透。在该情况下,可以防止突点间接合时的由底层填充的助焊剂等产生的空隙的发生。但是,如果要使用的底层填充树脂8的浸透性不足,由于存在着不能充分地实施底层填充密封的可能性,故究竟哪种工序是理想的,要根据所要使用的底层填充树脂的特性等决定。
其次,如图5D所示,在接合后的DRAM1的背面上设置Au突点9。然后,用所设置的Au突点,返回到图5B所示的工序,用与先前大体上同样的工艺叠层第2段的DRAM1。采用反复进行该工序的办法,就可以在接口芯片2’上面叠层8块DRAM1。
其次,如图5E所示,涂敷在图5B到5D的工序中进行了叠层的DRAM1的底层填充树脂8。然后,载置上具有Au突点9B和贯通电极7B的Si内插板3后,如图5F所示,把两者接合起来。
另外,在本实施形态中,虽然是依次进行各个芯片间的接合,但是,也可以使用于进行接合的底层填充在非真正硬化的状态下不断叠层下去,在已叠层上Si内插板3的阶段中再进行真正硬化的工序。在该情况下,可以减少要给全体施加的热履历。
其次,如图5G所示,一直到厚度变成为60微米为止对接口芯片2进行背研磨。这时,已用小的挠曲把8块DRAM1和1块Si内插板3接合起来。故即便是接口芯片2变薄,也可以防止在叠层起来的构造全体上产生大的挠曲变形。此外,由于各个芯片的平面尺寸是相同的,不会变成为薄的Si被剥离下来,故可以防止处理时的断裂等的发生。
其次,如图5H所示,在Si内插板3的背面上,形成焊料球15,如图5I所示,与树脂基板内插板4进行接合。这时,Si内插板3与树脂基板内插板4的接合面,要用底层填充树脂11密封起来。
然后,如图5J所示,采用用模制树脂5把树脂基板内插板4和接口芯片2、DRAM1和Si内插板3密封起来,如图5K所示,在树脂基板4的背面上形成用来与模块基板进行连接的突点6的办法,就可以制造半导体器件10。此外,根据需要,还可以如图1所示,在模制树脂5的上表面上通过热传导性树脂13设置散热板12。借助于这样的工序,就可以组装可靠性高的半导体器件。
其次,用图6对本实施形态的半导体器件的第2制造方法进行说明。
图6的工序图示出了本发明的实施形态1的半导体器件的第2制造方法。另外,与图1到图5K相同的标号,表示同一部分。
在图5A到5K所示的第1组装方法中,在把DRAM1、接口芯片2、Si内插板3切成芯片尺寸后再进行叠层。该方法,即便是各个芯片的成品率不好的状态下,由于也可以对各个芯片进行检查,仅仅把合格品汇集起来进行叠层,故是一种特别适合于高端产品的组装方法。另一方面,在各个芯片的成品率好的产品组装中,可以使用采用进行在晶片状态下的叠层而不是对每一个芯片进行叠层的办法提高组装效率的工序。
图6A到6J,示出了在晶片状态下进行的叠层工序。首先,如图6A所示,准备实施背研磨之前的充分地厚的晶片状态的接口芯片2’和实施背研磨之前的晶片状态的DRAM1’。虽然由于没有对DRAM1’实施背研磨而未贯通,但是却设置有已埋入到Si内部的多晶硅的电极7。
其次,如图6B所示,事前向晶片结合部分上涂敷底层填充树脂8,如图6C所示,用Au的金属间接合把两晶片的突点连接起来。这时,要用不含助焊剂的底层填充树脂的使用或用来使助焊剂逃逸在晶片的一部分上设置逃逸孔等,防止在底层填充树脂中产生空隙。
其次,如图6D所示,对晶片级的DRAM1’的背面实施背研磨,使多晶硅的贯通电极7露出来。
其次,如图6E所示,在露出来的电极上面设置Au突点9。然后,采用反复进行图6B到6E的工序的办法,就可以在晶片状态下把1块接口芯片2和8块DRAM1叠层起来。
其次,如图6F所示,准备未实施背研磨的晶片状态的Si内插板3’,如图6G所示,把晶片状态的Si内插板3’连接到叠层起来的DRAM1上,然后,如图6H所示,实施背研磨,以使Si内插板3’的背面露出来。
其次,如图6I所示,一直到厚度60微米为止对接口芯片2的背面进行背研磨,如图6J所示,采用划片的办法,完成以芯片尺寸把接口芯片、8块的DRAM1和Si内插板3叠层起来的构造体。之后的工序,转移到图5F以后的工序,就可以制造半导体器件10。
另外,在图5A到5K或图6A到6J所示的制造工序,在可进行各种各样的考虑的本发明的实施形态中,示出了在芯片状态下进行组装的组装方法和在晶片状态下进行组装的组装方法的各1个制造方法,即便是用另外的工序制造的半导体器件,只要具有本发明的特长,理所当然地也可以得到本发明的效果。
如上所述,倘采用本实施形态,由于要在构成存储单元的多块的DRAM芯片的上面叠层对全部存储单元总括地进行控制的接口芯片,并用贯通电极把这些芯片连接起来,故可以减少发热量。
此外,由于要把发热量大的接口芯片设置到要进行叠层的半导体芯片的最上层,故可以抑制动作时的半导体器件的温度上升。
再有,由于要把接口芯片设置到进行叠层的DRAM芯片的上面,把Si的内插板设置在下面,故即便是DRAM芯片薄的情况下,也可以减小在DRAM芯片中产生的应力。
此外,由于要用多块的内插板,故将使得各个芯片闻的贯通电极和模块基板的端子这样的步距差异大的布线间的引绕变得容易起来。
此外,由于把半导体器件的外部端子配置在芯片的周边部分上而不是DRAM芯片的正下面,故可以提高安装后的连接部分对温度变化的可靠性。
其次,用图7A、7B,对本发明的实施形态2的半导体器件的构成进行说明。
图7A、7B的构成图示出了本发明的实施形态2的半导体器件的构成,图7A是侧面剖面图,图7B是底视图。另外,与图1和图2相同的标号,表示同一部分。
在本实施形态的半导体器件10A中,不仅要在DRAM1的底面周边部分上设置焊料球6,在DRAM1的中央部分正下面,也设置有用来进行树脂基板内插板4与模块基板的接合的焊料球6A。
在把焊料球6A配置在DRAM1的正下面的情况下,由温度变化产生的Si与模块基板的热变形量差对于焊料球6A就起着剪切负荷的作用。但是,在DRAM1的中央部分处,不会发生Si与模块基板的热变形量差。为此,在配置在DRAM1的中央部分附近的焊料球6A上只能发生小的剪切方向负荷,可以确保连接寿命。由于在DRAM1的正下面有焊料球,故可以效率良好地使在芯片中产生的热向模块基板逃逸。
因此,接口芯片2与模块基板之间的布线管脚个数多而且恰好在树脂基板内插板4的周边部分不能配置焊料球6的情况下,或者,在接口芯片2与DRAM1的发热量大的情况下,就可以使用本实施形态这样的焊料球配置。
其次,用图8A、8B对本发明的实施形态3的半导体器件的构成进行说明。
图8的构成图示出了本发明的实施形态3的半导体器件的构成,图8A是侧面剖面图,图8B是底视图。另外,与图1和图2相同的标号,表示同一部分。
在本实施形态在半导体器件10B中,在树脂基板内插板4的整个上表面上,都配置有焊料球6B。如上所述,在不把焊料球6B配置在树脂基板内插板4的整个下表面上的情况下,归因于热变形在配置在DRAM1的拐角部分周边上的焊料球6B中就会产生大的剪切变形负荷,存在着产生龟裂或破断的悬念。因此,把这些焊料球用做信号布线或电源布线是不适当的。但是,即便是在焊料球6B中发生了龟裂或破断的情况下,由于较热导率比没有焊料球而且DRAM1的正下面变成了空气层的情况下大,故比起没有焊料球6B的情况来半导体器件的散热特性将会提高。
因此,在接口芯片3或DRAM1的发热量大而且需要提高散热特性的半导体器件中,可以使用本实施形态这样的焊料球配置。
其次,用图9对本发明的实施形态4的半导体器件的构成进行说明。
图8的侧面剖面图示出了本发明的实施形态4的半导体器件的构成,另外,与图1和图2相同的标号,表示同一部分。
在本实施形态在半导体器件10C中,在树脂基板内插板4的下表面上,配置管脚81而不是焊料球。由于在树脂基板内插板4和模块基板之间的接合中使用管脚81,故半导体器件10C,就不会经受焊料回流工序的热履历。在使半导体器件通过回流工序时,当树脂或底层填充树脂等的树脂吸湿后,就存在着产生树脂断裂等的缺憾的悬念。为此。在用户一侧进行器件向模块基板上的安装的情况下,用户就必须进行吸湿管理。但是,在像本实施形态那样使用管脚81进行器件向模块基板上的安装的情况下,则没有必要进行该管理,可以减轻用户一侧的负担。但是,在本实施形态的情况下,用户必须在模块基板1上设置用来接受管脚81的插座。
其次,用图10,对本发明的实施形态5的半导体器件的构成,进行说明。
图10的侧面剖面图示出了本发明的实施形态5的半导体器件的构成,另外,与图1和图2相同的标号,表示同一部分。
在本实施形态的半导体器件10D中,在树脂基板内插板4下表面上,配置的是插座91而不是焊料球。在本实施形态中,与图9的实施形态同样,由于不需要在用户一侧进行回流工序,故可以减轻用户一侧的吸湿管理的负担。但是,在本实施形态中,用户必须在模块基板上设置与插座91对应的插座。
其次,用图11对本发明的实施形态6的半导体器件的构成进行说明。
图11的侧面剖面图示出了本发明的实施形态6的半导体器件的全体构成。另外,与图1和图2相同的标号,表示同一部分。
在本实施形态中,采用在1块模块基板101上装载多个上面所说的构成的半导体器件的办法,实现了大容量的存储器模块。模块基板101具备模块基板端子102。在DIMM规格的模块基板上面单面可以装载6个左右,在两面上可以装载12个左右的半导体器件10,如果如上所述设1个半导体器件10的存储容量为0.5GB,则具备12个半导体器件的存储器模块的存储容量就变成为6GB。因此,采用把本半导体器件安装在DIMM规格的模块基板或SODIMM规格的模块基板上的办法,与同样规格的现状的产品比较,可以得到容量非常大的存储器模块产品。
其次,用图12对本发明的实施形态7的半导体器件的构成进行说明。
图12的侧面剖面图示出了本发明的实施形态7的半导体器件的全体构成。另外,与图1和图2相同的标号,表示同一部分。
在本实施形态中,在半导体器件10E的内部,装载有DRAM1以外的元件。在本半导体器件10E中,由于树脂基板内插板4的平面尺寸比DRAM1的平面尺寸大,故可以在树脂基板内插板4上面表面安装芯片电阻或芯片电容等的无源元件111。由于要像这样地内置无源元件,故可以增强作为半导体元件的功能。
其次,用图13对本发明的实施形态8的半导体器件的构成进行说明。
图13的侧面剖面图示出了本发明的实施形态8的半导体器件的全体构成。另外,与图1和图2相同的标号,表示同一部分。
在本实施形态中,在8块叠层起来的DRAM1的上部设置Si内插板121,在Si内插板121的上部,装载逻辑电路等的DRAM以外的半导体元件122,在最上部装载接口芯片2。如上所述,由于要把Si内插板121配置在DRAM和DRAM以外的电路之间,故可以混合装载各种各样的电路。这时,由于在DRAM以外的芯片122上也与DRAM同样把贯通电极配置成芯片中央的十字形状,故可以进行与用户一侧的要求对应的各种各样的芯片的组合。再有,除去DRAM以外的要装载的芯片,可以装载多块而没有必要是1块。
其次,用图14和图15对本发明的实施形态9的半导体器件的构成进行说明。
图14的侧面剖面图示出了本发明的实施形态9的半导体器件的全体构成。图15的侧面剖面图示出了已装载上本发明的实施形态9的半导体器件的存储器模块的构成。另外,与图1和图2相同的标号,表示同一部分。
如图14所示,本半导体器件10G,由叠层起来的8块DRAM1、配置在叠层起来的DRAM1的上部的作为第2内插板的Si内插板3、配置在叠层起来的DRAM1的下部的接口芯片2、配置在其更下部的树脂基板内插板4构成。这些构件1、2、3、4,要用模制树脂5密封起来,此外,还设置有作为用来进行与模块基板之间的连接的外部端子的焊料球6。就是说,与图1所示的构成,把Si内插板3与接口芯片2的上下位置颠倒了过来。采用把接口芯片2与Si内插板3的厚度,(例如,60微米)做成为大于等于DRAM1的厚度(例如,50微米)的办法,在降低了因组装时或动作时的温度变化等在DRAM1中产生的热应力的同时,还防止了DRAM1因被周边的树脂污染使得元件特性恶化。此外,Si内插板3,由于理想的是使用具有大于半导体元件1的线膨胀系数的线膨胀系数的构件,故在这里,使用的是作为与半导体元件1相同的材料的Si。另外,作为第2内插板,可以使用氮化铝或氧化铝之类的陶瓷。
用贯通电极把多块DRAM芯片1和接口芯片2连接起来。设置在Si内插板3上的电极,借助于键合金丝41与设置在树脂基板内插板4上的电极进行连接。
如图15所示,在树脂基板内插板4上,设置有已贯通了的热传导性优良的铜通路42。铜通路42与在树脂基板内插板4的上表面上形成的焊料球6C连接起来。另一方面,在模块基板50上,设置有已贯通了的热传导性优良的铜通路51。用焊料球6C把铜通路51与铜通路42连接起来,接口芯片2的发热,通过铜通路42、51向外部散热。
倘采用以上的构成,采用把总括地对全部存储单元进行控制的接口芯片叠层到构成存储单元的多块DRAM芯片的下面,用贯通电极把这些芯片连接起来的办法,也可以减少发热量。
此外,由于把接口芯片设置在要进行叠层的DRAM芯片的下面,在上面设置Si内插板,故即便是在DRAM芯片薄的情况下,也可以减小在DRAM芯片上产生的应力。
再有,由于在芯片的周边部分而不在DRAM芯片的正下方配置半导体器件的外部端子,故可以提高安装后的连接部分对温度变化的可靠性。
以上根据实施形态具体地对本发明进行了说明,但是本发明并不限于上述实施形态,不言而喻在不脱离本发明的宗旨的范围内,种种的变更是可能的。
Claims (7)
1.一种半导体器件,具有叠层状态的多个半导体元件,这些半导体元件中的至少一个半导体元件用贯通电极与其它半导体元件形成导通,其特征在于:
上述半导体器件具备接口芯片,该接口芯片叠层于上述叠层状态的多个半导体元件的上面或下面并且成为外部与上述半导体元件之间的接口。
2.根据权利要求1所述的半导体器件,其特征在于:上述接口芯片配置在上述叠层状态的多个半导体元件的最上层。
3.根据权利要求2所述的半导体器件,其特征在于还具备:
树脂内插板;以及
配置在上述树脂内插板与上述叠层状态的多个半导体元件之间的第2内插板,该第2内插板的厚度大于等于上述半导体元件的厚度且线膨胀系数小于上述树脂内插板的线膨胀系数大于等于上述叠层状态的多个半导体元件的线膨胀系数。
4.根据权利要求1所述的半导体器件,其特征在于还具备:
配置在上述叠层状态的多个半导体元件的最上层的第2内插板,该第2内插板厚度大于等于上述半导体元件的厚度且线膨胀系数大于等于上述叠层的状态的多个半导体元件的线膨胀系数;以及
树脂内插板,
上述接口芯片配置在上述树脂内插板与上述叠层状态的多个半导体元件之间。
5.根据权利要求3所述的半导体器件,其特征在于:上述第2内插板用Si构成。
6.根据权利要求4所述的半导体器件,其特征在于:上述第2内插板用Si构成。
7.根据权利要求1所述的半导体器件,其特征在于:上述半导体元件中的至少2个是存储器。
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JP2004055630A JP4205613B2 (ja) | 2004-03-01 | 2004-03-01 | 半導体装置 |
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JP (1) | JP4205613B2 (zh) |
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TWI249238B (en) | 2006-02-11 |
JP2005244143A (ja) | 2005-09-08 |
TW200531259A (en) | 2005-09-16 |
CN100411172C (zh) | 2008-08-13 |
US20050189639A1 (en) | 2005-09-01 |
KR100602106B1 (ko) | 2006-07-19 |
JP4205613B2 (ja) | 2009-01-07 |
US7119428B2 (en) | 2006-10-10 |
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