CN1675761A - 具有芯片级封装外壳的半导体器件 - Google Patents

具有芯片级封装外壳的半导体器件 Download PDF

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CN1675761A
CN1675761A CNA038187248A CN03818724A CN1675761A CN 1675761 A CN1675761 A CN 1675761A CN A038187248 A CNA038187248 A CN A038187248A CN 03818724 A CN03818724 A CN 03818724A CN 1675761 A CN1675761 A CN 1675761A
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semiconductor device
semiconductor chip
expansion
described semiconductor
shell
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CN100565852C (zh
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哈里·黑德勒
托尔斯滕斯·迈耶
芭芭拉·瓦斯克斯
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Infineon Technologies AG
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Abstract

本发明涉及一总用于安装在印刷电路板上的半导体器件(1)。所述半导体器件包括外壳(8)。此外壳(8)至少部分地环绕至少一个平坦半导体芯片(3)。将电触点(5)分配给所述半导体芯片，并用于建立与设置在所述印刷电路板上的电极或电极表面的电连接。所述平坦半导体芯片(3)具有安装侧表面(33)。将用于与所述电触点(5)接触的电接触表面设置在所述安装侧表面(33)上。位于所述外壳(8)和所述半导体芯片之间的缓冲层(7)环绕所述半导体芯片(3)，直至位于所述安装侧表面(33)上的支撑表面(31)。此支撑表面(31)比所述安装侧表面(33)小得多。

Description

具有芯片级封装外壳的半导体器件
技术领域
本发明涉及一种用于安装在印刷电路板上的半导体器件，所述半导体器件包括外壳，该外壳至少部分环绕半导体芯片，将电触点分配给所述半导体芯片，通过所述电触点产生与设置在印刷电路板上的电极或电极区的电连接。
背景技术
在大规模集成且极大地小型化的半导体器件中，问题在于：对于已经将所述器件安装在印刷电路(印刷电路板)上之后的强烈延伸，在温度波动的情况下，考虑到所包括的材料的不同的热膨胀系数，在所述器件内和所述器件与印刷电路板之间将发生较强的机械应力。图4示出了这种小型化半导体模块的传统设计。半导体器件1通过其电触点5与印刷电路板2相连。半导体芯片3通过电触点14与插入机构12相连，为了机械稳定的目的，通过底层填料13将半导体芯片焊接到插入机构上。还以封装15对半导体芯片3进行封装。通常，也对作为载体的插入机构12进行完全的封装。
由于温度波动或变化，考虑到不同材料的不同热膨胀系数，机械应力以已知分量的形式发生。图5对此进行了更为详细的描述。半导体芯片3具有比插入机构12低的热膨胀系数α，这由于不同的材料而导致。考虑到半导体芯片和插入机构的不同膨胀，较强的机械应力16通过机械固定和稳定所需的底层填料13进行传递，并在插入机构12中产生。为了不发生电触点14的连接断裂，必须使插入机构的热膨胀系数适应于半导体芯片。但是，通常所使用的印刷电路板2具有极大地不同于半导体芯片的热膨胀系数。因此，已经受到机械应力的插入机构12通过所述插入机构使其变形的电触点5向印刷电路板2施加较强的机械应力17。在极端情况下，这种较强的机械变形可能会导致印刷电路板的变形，尤其是在双侧组装的印刷电路板的情况下，可能会导致电触点5的断裂，并因而导致对电子设备的破坏。如果变形并不立即导致断裂，但是，在多次应变和应变消除的过程中，其将导致电触点5的材料的疲劳，于是，最终导致其断裂，并限制了使用寿命。此外，半导体器件自身程度不同的膨胀，并由此而得的机械应力，即一方面在半导体芯片和插入机构之间，另一方面，在其中再次引入变形18的半导体芯片和封装之间，导致了电触点14的疲劳，结果是可能会损坏半导体器件1。
为了防止来自插入层的机械应力或其传输，只通过隆起焊盘(bump)将半导体芯片直接设置在印刷电路板上并不能实现该目的，由于通过此装置并不能产生半导体芯片与印刷电路板之间的永久稳定的机械连接。此外，芯片通过隆起焊盘与底层填料的粘性焊接，例如，以环氧粘结剂的形式，只会将来自半导体芯片的直接变形传递给印刷电路板。这将再次导致具有上述困难的印刷电路板的变形。特别地，在双侧组装的印刷电路板的情况下，将导致对位于印刷电路板的一侧的电路或所述电路的电触点的破坏。
因此，为了仍然能够生产出具有足够长的寿命的电子电路，复杂而昂贵的外壳结构对于半导体器件而言是必需的。
发明内容
因此，本发明的目的在于提供一种半导体器件，其中不会发生上述缺点，并且仍然能够进行非常紧凑的设计。
通过权利要求1中的特征来实现上述目的。
本发明在于：平坦半导体芯片，具有安装侧区域，用于与设置在安装侧区域上的电触点接触，除了排列在安装侧区域上的支撑区域外，半导体芯片由缓冲层所环绕，该缓冲层位于外壳和半导体芯片之间，该支撑区域比安装侧区域小得多。
事实上，本发明提出：通过较小的支撑面积并从而导致与具有不利热膨胀系数的材料的较小空间接触来分离半导体芯片，结果，半导体芯片可以在外壳内膨胀到比环绕外壳或将半导体器件固定在其上的印刷电路板更小或更大的程度，而不会带来机械应力。在这种情况下，通过外壳，在其在印刷电路板上的位置上，确保了芯片的机械稳定。这使其能够适应印刷电路板材料的热机械特性，从而实现了印刷电路板(例如，印刷电路)与半导体器件之间的永久、无变形连接。
本发明的优选改进在于：在排列在安装侧区域上的支撑区域上，将半导体芯片机械地支撑在由所述外壳整形而得的支撑底座上。
优选地，在排列在安装侧区域上的支撑区域上，将半导体芯片机械地固定连接到由所述外壳整形而得的支撑底座上。
有利地，将所述支撑区域设置在所述安装侧区域的中心。
本发明的一个改进在于：所述外壳完全环绕所述半导体芯片。
本发明的优选改进在于：按照WLP(“晶片级封装”)、倒装芯片或CSP设计(“芯片级封装”)来生产所述半导体器件。
有利地，以隆起焊盘形成所述电触点。
有利地，并因而优选地，所述外壳与所述半导体芯片的侧区域之间的缓冲层的直径G至少为：
G : = C · α F - α C α G - α F
其中G是所述外壳与所述半导体芯片的侧区域之间的缓冲层的直径，C是从所述侧区域到所述半导体芯片的中心点的焊料的长度，αC是所述半导体芯片的热膨胀系数，αG是所述缓冲层的热膨胀系数，以及αF是所述外壳的热膨胀系数。
类似有利的是，根据本发明的一个改进，选择缓冲层的材料，从而使所述缓冲层的热膨胀系数大于将所述半导体器件固定于其上的印刷电路板的热膨胀系数。因此，选择材料，从而使缓冲层对应于所述半导体芯片的半导体材料(例如硅等)的较低热膨胀系数，从而使其一起对应于所述外壳或所述印刷电路板的热膨胀系数。
因此，本发明的一个改进在于：所述缓冲层是高度弹性的。
根据本发明的优选改进，选择所述外壳的材料，从而使所述外壳的热膨胀系数等于将所述半导体器件固定在其上的印刷电路板的热膨胀系数。
本发明的特别优选改进在于：选择所述外壳的材料，从而使所述外壳的热膨胀系数大于所述半导体芯片的热膨胀系数。
因此，本发明的一个改进在于：选择所述缓冲层和所述半导体芯片的材料，从而使其在一起的热膨胀系数等于所述外壳和/或将所述半导体器件固定在其上的印刷电路板的热膨胀系数。
通过其他从属权利要求或其组合，本发明的其他优点、特定特征和有利发展将显现出来。
附图说明
下面，将参照附图，对本发明进行更为详细的解释，其中：
图1示出了用于安装在印刷电路板上的本发明的半导体器件；
图2示出了根据本发明第二实施例的半导体器件；
图3示出了沿观看方向III所看到的图1和2中的半导体器件；
图4示出了安装在印刷电路板上的传统半导体器件；
图5示出了印刷电路板上的传统半导体器件的变形的图示；
图6示出了图1所示的半导体器件的细节视图；以及
图7示出了半导体器件的元件尺寸的示意图。
在附图中，相同的参考符号表示相同或相同作用的元件。
具体实施方式
图1示意性地示出了用于安装在印刷电路板上的本发明的半导体器件1。在这种情况下，由外壳8完全封装半导体芯片3，以便保护其不受外部影响。在外壳8内，除了支撑区域31外，半导体芯片3被缓冲层7所环绕。在支撑区域31内，通过电接触区域32、经由以隆起焊盘6(小焊料球，“焊料隆起焊盘”)的形式馈入电触点5的馈线连接半导体芯片3，通过所述馈线，形成与为此目的而设置在印刷电路板(未示出)的印刷电路板表面上的电极区域的电接触。
只通过支持区域31，将半导体芯片3本身与外壳8机械地相连。否则，将半导体芯片柔软地嵌入在弹性缓冲层中，从而排除与外壳之间的变形和半导体器件的外部尺寸的合成变形。
因此，半导体芯片和印刷电路板的不同热膨胀系数α不会导致变形，这是因为通过足够适应的缓冲层7缓解了印刷电路板与半导体芯片3之间的不同膨胀。此外，半导体芯片3与外壳8之间的不同膨胀不再施加到内触点32上，因为通过触点在芯片总面积的较窄区域中的中心排列，温度导致的相对于外壳的膨胀不再导致错位。结果，不再引起半导体器件内部以及半导体器件外侧的电触点的疲劳。极大地增加了使用寿命。
图2示出了半导体器件1的另一典型实施例，其中电触点由所谓的适应隆起焊盘(Compliant Bump)61形成。在这种情况下，通过硅树脂整形形成实际的隆起焊盘61，在进行接触的目的的情况下，涂覆有薄且高柔软性的材料带6a，以便实现电接触。
图3示出了沿图1和图2中的观看方向III而得到的视图。电接触区域32位于其中的支撑区域31比安装侧区域33小得多并位于其中心。
图6再次以更为详细的方式示出了对图1的引用，根据以下关系确定层厚度的尺寸：
G : = C · α F - α C α G - α F
其中αC是半导体芯片的热膨胀系数，αG是缓冲层7的热膨胀系数，以及αF是外壳的热膨胀系数。C是侧区域与中心轴34之间的距离。G表示这种情况下的最小值。
图7作为实例，示出了其中根据半导体芯片直径C的一半绘制缓冲层的厚度G的示意图。在这种情况下，8.7％的梯度得自于如下对热膨胀系数的假设值：
αC：＝3·10-6/K
αG：＝300·10-6/K
αF：＝16·10-6/K。
参考符号列表：
1        半导体器件
2        印刷电路板
3        半导体芯片
31       支撑区域
32       电接触区域
33       安装侧区域
34       中心轴
4、8     外壳
5        电触点
6        隆起焊盘
61       适应隆起焊盘
6a       金属带
7        缓冲层
9        支撑底座
91       馈线
10       印刷电路板的表面
12       插入机构
13       底层填料
14       电触点
15       封装
16到18   机械应力

Claims (18)

1、一种用于安装在印刷电路板上的半导体器件(1)，所述半导体器件包括外壳(8)，该外壳(8)至少部分地环绕至少一个以平面方式形成的半导体芯片(3)，将电触点(5)分配给所述半导体芯片，通过所述电触点(5)，产生与设置在印刷电路板上的电极或电极区域的电连接，其特征在于
所述平坦半导体芯片(3)具有安装侧区域(33)，电接触区域(32)，用于与设置在所述安装侧区域(33)上的电触点(5)接触，除了排列在所述安装侧区域(33)上的支撑区域(31)以外，所述半导体芯片(3)被缓冲层(7)所环绕，该缓冲层位于所述外壳(8)和所述缓冲层之间，该支撑区域(31)比所述安装侧区域(33)小得多。
2、根据权利要求1所述的半导体器件，其特征在于：
在排列在安装侧区域(33)上的支撑区域(31)上，将半导体芯片(3)机械地支撑在由所述外壳(8)整形而得的支撑底座(9)上。
3、根据权利要求1或2所述的半导体器件，其特征在于：
在排列在安装侧区域(33)上的支撑区域(31)上，将半导体芯片(3)机械地固定连接到由所述外壳(8)整形而得的支撑底座(9)上，并且所述底座用于将馈线(91)从所述电触点(5、6、61)馈入所述电接触区域(32)。
4、根据权利要求1到3之一所述的半导体器件，其特征在于：
将所述支撑区域(31)设置在所述安装侧区域(33)的中心。
5、根据权利要求1到3之一所述的半导体器件，其特征在于：
将所述支撑区域(31)设置在所述安装侧区域(33)的几何形心。
6、根据前述权利要求之一所述的半导体器件，其特征在于：
所述外壳(8)完全环绕所述半导体芯片(3)。
7、根据前述权利要求之一所述的半导体器件，其特征在于：
按照WLP(“晶片级封装”)、倒装芯片或CSP设计(“芯片级封装”)来生产所述半导体器件(1)。
8、根据前述权利要求之一所述的半导体器件，其特征在于：
以隆起焊盘(6)形成所述电触点(5)。
9、根据前述权利要求之一所述的半导体器件，其特征在于：
所述隆起焊盘(6)是小焊料球(“焊料隆起焊盘”)。
10、根据权利要求1到8之一所述的半导体器件，其特征在于：
所述隆起焊盘(6)是具有导电区域引线的硅树脂隆起焊盘，以便实现接触的目的，或者是实质上由硅树脂组成的导电隆起焊盘(“适应隆起焊盘”)。
11、根据前述权利要求之一所述的半导体器件，其特征在于：
所述外壳(8)与所述半导体芯片(3)的侧区域之间的缓冲层(7)的直径G至少为：
G : = C · α F - α C α G - α F
其中G是所述外壳(8)与所述半导体芯片(3)的侧区域之间的缓冲层(7)的直径，C是从所述侧区域到所述半导体芯片(3)的中心点的焊料的长度，αC是所述半导体芯片(3)的热膨胀系数，αG是所述缓冲层(7)的热膨胀系数，以及αF是所述外壳(8)的热膨胀系数。
12、根据前述权利要求之一所述的半导体器件，其特征在于：
选择缓冲层(7)的材料，从而使所述缓冲层的热膨胀系数大于将所述半导体器件(1)固定于其上的印刷电路板的热膨胀系数。
13、根据前述权利要求之一所述的半导体器件，其特征在于：
所述缓冲层是高度弹性的。
14、根据前述权利要求之一所述的半导体器件，其特征在于：
选择所述外壳(8)的材料，从而使所述外壳的热膨胀系数等于将所述半导体器件(1)固定在其上的印刷电路板的热膨胀系数。
15、根据前述权利要求之一所述的半导体器件，其特征在于：
选择所述外壳的材料(8)，从而使所述外壳的热膨胀系数大于所述半导体芯片的热膨胀系数。
16、根据前述权利要求之一所述的半导体器件，其特征在于：
选择所述缓冲层(7)和所述半导体芯片(3)的材料，从而使其在一起的热膨胀系数等于所述外壳(8)和/或将所述半导体器件(1)固定在其上的印刷电路板的热膨胀系数。
17、根据前述权利要求之一所述的半导体器件，其特征在于：
所述缓冲层(7)由聚合物或气体组成，尤其是硅树脂、聚亚安酯等。
18、根据权利要求17所述的半导体器件，其特征在于：
所述缓冲层(7)由发泡材料组成。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101488482B (zh) * 2008-01-18 2011-09-14 南茂科技股份有限公司 半导体封装结构及其制造方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3945483B2 (ja) 2004-01-27 2007-07-18 カシオ計算機株式会社 半導体装置の製造方法
DE102004043663B4 (de) * 2004-09-07 2006-06-08 Infineon Technologies Ag Halbleitersensorbauteil mit Hohlraumgehäuse und Sensorchip und Verfahren zur Herstellung eines Halbleitersensorbauteils mit Hohlraumgehäuse und Sensorchip
DE102006062473A1 (de) * 2006-12-28 2008-07-03 Qimonda Ag Halbleiterbauelement mit auf einem Substrat montiertem Chip
ITMI20070099A1 (it) * 2007-01-24 2008-07-25 St Microelectronics Srl Dispositivo elettronico comprendente dispositivi sensori differenziali mems e substrati bucati
JP2009049218A (ja) * 2007-08-21 2009-03-05 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
US7910404B2 (en) * 2008-09-05 2011-03-22 Infineon Technologies Ag Method of manufacturing a stacked die module
US20160064299A1 (en) * 2014-08-29 2016-03-03 Nishant Lakhera Structure and method to minimize warpage of packaged semiconductor devices
CN116888728A (zh) * 2021-04-29 2023-10-13 华为技术有限公司 电路板装配件和电子设备

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3105089B2 (ja) * 1992-09-11 2000-10-30 株式会社東芝 半導体装置
JP2570628B2 (ja) * 1994-09-21 1997-01-08 日本電気株式会社 半導体パッケージおよびその製造方法
US5783870A (en) * 1995-03-16 1998-07-21 National Semiconductor Corporation Method for connecting packages of a stacked ball grid array structure
JP3332308B2 (ja) * 1995-11-07 2002-10-07 新光電気工業株式会社 半導体装置及びその製造方法
US6667560B2 (en) * 1996-05-29 2003-12-23 Texas Instruments Incorporated Board on chip ball grid array
DE19649798A1 (de) * 1996-12-02 1998-06-04 Abb Research Ltd Leistungshalbleitermodul
JP3695893B2 (ja) * 1996-12-03 2005-09-14 沖電気工業株式会社 半導体装置とその製造方法および実装方法
KR100248792B1 (ko) * 1996-12-18 2000-03-15 김영환 단일층 세라믹 기판을 이용한 칩사이즈 패키지 반도체
KR100237328B1 (ko) * 1997-02-26 2000-01-15 김규현 반도체 패키지의 구조 및 제조방법
US6235471B1 (en) * 1997-04-04 2001-05-22 Caliper Technologies Corp. Closed-loop biochemical analyzers
US5881945A (en) * 1997-04-30 1999-03-16 International Business Machines Corporation Multi-layer solder seal band for semiconductor substrates and process
JP3335575B2 (ja) * 1997-06-06 2002-10-21 松下電器産業株式会社 半導体装置およびその製造方法
US6014316A (en) * 1997-06-13 2000-01-11 Irvine Sensors Corporation IC stack utilizing BGA contacts
US6150719A (en) * 1997-07-28 2000-11-21 General Electric Company Amorphous hydrogenated carbon hermetic structure and fabrication method
DE19803020C2 (de) * 1998-01-27 1999-12-02 Siemens Ag Chipkartenmodul für biometrische Sensoren
JP2000156435A (ja) * 1998-06-22 2000-06-06 Fujitsu Ltd 半導体装置及びその製造方法
JP3602000B2 (ja) * 1999-04-26 2004-12-15 沖電気工業株式会社 半導体装置および半導体モジュール
US6376769B1 (en) * 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
DE19931004C2 (de) * 1999-07-05 2002-02-07 Tyco Electronics Logistics Ag Chipmodul, insbesondere BGA-Package, mit einem Interconnect zur stressfreien Lötverbindung mit einer Leiterplatte
US6441476B1 (en) * 2000-10-18 2002-08-27 Seiko Epson Corporation Flexible tape carrier with external terminals formed on interposers
DE19954888C2 (de) * 1999-11-15 2002-01-10 Infineon Technologies Ag Verpackung für einen Halbleiterchip
US6384487B1 (en) * 1999-12-06 2002-05-07 Micron Technology, Inc. Bow resistant plastic semiconductor package and method of fabrication
JP4374691B2 (ja) * 2000-01-28 2009-12-02 凸版印刷株式会社 チップサイズ型半導体装置
JP2001237351A (ja) * 2000-02-22 2001-08-31 Hitachi Maxell Ltd 半導体装置
DE10016132A1 (de) * 2000-03-31 2001-10-18 Infineon Technologies Ag Elektronisches Bauelement mit flexiblen Kontaktierungsstellen und Verfahren zu dessen Herstellung
US6560117B2 (en) * 2000-06-28 2003-05-06 Micron Technology, Inc. Packaged microelectronic die assemblies and methods of manufacture
US6326700B1 (en) * 2000-08-15 2001-12-04 United Test Center, Inc. Low profile semiconductor package and process for making the same
JP2002083904A (ja) * 2000-09-06 2002-03-22 Sanyo Electric Co Ltd 半導体装置およびその製造方法
JP3640876B2 (ja) * 2000-09-19 2005-04-20 株式会社ルネサステクノロジ 半導体装置及び半導体装置の実装構造体
JP4183375B2 (ja) * 2000-10-04 2008-11-19 沖電気工業株式会社 半導体装置及びその製造方法
US6388322B1 (en) * 2001-01-17 2002-05-14 Aralight, Inc. Article comprising a mechanically compliant bump
DE10133361C2 (de) 2001-07-10 2003-05-28 Infineon Technologies Ag Verfahren zur Herstellung einer Verpackung für Halbleiterchips
DE10138278C1 (de) * 2001-08-10 2003-04-03 Infineon Technologies Ag Elektronisches Bauteil mit aufeinander gestapelten elektronischen Bauelementen und Verfahren zur Herstellung derselben
KR20030029743A (ko) * 2001-10-10 2003-04-16 삼성전자주식회사 플랙서블한 이중 배선기판을 이용한 적층 패키지
JP4085788B2 (ja) * 2002-08-30 2008-05-14 日本電気株式会社 半導体装置及びその製造方法、回路基板、電子機器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101488482B (zh) * 2008-01-18 2011-09-14 南茂科技股份有限公司 半导体封装结构及其制造方法

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US7274110B2 (en) 2007-09-25
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CN100565852C (zh) 2009-12-02
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DE50312399D1 (de) 2010-03-25

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