CN1689143A - Cmos栅的原子层沉积 - Google Patents

Cmos栅的原子层沉积 Download PDF

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CN1689143A
CN1689143A CNA03824408XA CN03824408A CN1689143A CN 1689143 A CN1689143 A CN 1689143A CN A03824408X A CNA03824408X A CN A03824408XA CN 03824408 A CN03824408 A CN 03824408A CN 1689143 A CN1689143 A CN 1689143A
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transistor
forming
metal conductor
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pmos
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CN100359640C (zh
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L·福尔贝斯
K·Y·阿恩
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Micron Technology Inc
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2

Abstract

本发明提供了一种用于晶体管的结构、系统和方法，所述晶体管具有通过原子层沉积形成的并具有可变功函的栅极。一个晶体管的实施方案包括第一源极/漏极区域；第二源极/漏极区域；位于它们之间的通道区域。栅极通过栅极绝缘体与所述通道区域分开。所述栅极包括通过原子层沉积形成的三元金属导体，以为所述三元金属导体提供被设计用于提供期望阈值电压的组成。

Description

CMOS栅的原子层沉积
技术领域
本发明通常涉及半导体集成电路，更加具体地说，涉及具有可变功函的CMOS栅的原子层沉积。
背景技术
CMOS技术中的传统n型掺杂多晶硅栅电极具有两个问题。首先，多晶硅是导电的，但可仍存在这样一个表面区域，其在偏压条件下能够耗损载体。这表现为额外的栅绝缘体厚度并且通常被称作栅极耗损和增加了等效氧化层厚度。虽然该区域是薄的，也就几个埃(Å)的等级，但当栅极氧化物厚度被降低至2nm或20Å以下时它是可感知的。另一个问题是功函对于n-MOS和p-MOS器件都不是最佳的，历史上该问题通过阈值电压调整注入来补偿。然而，随着器件变得越来越小，通道长度小于1000Å并因此使表面空间电荷区域小于100Å，所以越来越难于进行这些注入过程。阈值电压控制变成一个重要考虑因素，因为电源被减至1伏特的范围。PMOS和NMOS晶体管的最佳阈值电压需要具有约0.3伏特的幅值。
多晶硅栅极耗损问题的一个解决方案是用金属或高导电的金属氮化物代替半导电的栅极材料。关于任何新的电路材料，栅电极必须与晶体管和所述处理在化学和热学方面具有相容性。可利用不同的金属或者修改导电氮化物的属性来提供最佳功函。
栅电极的功函-提取电子所需的能量-必须与半导体材料的势垒高度一致。对于PMOS晶体管，所需的功函是约5.0eV。获得NMOS晶体管所需的较低功函即约4.1eV是更加困难的。图1A和1B分别表示NMOS和PMOS晶体管的期望能量带视图和功函。类似钛(Ti)和钽(Ta)的难熔金属在典型的工艺条件下快速氧化。对该问题提出的一个解决方案依赖“调谐的”钌-钽(Ru-Ta)合金，该合金在工艺条件下是稳定的。当Ta浓度低于20％时，该合金的电学性能类似铷(Ru)，一种良好的PMOS栅电极。当Ta浓度在40％-54％之间时，所述合金是良好的NMOS栅电极。
有希望的候选物包括金属氮化物，例如氮化钽(TaN)和氮化钛(TiN)。氮化钽、氮化钛和氮化钨是中间间隙(mid-gap)功函的金属导体，通常说明为用于CMOS器件。中间间隙功函的使用使得NMOS和PMOS器件的阈值电压对称，因为阈值电压的幅值将是相同的，但所述两个阈值电压将具有比最佳值高的幅值，所述最佳值具有低电源电压。
近来，物理沉积、蒸镀已经用于试验某些三元金属氮化物用作栅电极的适用性，这些三元金属氮化物包括TiAlN和TaSiN。然而，这些三元金属氮化物是通过物理沉积而不是原子层沉积方式沉积的，并且只有电容器结构被制造，而非具有栅极结构的晶体管。
因此，现在对于改进的CMOS晶体管设计有一种迫切需要。
参考书目
由Y.Yee-Chia等人在2001年5月出版的IEEE Electron DeviceLetters(卷22，5期，第227-229页)上发表的“Dual-metal gate CMOStechnology with ultrathin silicon nitride gate dielectric”；
L Qiang，Y.Yee Chia等人在2000年举办的2000讨论会的技术论文文摘VLSI技术(2000年)(72-73页)中发表的“Dual-metal gatetechnology for deep-submicron CMOS transistors”；
H.Wakabayashi等人在2001年10出版的IEEE学报ElectronDevices(卷48，10期)(2363-2369页)上发表的“A dual-metalgate CMOS technology using nitrogen-concentration-controlledTiNx film”；
H.Zhong等人在2001年于华盛顿召开的IEEE国际电子器件会议文摘(论文20.05)上发表的“Properties of Ru-Ta Alloys as gateelectrodes for NMOS and PMOS silicon devices”；
V.Misra，H.Zhong等人在2002年6月出版的IEEE ElectronDevice Letters(卷23，6期)(354-356页)上发表的“Electricalproperties of Ru-based alloy gate electrodes for dual metalgate Si-CMOS”；
H.Zhong等人在2000年12月出版的IEEE Electron DeviceLetters(卷21，12期)(593-595页)上发表的“Electricalproperties of Ru0/sub 2/gate electrodes for dual metal gateSi-CMOS”；
H.Shimada等人在2001年6月于日本Kyoto召开VLSI技术2001讨论会(67-68页)上发表的“Low resistivity bcc-Ta/TaN/subx/metal gate MNSFETs having plane gate structure featuringfully low temperature processing below 450 degrees C”；
H.Shimada等人在2001年8月的电子器件IEEE会报(卷48，第8节)(1619-26页)上发表的“Tantalum nitride metal gate FD-SOICMOS FETs using low resistivity self-grown bcc-tantalum，layer”；
B.Claflin等人在1998年4月13-15日于加利福尼亚(CA)旧金山召开的MRS Symposium on Silicon Front-End Technology-Materials Processing and Modelling(171-176页)上发表的“Investigation of growth and chemical stability of compositemetal gates on ultra-thin gate dielectrics”；
A.Yagishita等人在2000年12月于旧金山召开的DigestTechnical Papers Int.Electron Devices Meeting(663-6页)上发表的“Dynamic threshold voltage damascene metal gateMOSFET(DT-DMG-MOS)with low threshold voltage，high drivecurrent and uniform electrical characteristics”；
B.Claflin等人在1998年4月13-15日于加利福尼亚(CA)旧金山召开的MRS Symposium on Silicon Front-End Technology-Materials Processing and Modelling(171-176页)上发表的“Investigation of growth and chemical stability of compositemetal gates on ultra-thin gate dielectrics”；
M.Moriwaki等人在2000年出版的Jpn.J.Appl.Phys(卷39，第4B节)(2177-80页)上发表的“Improved metal gate process bysimultaneous gate-oxide nitridation during W/WN/sub x/gateformation”；
Dae-Gyu Park等人在2001年召开的Electron DevicesMeeting，2001 IEDM Technical Digest International(30.6.1-30.6.4页)上发表的“Robust ternary metal gate electrodes fordual gate CMOS devices”；
Ofer Sneh等人在Thin Solid Films，402(2002)248-261上发表的“Thin film atomic layer deposition equipment forsemiconductor processing”；
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Petra Alen等人在Jour，of the Electrochemical Society，148(10)，G566-G571(2001)上发表的“Atomic-Layer Deposition ofTa(Al)N(C)Thin Films Using Trimethylaluminum as a ReducingAgent”；
J.S.Min等人在1998年9月15日出版的Jpn.J.Appl.Phys(卷37，部分1，第9A节，4999-5004页)上发表的“Atomic-LayerDeposition of TiN Films by alternate supply on Tetrakis(ethylmethyllamino)-titanium and ammonia”；
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发明内容
上述提到的CMOS晶体管设计问题以及其它问题通过本发明来解决并且将通过阅读和研究下面的说明书来理解。该申请说明了三元金属导体的原子层沉积的应用，其中所述组成和功函都是变化的，以控制CMOS技术中的NMOS和PMOS晶体管的阈值电压，以便提供最佳性能。
更加具体的说，本发明的一个实施方案包括一晶体管，其具有：一源极区、一漏极区和一位于其间的通道。一栅极通过一栅极绝缘体与所述通道区域分开。所述栅极包括通过原子层沉积形成的三元金属导体。在一个实施方案中所述三元金属导体包括钽铝氮化物(TaAlN)。在一个实施方案中所述三元金属导体包括钛铝氮化物(TiAlN)。在一个实施方案中所述三元金属导体包括钛硅氮化物(TiSiN)。在一个实施方案中所述三元金属导体包括钨铝氮化物(WAlN)。在一些实施方案中，所述栅极进一步包括一在所述三元金属导体上形成的难熔金属。
本发明的这些和其它实施方案、方面、优点和特征将部分的在下述说明中阐释，并且一部分对于本领域技术人员来说通过参照本发明的下述说明和参考的附图或通过本发明的实践将变得显而易见。本发明的这些方面、优点和特征借助在后附权利要求中具体指出的手段、过程及其结合来实现和获得。
附图说明
图1A和1B分别表示NMOS和PMOS晶体管的期望能带视图和功函；
图2为描绘了在本发明的各种实施方案中使用的各种金属氮化物的电子亲和性和能带隙的关系的示图；
图3表示根据本发明的教导形成的晶体管结构的一个实施方案；
图4表示一存储器件的实施方案，其利用了通过根据本发明实施方案的原子层沉积形成的三元金属栅极；
图5为一电子系统或基于处理器的系统的方框图，其利用了通过根据本发明实施方案的原子层沉积形成的三元金属栅极。
具体实施方式
在下面对本发明所作的详细说明中，将参考形成其一部分的附图，并且在其中示意性的示出了本发明可被实践的特定实施方案。在附图中，相同的附图标记在几幅图中都表示基本相似的部件。对这些实施方案进行了充分详细的说明以使本领域技术人员能够实践本发明。在不脱离本发明范围的情况下，也可利用其他实施方案，并且可进行结构、逻辑和电子修改。
在下述说明中使用的术语晶片和衬底包括具有能够形成本发明的集成电路(IC)结构的暴露表面的任何结构。术语衬底被理解为包括半导体晶片。术语衬底也用于指处理期间的半导体结构，并且可包括已经在其上制造的其它层。晶片和衬底都包括掺杂和未掺杂的半导体、由基础半导体或绝缘体支撑的取向附生的半导体层、以及本领域技术人员公知的其它半导体结构。术语导体被理解为包括半导体，术语绝缘体被定义为包括导电性比称作导体的材料弱的任何材料。因此，下面的详细说明并不受到局限，本发明的范围仅由所附权利要求以及该权利要求所授权的全部等价范围定义。
本公开描述了三元金属导体的原子层沉积的应用，其中所述组成是变化的且功函也是变化的，参见图2，以控制CMOS技术中的NMOS和PMOS晶体管的阈值电压，以便提供最佳性能。在若干个实施方案中，这些应用包括使用TaAlN、TiAlN、TiSiN和WAlN作为三元金属导体。传统的高掺杂多晶硅或如W、Ta、Ti的难熔金属被沉积在金属导体上以给出图3中所示的栅极结构。如图3所示，晶体管301结构包括一源极区302、漏极区304和位于它们之间的通道306。栅极310通过一栅绝缘体308与所述通道区域分离开。根据本发明的教导，栅极310包括通过原子层沉积形成的三元金属导体。在一个实施方案中，所述三元金属导体包括钽铝氮化物(TaAlN)。在一个实施方案中，所述三元金属导体包括钛铝氮化物(TiAlN)。在一个实施方案中，所述三元金属导体包括钛硅氮化物(TiSiN)。在一个实施方案中，所述三元金属导体包括钨铝氮化物(WAlN)。如图3所示，在一些实施方案中，所述栅极进一步包括一层高导电多晶硅312，或可选择的包括一难熔金属层312，其形成在三元金属导体310上。在具有难熔金属层的实施方案中，层312例如包括但不局限于类似钽、钛和钨的难熔金属。
形成方法
在70年代早期开发的原子层沉积为CVD变体，并且还可被称作“可选择脉冲-CVD”。在该技术中，一次对衬底表面引入一种气体前体，并且在脉冲之间，反应器以惰性气体清洗或抽空。在该第一反应步骤，所述前体被饱和的化学吸收在衬底表面处，并且在随后的清洗期间，将前体从反应器中除去。在第二步骤，在所述衬底上引入其它前体，并且进行期望的薄膜生长反应。此后从反应器中清洗出反应副产品和剩余前体。当前体化学是有益的时，即当前体彼此迅速吸收和反应时，可在适当设计的流动型反应器中在少于一秒的时间执行一个ALD周期。
ALD的令人惊叹的特征是所有该反应和清洗步骤的饱和，这使得生长自我限制，从而获得大面积的均匀性和一致性，这是ALD的最重要的性质，如在各种极其不同的情况，即平板衬底、深沟槽，以及多孔硅和大表面积氧化硅和氧化铝的极端情况所示。此外，对薄膜厚度的控制是简单直截的，并且能通过简单地计算生长周期来进行。ALD最初开发用以制造光电显示器中所需要的发光和介电薄膜，并且已经将许多努力放在了掺杂硫化锌和碱土金属硫化物薄膜的生长上。以后研究了ALD用于不同取向附生II-V和II-VI薄膜的生长，非取向附生晶体或非晶体氧化物和氮化物薄膜是它们的多层结构。
对于硅和锗薄膜的ALD生长已经引起了相当大的兴趣，但由于前体化学的难度，其结果一直以来不是很成功。
反应序列ALD(RS-ALD)薄膜具有若干个独特和无与伦比的优点：
·界面处的连续性，能够避免成核区域边界不清晰，这样的区域对CVD(＜20Å)和PVD(＜50Å)膜而言是典型现象。为了获得该连续性，必须激发衬底表面使其与首次暴露的RS-ALD前体直接反应。
·通过更粗旷的方法在最粗糙的衬底形貌上获得了无与伦比的一致性，这种一致性只能通过逐层沉积获得。
·典型的，低温和轻微的氧化处理。这被认为是制备栅极绝缘体的主要优点，其中主要关心的是在无需氧化衬底的情况下(使用氧化前体)沉积非硅基的电介质。
·RS-ALD具有制备多层叠层膜，可能降到单层分辨率，以及看起来独一无二的合金复合薄膜的能力。该能力是能够用单层精度控制沉积和沉积连续的单层非结晶膜的能力相结合的结果(这是RS-ALD所独有的)。
·空前粗旷的方法。RS-ALD方法没有第一晶片影响性和腔室依赖性。因此，RS-ALD方法将能够较容易的从研发转移至生产并且能从200发展至300毫米的晶片尺寸。
·厚度仅取决于周期数。厚度可以作为简单处方变化而“拨入(dialed-in)”，无需随着技术更新的进步而对方法有另外的发展。
氮化物的原子层沉积
Ta-N：已经说明了使用作为叔丁基酰亚胺基三(二乙基氨基)钽的还原剂的氢自由基在260℃沉积温度下进行的氮化钽(Ta-N)薄膜的等离子体增强原子层沉积(PEALD)。PEALD产生了高级Ta-N膜，其具有400μΩcm的电阻率，并且在暴露于空气的情况下没有老化效应。该薄膜密度高于通过典型的ALD形成的Ta-N膜的密度，典型ALD中使用NH3而不是氢自由基。另外，沉积后的薄膜不是无定形的，而是多晶体结构的腕尺TaN。薄膜的密度和结晶度随着氢等离子体的脉冲时间而增加。该薄膜组成上富含Ta，并且包括约15原子％的碳杂质。在PEALD制备的Ta-N薄膜中，氢自由基代替NH3作为还原剂，NH3在典型的Ta-NALD中被用作反应气体。薄膜在冷壁反应器中使用(Net2)3Ta＝Nbut[叔丁基酰亚胺基三(二乙酰胺基)钽，TBTDET]作为Ta的前体以260℃的沉积温度和133Pa的沉积压力沉积在SiO2(100nm)/Si晶片上。液体前体被包含在以70℃加热的起泡器中并由35sccm的氩承载。一个沉积周期由以下组成：暴露至TBTDET的金属有机前体中、用Ar清洗的周期，和暴露至氢等离子体，其后是用Ar进行的另一个清洗周期。不是在每种反应气体脉冲之间而是进行15秒的Ar清洗周期将反应气体彼此分开。为了引燃和保持与沉积周期同步的氢等离子体，在上和下电极之间施加矩形的电压。用于使反应气体在反应器中均匀分布的莲蓬头被用作上电极，所述莲蓬头与以100W功率操作的rf(13.56MHz)等离子源进行电容性耦合。晶片驻留其上的下电极被接地。通过场发射扫描电子显微镜法分析薄膜厚度和形态学。
Ta(Al)N(C)：已经使用TaCl5或TaBr5和NH3作为前体和Al(CH3)3作为附加的还原剂研究了薄膜的技术工作。沉积温度在250-400℃之间变化。该薄膜包括铝、碳和氯杂质。随着沉积温度的增加，氯含量显著减少。在400℃沉积的薄膜包含少于4原子％的氯，并且还具有最低的电阻率，1300μΩcm。使用了按照脉冲顺序TaCl5-TMA-NH3，TMA-TaCl5-NH3，TaBr5-NH3，TaBr5-Zn-NH3，和TaBr5-TMA-NH3的五种不同的沉积处理方法。从保持在反应器内部的敞舟皿蒸镀TaCl5，TaBr5和Zn。TaCl4，TaBr5和Zn的蒸镀温度分别是90、140、380℃。通过一质量流量计、一针形阀和一电磁阀向反应器中引入氨。在连续流动中将流速调至14sccm。TMA被保持在16℃的恒定温度下并且通过针形阀和电磁阀脉动。脉动时间对于TaCl5，TaBr5NH3和Zn来说为0.5s，但TMA的脉冲长度在0.2至0.8s之间变化。清洗脉冲的长度总是0.3s。氮气被用于传输前体和作为清洗气体。氮气的流速是400sccm。
TiN：通过交替提供反应源Ti[N(C2H5CH3)2]4[四(乙基甲基氨基)钽，TEMAT]和NH3已经在170℃和210℃之间在SiO2上通过原子层沉积(ALD)制备了非结晶TiN膜。这些反应物源以下面的顺序注入到反应器中：TEMAT蒸汽脉冲、Ar气体脉冲、NH3气体脉冲和Ar气体脉冲。当在200℃并且反应物源有充足脉冲时间时，每周期薄膜厚度的饱和值是大约每周期1.6单层。其结果表明每个周期的薄膜厚度在ALD中可超过1ML/周期，并且通过反应物源的再化学吸收机制对其进行说明。周期数量和薄膜厚度之间的理想线性关系被确定。
TiAlN：Koo等人发表了关于通过原子层沉积方法沉积的TiAlN薄膜的特性研究的论文。该系列的金属-Si-N阻挡层具有1000μΩcm以上的高电阻率。他们提出了TiAlN的另一种三元扩散阻挡层。虽然Al含量相当大，但TiAlN薄膜还是呈现为NaCl结构。分别使用TiCl4和二甲基铝氢化物乙基哌啶(DMAH-EPP)作为钛前体和铝前体来沉积TiAlN膜。在13-15℃下从液体蒸发TiAl4并将其引入ALD腔，其使用Ar载体气体以30sccm的流速通过起泡器来提供。在60℃下蒸镀DMAH-EPP前体并使用与TiCl4相同的流速将其引入ALD腔。NH3气体也被用作反应气体并且其流速约为60sccm。引入Ar清洗气体以完全分离反应物源和反应气体。在350至400℃的温度下沉积TiAlN膜并且将总压力保持恒为两托。
TiSiN：金属有机原子层沉积(MOALD)获得了近乎完美的逐层覆盖(stepcoverage step)并精确地控制生长的薄膜的厚度和组成。对于使用连续提供的Ti[N(CH3)2]4[四(二甲基酰胺基)钛：TDMAT]硅烷(SiH4)和氨(NH3)的三元Ti-Si-N膜的MOALD技术已经研发了出来，并用高频C-V测量法评估10nmTi-Si-N薄膜的Cu扩散阻挡层特性。在180℃的沉积温度下，按照TDMAT脉冲、硅烷脉冲和氨脉冲的顺序单独提供硅烷。沉积膜的硅含量和每周期的沉积厚度保持几乎恒定为在18原子％和0.22nm/周期，即使硅烷分压从0.27变化到13.3Pa。尤其是，Si含量的依赖性与传统的化学气相沉积显著不同。甚至在具有略微负斜率和10∶1纵横比的0.3μm直径的孔中，逐层覆盖近似100％。
WN：使用连续表面反应进行原子层控制已经沉积了氮化钨薄膜。氮化钨薄膜生长是通过将二元反应 分成两个半反应实现的。按照ABAB……顺序连续施加WF6和NH3半反应，在600至800K的衬底温度下产生氮化钨沉积。透射傅立叶变换红外线(FTIR)光谱在WF6和NH3半反应期间监控WFX *和NHY *表面物质在高表面积粒子上的覆盖情况。FTIR光谱结果证实WF6和NH3半反应在＞600K的温度下是完整的和自限的。原位分光镜椭圆光度法监控在Si(100)衬底上的薄膜生长和温度和反应剂暴露量的关系。在600-800K下分别对于WF6和NH3反应物暴露量＞3000L和10000L测量氮化钨沉积速度为2.55Å/AB周期。X射线光电子能谱深度分布试验确定所述薄膜具有低C和O杂质浓度的W2N化学计量关系。X射线衍射试验揭示氮化钨膜是微晶的。对沉积膜进行原子力显微镜分析观察到表示平滑薄膜生长的异常平坦表面。以原子层控制沉积的这些平滑氮化钨薄膜将用作接触和通过孔的Cu的扩散控制。
AlN：已经通过原子层化学气相沉积(ALCVD)从三甲基铝(TMA)和氨前体在多孔硅石上生长了氮化铝(AlN)。ALCVD生长是基于气体前体与固体衬底的交替的、分开的、饱和的反应来进行的。TMA和氨在硅石上分别在423和623开氏温度(K)下进行反应，硅石已经通过用823K下的氨进行预处理而在1023K下进行了脱羟基。在三个反应周期中的生长通过元素分析而被定量的分析，并且表面反应产物由IR和固态及Si NMR分析法进行辨别。获得了约2铝原子/nm2硅/反应周期的稳定生长。所述生长主要通过下列反应进行：(I)在表面Al-Me和Si-Me基中得到的TMA的反应，和(II)用氨基取代铝键合甲基的氨反应。氨还与在TMA与硅氧烷桥的独立反应中形成的硅键合甲基进行部分反应。TMA与氨基反应，就象它与表面硅烷醇基和硅氧烷桥反应一样。通常，Al-N层与硅衬底的相互作用强烈，但在第三反应周期中，可形成AlN型位点(site)。
器件
在图4中示出了根据本发明教导的存储器件。存储器件440包含存储器阵列442、行和列解码器444、448和感测放大电路446。存储器阵列442由多个晶体管单元400构成，这些单元具有通过原子层沉积形成的金属栅极，其字线480和位线460通常被分别布置为行和列。存储器阵列442的位线460与感测放大电路446连接，而其字线480与行解码器444连接。地址和控制信号在地址/控制线461上被输入到存储器件440中，并被连接至列解码器448、感测放大电路446和行解码器444，并被用于获得，在其它事件中例如对存储器阵列442的读和写访问。
列解码器448通过列选择线462上的控制和列选择信号而被连接至感测放大电路446。感测放大电路446借助于输入/输出(I/O)数据线463接收去往存储器阵列442的输入数据并输出从存储器阵列442读取的数据。通过激发字线480(借助于行解码器444)从存储器阵列442的单元读取数据，所述字线将与该字线相应的所有存储器单元耦合至各自的位线460，所述位线定义了阵列的列。还激发一个或多个位线460。当特定的字线480和位线460被激发时，与位线列连接的感测放大电路446检测并放大通过给定晶体管单元感测的并通过测量激发位线460和参考位线之间的势差而传送至其位线460的传导信号，所述参考线可以是未激发位线。此外，在读操作中，给定单元的源极区域被耦合至接地源极线或阵列板(未示)。存储器件感测放大器的操作在例如美国专利第5627785、5280205和5042011号中进行了描述；所有这些专利都被转让给Micron Technology Inc(Micron技术有限公司)。
图5为利用具有通过根据本发明教导的原子层沉积形成的三元金属栅极的晶体管单元的电子系统或基于处理器的系统500的方框图。例如，借助例子而非限制，根据本发明来构造存储器512以使晶体管单元具有通过原子层沉积形成的三元金属栅极。然而，本发明并不受限制，本发明可同样应用于CPU等中的晶体管。基于处理器的系统500可以是计算机系统，处理控制系统或任何其他利用处理器和相关存储器的系统。系统500包括一中央处理单元(CPU)502，例如，微处理器，其通过总线520与存储器512和I/O装置508通信。必须注意总线520可以是通常用在基于处理器的系统中的一系列总线和电桥，但是仅为了方便的目的，图中将总线520表示为单一总线。还示出了第二I/O装置510，但其并非为实践本发明所必需的。基于处理器的系统500还可以包括只读存储器(ROM)514，并且可包括外围设备，例如软盘驱动器504和光盘(CD)ROM驱动器506，它们也通过总线520与CPU502通信，这一点在现有技术中是公知的。
本领域技术人员应该意识到，附加的电路和控制信号可被提供，并且基于处理器的系统500被简化了以集中说明本发明。
应该理解，图5中所示的实施方案示出了电子系统电路的一个实施方案，其中使用了通过原子层沉积形成的新颖三元金属栅极晶体管单元。对如图5中所示的系统500的说明用于对本发明的结构和电路的一个应用提供一种通常的理解，而非用于完整说明使用通过原子层沉积形成的新颖三元金属栅极晶体管单元的电子系统的所有元件和特征。此外，本发明可同等的应用于使用通过原子层沉积形成的新颖三元金属栅极晶体管单元的任何尺寸和类型的系统500，并且本发明不想限制于上述的说明。如本领域技术人员将理解的，这样的电子系统可以以单一封装处理单元制造，甚或制造在单一的半导体芯片上，以便减少处理器和存储器件之间的通信时间。
包括如在本申请中所述的通过原子层沉积形成的新颖三元金属栅极晶体管单元的应用系统，包括用于存储器模块、器件驱动器、电源模块、通信调制解调器、处理器模块和特定应用的模块的电子系统，并且可以包括多层、多芯片模块。这种电路可进一步是各种电子系统的子部件，所述电子部件例如时钟、电视、蜂窝电话、个人计算机、汽车、工控系统、飞行器和其它系统。
结论
本申请说明了原子层沉积的三元金属导体作为晶体管栅极的应用。所述组成是变化的并且功函也是变化的，以控制CMOS技术中的NMOS和PMOS晶体管的阈值电压，以便提供最佳性能。
应该理解上述说明仅仅是示意性的，并非限制性的。许多其它实施方案对于阅读了上述说明的本领域技术人员来说将是显而易见的。因此，本发明的范围应该参照后附权利要求连同这种权利要求所授权的全部等价范围进行确定。

Claims (33)

1.一种晶体管，包括：
第一源极/漏极区域；
第二源极/漏极区域；
位于所述第一和第二源极/漏极区域之间的通道区域；
通过栅极绝缘体与所述通道区域分开的栅极，其中所述栅极包括通过原子层沉积形成的三元金属导体，以提供组成被设计用于提供期望阈值电压的三元金属导体。
2.根据权利要求1所述的晶体管，其中所述三元金属导体包括钽铝氮化物(TaAlN)。
3.根据权利要求1所述的晶体管，其中所述三元金属导体包括钛铝氮化物(TiAlN)。
4.根据权利要求1所述的晶体管，其中所述三元金属导体包括钛硅氮化物(TiSiN)。
5.根据权利要求1所述的晶体管，其中所述三元金属导体包括钨铝氮化物(WAlN)。
6.根据前述任何一项权利要求所述的晶体管，其中所述栅极进一步包括在所述三元金属导体上形成的导电多晶硅层。
7.根据前述任何一项权利要求所述的晶体管，其中所述栅极进一步包括在所述三元金属导体上形成的难熔金属。
8.根据权利要求7所述的晶体管，其中所述难熔金属包括钨(W)。
9.根据权利要求7所述的晶体管，其中所述难熔金属包括钽(Ta)。
10.根据权利要求7所述的晶体管，其中所述难熔金属包括钛(Ti)。
11.一种存储器单元，包括前述任何一项权利要求的晶体管，并进一步包含耦合至所述源极区域的源极线和耦合至所述漏极区域的传输线。
12.一种存储器阵列，包括多个根据前述任何一项权利要求所述的晶体管，所述晶体管阵列包括：
形成在衬底上的多个单元，其中每个单元包括所述多个晶体管中的至少一个；
多个位线，它们沿所述晶体管阵列的行耦合至每个晶体管的漏极区域；和
多个字线，它们沿所述存储器阵列的列耦合至每个晶体管的栅极。
13.一种包括根据权利要求12所述的存储器阵列的半导体器件，包括：
耦合至所述多个字线的字线地址解码器；
耦合至所述多个位线的位线地址解码器；
耦合至所述多个位线的感测放大器。
14.一种包括根据权利要求12所述的存储器阵列的电子系统，包括：
处理器；和
耦合至所述处理器的存储器件，其中所述存储器件包括所述存储器阵列。
15.一种包括PMOS晶体管和NMOS晶体管的CMOS器件，其中：
所述PMOS晶体管和NMOS晶体管中的至少一个包括根据权利要求1-10中的任何一项所述的晶体管；
所述PMOS晶体管和NMOS晶体管每个都包括源极、漏极、位于其间的通道区域，通过栅极绝缘体与所述通道区域分开的栅极；和
所述PMOS晶体管和NMOS晶体管的栅极包括变化的组成和变化的功函，以便获得近似相等幅值的低阈值电压。
16.根据权利要求15所述的CMOS器件，其中所述近似相等幅值的阈值电压包括低于0.4伏特的阈值电压幅值。
17.根据权利要求15所述的CMOS器件，其中所述近似相等幅值的阈值电压包括大约为0.3伏特的阈值电压幅值。
18.根据权利要求15所述的CMOS器件，其中所述PMOS晶体管和NMOS晶体管的栅极中的一个包括二元金属导体，而另一个包括所述三元金属导体。
19.根据权利要求18所述的CMOS器件，其中所述二元金属导体包括选自氮化钽(TaN)、氮化钛(TiN)和氮化钨(WN)的二元金属导体。
20.一种包括PMOS晶体管和NMOS晶体管的CMOS器件，其中：
所述PMOS晶体管和NMOS晶体管每个都包括源极、漏极、位于其间的通道区域，通过一栅极绝缘体与所述通道区域分开的栅极；和
所述PMOS晶体管和NMOS晶体管中的至少一个包括根据权利要求1所述的晶体管；其中所述PMOS晶体管和NMOS晶体管的栅极中的一个包括钽铝氮化物(TaAlN)作为三元金属导体，且所述PMOS晶体管和NMOS晶体管的栅极中的另一个包括二元金属导体，其包括氮化钽(TaN)，以便获得近似相等幅值的低阈值电压。
21.一种包括PMOS晶体管和NMOS晶体管的CMOS器件，其中：
所述PMOS晶体管和NMOS晶体管每个都包括源极、漏极、位于其间的通道区域，通过栅极绝缘体与所述通道区域分开的栅极；和
所述PMOS晶体管和NMOS晶体管中的至少一个包括根据权利要求1所述的晶体管；其中所述PMOS晶体管和NMOS晶体管的栅极中的一个包括钛铝氮化物(TiAlN)作为三元金属导体，且所述PMOS晶体管和NMOS晶体管的栅极中的另一个包括二元金属导体，其包括氮化钛(TiN)，以便获得近似相等幅值的低阈值电压。
22.一种包括PMOS晶体管和NMOS晶体管的CMOS器件，其中：
所述PMOS晶体管和NMOS晶体管每个都包括源极、漏极、位于其间的通道区域，通过栅极绝缘体与所述通道区域分开的栅极；和
所述PMOS晶体管和NMOS晶体管中的至少一个包括根据权利要求1所述的晶体管；其中所述PMOS晶体管和NMOS晶体管的栅极中的一个包括钨铝氮化物(WAlN)作为三元金属导体，且所述PMOS晶体管和NMOS晶体管的栅极中的另一个包括二元金属导体，其包括氮化钨(WN)，以便获得近似相等幅值的低阈值电压。
23.一种形成晶体管的方法，包括：
在衬底上形成第一源极/漏极区域、第二源极/漏极区域，和介于它们之间的通道区域；
形成与所述通道区域相对并通过第一栅极绝缘体与其分开的栅极；和
其中形成栅极的步骤包括通过原子层沉积形成三元金属导体，以便提供设计用于提供期望阈值所需的组成。
24.根据权利要求23所述的方法，其中通过原子层沉积形成三元金属导体的步骤包括形成钽铝氮化物(TaAlN)层。
25.根据权利要求23所述的方法，其中通过原子层沉积形成三元金属导体的步骤包括形成钛铝氮化物(TiAlN)层。
26.根据权利要求23所述的方法，其中通过原子层沉积形成三元金属导体的步骤包括形成钛硅氮化物(TiSiN)层。
27.根据权利要求23所述的方法，其中通过原子层沉积形成三元金属导体的步骤包括形成钨铝氮化物(WAlN)层。
28.根据权利要求23-27中的任何一项所述的方法，其中形成栅极的步骤进一步包括在所述金属导体上形成难熔金属。
29.根据权利要求23-27中的任何一项所述的方法，其中形成栅极的步骤进一步包括形成在所述三元金属导体上形成的导电多晶硅层。
30.一种形成CMOS器件的方法，包括：
形成PMOS晶体管；
形成NMOS晶体管；
其中形成所述NMOS晶体管和PMOS晶体管中的至少一个包括根据权利要求23-29中的任何一项所述形成晶体管，和
其中形成所述NMOS晶体管和PMOS晶体管的步骤包括在每个各自的晶体管上形成变化的栅极组成，其具有变化的功函，以便将每个各自的晶体管的阈值电压控制为近似相等的幅值。
31.一种形成CMOS器件的方法，包括：
形成PMOS晶体管；
形成NMOS晶体管；
其中形成所述NMOS晶体管和PMOS晶体管中的一个的步骤包括根据权利要求24所述形成晶体管，和形成所述NMOS晶体管和PMOS晶体管中的另一个的步骤包括通过原子层沉积形成具有二元金属导体的晶体管栅极，所述二元金属导体包括氮化钽(TaN)层，使得所述NMOS晶体管和PMOS晶体管具有近似相等幅值的阈值电压。
32.一种形成CMOS器件的方法，包括：
形成PMOS晶体管；
形成NMOS晶体管；
其中形成所述NMOS晶体管和PMOS晶体管中的一个的步骤包括根据权利要求25所述形成晶体管，和形成所述NMOS晶体管和PMOS晶体管中的另一个的步骤包括通过原子层沉积形成具有二元金属导体的晶体管栅极，所述二元金属导体包括氮化钛(TiN)层，使得所述NMOS晶体管和PMOS晶体管具有近似相等幅值的阈值电压。
33.一种形成CMOS器件的方法，包括：
形成PMOS晶体管；
形成NMOS晶体管；
其中形成所述NMOS晶体管和PMOS晶体管中的一个的步骤包括根据权利要求26所述形成晶体管，和形成所述NMOS晶体管和PMOS晶体管中的另一个的步骤包括通过原子层沉积形成具有二元金属导体的晶体管栅极，所述二元金属导体包括氮化钨(WN)层，使得所述NMOS晶体管和PMOS晶体管具有近似相等幅值的阈值电压。
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US20040140513A1 (en) 2004-07-22
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US20050032342A1 (en) 2005-02-10
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US20050179097A1 (en) 2005-08-18
JP2005536877A (ja) 2005-12-02
AU2003260042A1 (en) 2004-03-11
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