CN1722430A - 电路模块以及电路模块的制造方法 - Google Patents

电路模块以及电路模块的制造方法 Download PDF

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CN1722430A
CN1722430A CNA200510076316XA CN200510076316A CN1722430A CN 1722430 A CN1722430 A CN 1722430A CN A200510076316X A CNA200510076316X A CN A200510076316XA CN 200510076316 A CN200510076316 A CN 200510076316A CN 1722430 A CN1722430 A CN 1722430A
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built
thin slice
circuit module
wiring pattern
circuit
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CN100420018C (zh
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樱井大辅
西川和宏
塚原法人
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

在各种移动机器、IC卡或存储卡等中使用的电路模块必须薄型化、层叠化。与此相伴的制造方法存在复杂化以及因层间剥离导致的可靠性低的问题。本发明提供一种具有层叠结构的电路模块及其制造方法,其形成将半导体芯片及无源器件埋置于由热可塑性树脂形成的薄片内的器件内置薄片,沿电路区块的边界对含有在表面形成有布线图案的多个电路区块的模块薄片折叠后层叠,通过加热和加压,熔融为一体化。这样,采用简单的制造方法就可以制作可靠性高的电路模块。

Description

电路模块以及电路模块的制造方法
技术领域
本发明涉及一种电路模块及其制造方法,该电路模块内置有电子器件,且叠合层叠形成有布线图案的薄片,其间相互布线。
背景技术
移动机器的多功能化及其轻薄小巧化不断地发展。同时,在安装电路基板及电子器件的电路模块中,追求更高的密度和性能。伴随着IC卡、存储卡的普及,薄的、高性能的、高可靠性且便宜的柔性电路模块的需求增大。
在特开2002-43513号公报中,公开了如图11所示的层叠结构的半导体装置及其制造方法。也就是说,如图11所示,将多个半导体芯片1010和器件1020安装在设有布线图案的支撑体1030上。此后,通过绝缘树脂1040模塑。另外,以区域单位将其折弯并重叠3层后,整体用绝缘树脂1050再次模塑。藉此得到层叠结构的半导体装置。
在这种情况下,为了使半导体芯片1010和器件1020的位置关系保持固定直到最终状态,支撑体1030有必要具有一定的刚性。因此,该结构的模块的薄型化有一定限度。
特开平2-239695号公报公开了具有同样层叠结构的多层印刷布线板。最初,形成在柔性薄片上形成有必要的布线图案及电极焊盘的可折弯的双面柔性基板。将这样的柔性基板在适当位置折叠。然后,用焊锡或导电性粘结剂将重叠的导体露出部位之间粘结,形成多层结构。藉此得到多层印刷布线板。然而,在该方法中,在布线板中没有内置电子器件,因此很难制造高性能的电子电路。
另外,美国专利第6225688号说明书中,公开了在薄膜基板上以面朝下方式安装电子器件,通过将其折弯形成多层化的安装结构。
另外,专利2001-93934号公报公开了以下半导体元件的安装方法。
另外,在半导体元件上通过导线焊接法形成凸块(bump)。将该半导体元件以凸块露出的方式埋置在热可塑性树脂中。接着,在包含凸块的热可塑性树脂的表面形成布线图案。其后,再用热可塑性树脂模塑。虽然公开了依据这样的方法的半导体元件的安装方法,但没有公开多层化结构。
各种移动机器、IC卡或存储卡等,在形成双面布线图案的柔性薄片薄片上安装半导体芯片和器件所构成的电路模块被广泛使用。为增大安装密度,也正在开发将安装有半导体芯片和器件的基板进一步层叠所构成的电路模块。
然而,在IC卡或存储卡等中,不仅要提高安装密度和可靠性,也要使产品形状标准化。为此,就要求在所规定的形状中实现高功能化。
最近,伴随着移动机器、IC卡或存储卡的发展,电路规模(例如,记忆容量等)正在变大。为满足这一需要,在上述现有例子中,将安装有电子器件的柔性薄片折弯,通过粘结层层叠,而实现多层基板和电路模块。通过这样的多层化,可以加大电路规模。可是,由于粘结剂和柔性薄片的材质不同,它们的热膨胀系数也不同。结果容易产生热膨胀系数的差异产生的应力所导致的层间剥离。为此,为防止可靠性降低,就有必要使基板具有一定的厚度,在要求厚度有限的IC卡中,就很难通过层叠来扩大电路的规模。
发明内容
为解决上述问题,本发明的目的在于提供一种在柔性薄片内埋置半导体芯片及器件,在给定位置折弯叠合,通过加热以及加压处理而熔接的一体化电路模块及其制造方法。
本发明的电路模块,通过叠合埋置有电子器件的器件内置薄片而进行层叠化,其具有以下结构:包括:器件内置薄片,其具有以至少让电子器件的凸起状电极表面露出的方式埋入了该电子器件的多个电路区块;布线图案,其与器件内置薄片的凸起状电极连接;覆盖薄片,其覆盖布线图案;沿电路区块的边界折叠并层叠电路区块,使器件内置薄片以及覆盖薄片熔接,成为一体化。
另外,本发明的电路模块的制造方法,包括:形成器件内置薄片的工序,该器件内置薄片具有以至少让电子器件的凸起状电极表面露出的方式埋入了该电子器件的多个电路区块;形成布线图案的工序,该布线图案与器件内置薄片的凸起状电极连接;由覆盖薄片覆盖布线图案的工序;通过在电路区块的边界折叠器件内置薄片而进行层叠的工序;和对层叠后的器件内置薄片和覆盖薄片热压,使其相互熔接而一体化的工序。
另外,本发明的电路模块的制造方法,包括:形成器件内置薄片的工序,该器件内置薄片具有以至少让电子器件的凸起状电极表面露出的方式埋入了该电子器件的多个电路区块;形成布线图案的工序,该布线图案与器件内置薄片的凸起状电极连接;由覆盖薄片层叠埋入了电子器件的布线图案的工序;通过在电路区块的边界折叠器件内置薄片而进行层叠的工序;和对层叠后的器件内置薄片和覆盖薄片热压,使其相互熔接而一体化的工序。
附图说明
图1表示有关本发明第一实施例的电路模块的剖面图;
图2表示说明同一实施例电路模块的制造方法的流程图;
图3表示图2的主要处理工序和工序结束后的剖面图;
图4表示同一实施例的电路模块中有关另一变形例的电路模块的剖面图;
图5表示同一实施例的电路模块中有关另一变形例的模块薄片的剖面图;
图6表示有关本发明第二实施例的电路模块的剖面图;
图7表示同一实施例的电路模块制造方法的主要处理工序和工序结束后主要部位的剖面图;
图8表示有关本发明第三实施例的电路模块的剖面图;
图9表示说明同一实施例电路模块制造方法的流程图;
图10表示图9所示的主要处理工序和工序结束后的剖面图;
图11表示有关现有技术的电路模块的剖面图。
具体实施方式
以下,参照附图说明本发明的实施例。
第一实施例
图1表示有关本发明第一实施例的电路模块的剖面图。
图1的电路模块具有如下结构:将由半导体芯片100和无源器件110等构成的电子器件埋设于各层的器件内置薄片120中,并且层叠为形成有布线图案130的4层。在各半导体芯片100的电极(图中未示出)形成有凸块140。另外,各无源器件110上也设有凸起状的电极150。另外,在以下,虽然为了与无源器件110的凸起状电极150相区别,而将在半导体芯片100上形成的凸起状电极特别作为凸块140进行说明,但它们的功能相同。
另外,器件内置薄片120的折叠部分190处也形成布线图案130,与形成于各层的半导体芯片100的凸块140之间或者无源器件110的凸起状电极150之间实现电连接。于是,使根据需要在覆盖薄片上层叠的4层器件内置薄片120互相热熔接为一体化,其熔接的边界面消失,形成半导体芯片100和无源器件110完全埋入的结构。另外,以下的说明为了有助于理解,将在布线图案130一侧形成的覆盖薄片记为第一覆盖薄片,将在布线图案130的形成面以外形成的覆盖薄片记为第二覆盖薄片,以示区别。
图1中,虽然为在折叠部分190留置有细支撑杆160的状态,也可以在一体化后将其取除。该支撑杆160旨在防止折弯工序中布线图案130的断线,即使取除也不会对电路模块的工作产生任何问题。
图2表示说明本实施例的电路模块制造工序的流程图。图3A至图3C表示图2的主要处理工序和工序结束后的主要部位的剖面图。
以下,结合图2至图3C说明本发明的电路模块的制造方法。
首先,在步骤S1中,准备研磨成薄片状且在电极(图中未示出)上用诸如导线焊接法形成有凸块140的半导体芯片100。同样,准备形成有凸起状电极150的无源器件110。例如,半导体芯片100和无源器件110的厚度分别为50μm。凸块140和凸起状电极150的高度通过研磨或者按压优选统一为大约25μm的程度,但并不限定于此。另外,凸块140也可以通过镀金、导电性浆料或焊锡等形成。
接下来,在步骤S2中,在热可塑性树脂形成的诸如75μm厚的薄片上在给定位置并且在每个给定电路区块300上载置一个或多个形成有凸块140的半导体芯片100以及形成有凸起状电极150的无源器件110。热塑性树脂可以用聚乙烯对苯二酸盐(PETG)、氯化乙烯、聚碳酸脂、或丁晴苯乙烯。另外薄片也可以用诸如环氧树脂等热硬化性树脂,或诸如聚铣亚胺等热可塑性树脂和热硬化性树脂混合的树脂。
接下来,在步骤S3中,将载置有半导体芯片100和无源器件110的薄片夹在热压板中间,加热同时加压。例如,对于PETG,压力为30kg/cm2,温度为150℃,加压时间为2分钟。通过该工序,薄片变为暂时熔融状态,半导体芯片100和无源器件110在薄片的至少一面让凸块140和凸起状电极150的表面露出的状态被埋置。通过该埋置,形成器件内置薄片120。此时,为确保凸块140以及凸起状电极150露出,埋入后,可在薄片的表面用等离子体等做清洗处理。
接下来,在步骤S4中,在嵌埋有半导体芯片100和无源器件110的器件内置薄片120的另一面,层叠例如25μm的第二覆盖薄片180。另外,该工序对于在嵌入有半导体芯片100和无源器件110的器件内置薄片120的另一面的熔接时的粘结强度较强的情况下也可以省略,藉此,可以得到更薄的电路模块。另外,也可在进行下述步骤S6的同时,层叠第二覆盖薄片180。
接下来,在步骤S5中,在露出凸块140和凸起状电极150的器件内置薄片120(例如由软化温度为120℃做成的材料构成时)的一个面上丝网印刷导电性浆料。然后,例如以110℃加热10分钟,干燥导电性浆料,使之硬化,从而形成具有给定图案形状的例如15μm厚的布线图案130。另外,布线图案130也可以通过纳米级导电性浆料的丝网印刷和镀金,溅射制膜等形成。另外,为提高折叠部分190的可靠性,将优选具有良好延展性、高抗折性的诸如金、银、铜等形成的金属材料。
因此,在步骤S6中,在含有布线图案130的器件内置薄片120的一个面上层叠由诸如PETG形成的25μm的第一覆盖薄片170。此时,也可以和步骤S4所示的第二覆盖薄片180同时层叠。
图3A表示上述步骤S1到步骤S6的各工序结束后的结构剖面图。另外,器件内置薄片120、第一覆盖薄片170和第二覆盖薄片180使用同一材料时,可容易地通过热粘结实现一体化。另外,为了避免半导体芯片100和无源器件110的流动,希望覆盖薄片的软化温度与构成器件内置薄片120的薄片的软化温度相比为相同程度或者更低。
因此,在以下的说明中,把由器件内置薄片120、第一覆盖薄片170以及第二覆盖薄片180三者叠合为一体的器件单称作模块薄片200。
另外,在步骤S7中,将形成于最下层的模块薄片200的电路区块300放置于平坦的台面上,在其折叠位置的电路区块300的边界部分310放置支撑杆160。然后,如图3B所示,以支撑杆160为中心顺次以例如S字状折叠,藉此准备具有4层的电路模块。
另外,折叠方法不限于S字状,可以任意选定电路区块300的折叠位置,以诸如螺旋状折叠。至于支撑杆160,可以用例如和器件内置薄片120相同的材料,ABS树脂、丙烯树脂等塑料、不锈钢等金属材料。另外,当在一体化后取除支撑杆160时,优选在支撑杆160的表面由例如氟素树脂等覆盖,进行离型处理。
另外,若能确保与布线图案140的绝缘性,作为支撑杆160也可以用镍铬合金等高电阻率的金属线。然后,在其中流过电流,让器件内置薄片120、第一覆盖薄片170及第二覆盖薄片180软化,以支撑杆160和模块薄片200粘结的状态折叠。
在这种情况下,优选在模块薄片200上的支撑杆160的位置固定,且使折叠部分190软化,以提高折叠部位的弯曲精度。
另外,当各层间需要正确定位时,也可以利用在各层预设的定位标记,进行光学定位。
接下来,在特别要求耐湿性等高可靠性的场合,在步骤S8中,对折叠后的模块薄片200层叠保护薄片,该步骤S8并不一定需要。
接下来,在步骤S9中,将4层折叠的模块薄片200或层叠有保护薄片的模块薄片200夹在热压板的中间,加热并且加压。这时的条件,例如模块薄片200是PETG时,只要压力为35kg/cm2,温度为110℃,加压时间为1分钟即可。
通过以上的工序,模块薄片200通过热熔融各层之间熔接,成为一体。因此,如图3C所示,得到所有半导体芯片100和无源器件110完全被嵌埋在模块薄片200中的结构。
最后,在步骤S10中,利用激光除去用于同外部电路连接的电极位置的模块薄片200,使布线图案130的一部分露出,在其表面用导电性浆料、焊锡球等形成连接电极210。
通过以上的工序,得到如图1所示的电路模块。
另外,以下说明在本实施例的电路模块有关另一变形例的电路模块。
该变形例的电路模块的特征为:在图2所示的步骤S5中,当在凸块140露出的器件内置薄片120的一个面上,通过丝网印刷导电性浆料,形成布线图案130时,同时形成与布线图案130电连接的无源器件110。作为该无源器件110,能够形成例如薄膜电感器或厚膜电感器,或电容器、电阻器等无源元件。由这样的无源元件构成的无源器件110的形成,可在厚膜电子器件用的材料浆料和电介质材料上,通过采用丝网印刷法或喷墨技术、分配器(dispenser)技术的绘图法进行。另外,也可以将薄片状装置等无源器件110通过导电性浆料等安装在器件内置薄片120的表面。
藉此,在由多层形成的器件内置薄片120的内部,将某一层作为厚膜电子器件形成领域利用,通过内置占有面积大的电感器、电容器和电阻器等可得到高密度的电路模块。进一步,也能在折叠部分190处形成薄膜或厚膜电子器件。
其后,经过和图2同样的工序,得到内置薄膜或厚膜电子器件的电路模块。
另外,图4表示有关本实施例的电路模块又一变形例的电路模块。
该变形例的电路模块的特征为:在由4层一体化的电路区块300形成的模块薄片200中,具有在与布线图案130相面对的第二层或第三层间的给定连接盘之间通过导电性浆料电连接的连接体220。
该结构是通过用激光除去与诸如连接体220连接的连接盘位置的第一覆盖薄片170后,折叠将导电性浆料填充到连接盘的模块薄片200,叠合为一体化而做成。通过该连接体220,与通过折叠部分190连接的布线图案130相比,能够缩短多个半导体芯片100以及无源器件110之间的布线距离。
本实施例中,半导体芯片100和无源器件110埋置在器件内置薄片120的内部。因此,实际的电路模块厚度大体上取决于由器件内置薄片120、第一覆盖薄片170和第二覆盖薄片形成的覆盖薄片的厚度以及叠合的层数。其结果为能够制造具有非常薄的层叠结构的电路模块。
另外,本实施例的制造方法,在器件内置薄片120中,在构成多层的电路区块300上,将必要的半导体芯片100和无源器件110以在同一平面展开的形式埋置,形成布线图案130,通过对之折叠而层叠化。为此,与个别地制作构成各层的电路区块300的层叠化方法相比,工序非常简单。
另外,叠合形成的模块薄片200,通过热熔接而一体化,因而具有不易因层间剥离产生密封不良和断线不良的优越效果。
另外,上述发明中的无源器件110示出了芯片电容器、芯片电阻器、芯片电感器和芯片状晶体管等芯片器件。另外,对于布线图案130,虽然通过印刷导电性浆料形成的方法进行了说明,也可以用将镀金层图案化的方法形成。因此,与外部电路连接的连接电极210也可通过镀金层和各向异性导电膜形成。
另外,本实施例中,是以半导体芯片100的凸块140和无源器件110的凸起状电极150在器件内置薄片120的同一面露出的情况为例进行了说明。可是,如图5的折叠前的模块薄片的剖面图所示,半导体芯片100的凸块140和无源器件110的凸起状电极150的露出面并不一定在同一面。例如,也可以在器件内置薄片120的两面露出。在该种情况下,布线图案130与同一面上露出的凸块140和凸起状电极150相连接。因此,也可在第一覆盖层上形成相当的覆盖薄片,折叠为一体化结构。另外,当器件内置薄片120的热粘结强度大,而布线图案130一体化时相互不短路构成的情况,也可不形成覆盖薄片。
另外,显然上述结构能够适用于以下的实施例。
第二实施例
图6表示有关本发明第二实施例的电路模块的剖面图。
本实施例的电路模块具有在由4层形成的器件内置薄片120的内部埋置半导体芯片100和无源器件110,并形成有布线图案130的结构。进一步,切断折叠部分190,通过通孔230实现不同层之间的电连接。
另外,对于与图1相同的结构采用相同符号,并省略其说明。另外,半导体芯片100的凸块140和无源器件110的凸起状电极150与第一实施例相同。进一步,由4层形成的器件内置薄片120与第一实施例的情况相同,热粘接为一体,成为其连接边界面消失的状态。
以下,说明有关本实施例的电路模块的制造方法。
首先,将埋设有半导体芯片100和无源器件110的器件内置薄片120折弯并层叠,直至通过加热和加压处理实现一体化的工序(相当于图2的步骤S9),与第一实施例相同。
接下来,利用切片锯或激光等切断折叠部分190,可得到如图7A所示的层叠层。
接下来,在没有安装半导体芯片100和无源器件110的周边区域,或在半导体芯片100和无源器件110之间,通过激光加工或钻孔加工形成贯通孔。同时,用诸如丝网印刷法在该贯通孔填充导电性浆料或用金属镀金法形成导电层,藉此得到通孔230。图7B表示该工序结束后的层叠体结构。
接下来,在为了同外部电路连接而被赋予了导电性的通孔230的位置,用焊锡和导电性浆料等形成连接电极210。
通过以上工序,得到图6或图7C所示的电路模块。
依据本发明第二实施例,由于利用通孔230进行层间连接,与有关第一实施例的通过折叠部分190的布线图案130的层间连接相比,能够缩短连接布线长度。特别是,能够缩短不相邻接的层间的连接布线长度。
藉此结构,能够抑制布线图案130的连接布线的长度引起的阻抗增加,改善电路模块的低噪音化和高频特性。
第三实施例
图8表示有关本发明第三实施例的电路模块的大概结构的剖面图。
本实施例的电路模块具有在由4层形成的器件内置薄片120的内部埋置半导体芯片100和无源器件110,并形成有布线图案130的结构。另外,不同层间通过设置在模块薄片200的诸如金属线等形成的导电性部件240实现电连接。
另外,对于与图1相同的结构采用相同符号,并省略其说明。另外,半导体芯片100的凸块140和无源器件110的凸起状电极150和第一实施例相同。进一步,构成4层的各模块薄片200,与第一实施例的情况相同,热熔接为一体化,成为这些连接边界面消失的状态。
在本发明的第三实施例中,不限于通孔230,可通过盲孔实现层间连接。
以下,说明有关本实施例的电路模块的制造方法。
图9表示说明有关第三实施例的电路模块的制造方法的流程图。图10表示图9的主要处理工程和工程结束后的主要部位剖面图。
首先,在步骤S1中,准备研磨成薄片状且在电极(图中未示出)上用诸如导线焊接法等形成有凸块140的半导体芯片100,和形成有凸起状电极150的无源器件110以及用于各层间连接的导电性部件240。例如,半导体芯片100和无源器件110的厚度各自为50μm。凸块140和凸起状电极150的高度优选为通过研磨或者按压统一成25μm的程度,但并不限定于此。导电性部件240的大小,对于诸如园柱形的情况,直径为0.2mm,高度可与器件内置薄片120的厚度相当。
接下来,在步骤S2中,在由聚乙烯对苯二酸盐(PETG)、氯化乙烯、聚碳酸脂、或丁晴苯乙烯等热可塑性树脂形成的诸如75μm厚的薄片上的给定位置载置形成有凸块140的半导体芯片100、形成凸起状电极150的无源器件110以及导电性部件240。此时,导电性部件240以垂直于薄片表面的方向载置。
接下来,在步骤S3中,将载置有半导体芯片100、无源器件110和导电性部件240的薄片夹在热压板中间,加热同时加压。例如,对于PETG,压力为30kg/cm2,温度为120℃,加压时间为1分钟。通过该工序,半导体芯片100和无源器件110,在薄片的至少一个面以凸块140、凸起状电极150以及导电性部件240的表面露出的状态被埋置。通过该埋置,形成器件内置薄片120。
接下来,在步骤S4中,在埋置有半导体芯片100和无源器件110的器件内置薄片120的另一个面,层叠例如25μm的第二覆盖薄片180。另外,该工序对于在埋置有半导体芯片100和无源器件110的器件内置薄片120的另一个面的热粘结的结合强度较强的情况也可以省略。藉此,可以得到更薄的电路模块。另外,也可在进行下述步骤S6的同时,层叠第二覆盖薄片180。
接下来,在步骤S5中,在凸块140和凸起状电极150露出的器件内置薄片120的一个面丝网印刷导电性浆料。然后,例如以110℃加热10分钟,干燥导电性浆料,使之硬化,从而形成连接凸块140和凸起状电极150的具有给定图案形状的布线图案130。
因此,在步骤S6中,在含有布线图案130的器件内置薄片120的表面层叠由诸如PETG形成的25μm的第一覆盖薄片170。此时,根据必要,也可以和第二覆盖薄片180同时层叠。
接下来,在步骤S7中,根据必要用激光除去连接不同层间的导电性部件240的位置的第一覆盖薄片170和第二覆盖薄片180,在其开口部900填充导电性浆料。
图10A表示该工序结束后的结构剖面图。另外,省略步骤S7也可形成盲孔。
接下来,由于图10B所示的折叠工序(步骤S8)以下的工序同第一实施例(相当于图2所示的步骤S7以下的工序)相同,因此省略其说明。
最后,利用诸如切片锯等切断折叠部分190,形成用于同外部电路连接的连接电极210(步骤S11),得到图8或图10C所示的电路模块。
依据本实施例,由于各层的模块薄片200通过热熔接形成为一体,因此具有不易因层间剥离出现密封不良及断线不良的优越效果。
另外,由于能够用像金属线的低电阻材料形成导电性部件240,能够进一步降低布线电阻,结果改善了电路模块的低噪音化和高频特性。
另外,作为步骤S7的工序的替代,器件内置薄片120、由第一覆盖薄片170和第二覆盖薄片180等形成的覆盖薄片被叠合或一体化的模块薄片200的状态,也可以埋置其长度与模块薄片200的厚度相同程度的导电性部件240。
藉此,可以使得后续工序简化。
另外,在本发明的各实施例中,对于由4层形成的层叠结构中,层叠的数目并不限定于此,可以根据需要的电路规模、尺寸、成本等观点决定。
另外,依据本发明,高密度内置了半导体芯片和无源器件的薄型、层叠型的电路模块可通过简单的制造工序制造。
进一步,相面对的模块薄片之间不用组份不同的粘结剂,由于能够通过熔融由同一组份形成的热可塑性树脂,因此不易因温度变化、压力等产生层间剥离。
因而,能够以较低的价格制造高性能的IC卡、存储卡以及各种移动机器用的电路模块等。

Claims (17)

1、一种电路模块,通过叠合埋置有电子器件的器件内置薄片而进行层叠化,其特征在于,包括:
器件内置薄片,其具有以至少让所述电子器件的凸起状电极表面露出的方式埋入了该电子器件的多个电路区块;
布线图案,其与所述器件内置薄片的所述凸起状电极连接;
覆盖薄片,其覆盖所述布线图案;
沿所述电路区块的边界折叠并层叠所述电路区块,使所述器件内置薄片以及所述覆盖薄片熔接,成为一体化。
2、根据权利要求1所述的电路模块,其特征在于,载置有与所述布线图案电连接的薄片状的无源元件。
3、根据权利要求1所述的电路模块,其特征在于,所述器件内置薄片和所述覆盖薄片由热可塑性树脂形成。
4、根据权利要求1所述的电路模块,其特征在于,层叠的所述器件内置薄片的所述电路区块之间,通过设置于所述折叠部分的所述布线图案而连接。
5、根据权利要求1所述的电路模块,其特征在于,层叠的所述器件内置薄片的所述电路区块之间的所述布线图案,通过贯通所述电路区块之间的通孔电连接。
6、根据权利要求1所述的电路模块,其特征在于,通过埋置于所述器件内置薄片的每个所述电路区块中的导电性部件,所述布线图案之间被电连接。
7、根据权利要求1所述的电路模块,其特征在于,在层叠的所述器件内置薄片的最外层的布线图案上设有旨在与外部电路连接的连接电极。
8、一种电路模块的制造方法,其特征在于,包括:
形成器件内置薄片的工序,该器件内置薄片具有以至少让电子器件的凸起状电极表面露出的方式埋入了该电子器件的多个电路区块;
形成布线图案的工序,该布线图案与所述器件内置薄片的所述凸起状电极连接;
由覆盖薄片覆盖所述布线图案的工序;
通过在所述电路区块的边界折叠所述器件内置薄片而进行层叠的工序;和
对层叠后的所述器件内置薄片和所述覆盖薄片热压,使其相互熔接而一体化的工序。
9、一种电路模块的制造方法,其特征在于,包括:
形成器件内置薄片的工序,该器件内置薄片具有以至少让电子器件的凸起状电极表面露出的方式埋入了该电子器件的多个电路区块;
形成布线图案的工序,该布线图案与所述器件内置薄片的所述凸起状电极连接;
由覆盖薄片层叠埋入了所述电子器件的所述布线图案的工序;
通过在所述电路区块的边界折叠所述器件内置薄片而进行层叠的工序;和
对层叠后的所述器件内置薄片和所述覆盖薄片热压,使其相互熔接而一体化的工序。
10、根据权利要求8所述的电路模块的制造方法,其特征在于,形成与所述布线图案电连接的薄片状的无源元件。
11、根据权利要求9所述的电路模块的制造方法,其特征在于,形成与所述布线图案电连接的薄片状的无源元件。
12、根据权利要求10所述的电路模块的制造方法,其特征在于,所述薄片状的无源元件通过导电性浆料或电介质的印刷或描绘而形成。
13、根据权利要求11所述的电路模块的制造方法,其特征在于,所述薄片状的无源元件通过导电性浆料或电介质的印刷或描绘而形成。
14、根据权利要求8所述的电路模块的制造方法,其特征在于,所述布线图案通过导电性浆料的印刷而形成。
15、根据权利要求9所述的电路模块的制造方法,其特征在于,所述布线图案通过导电性浆料的印刷而形成。
16、根据权利要求8所述的电路模块的制造方法,其特征在于,沿所述电路区块的边界线载置支撑杆,将所述支撑杆作为折叠的支点。
17、根据权利要求9所述的电路模块的制造方法,其特征在于,沿所述电路区块的边界线载置支撑杆,将所述支撑杆作为折叠的支点。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4602208B2 (ja) * 2004-12-15 2010-12-22 新光電気工業株式会社 電子部品実装構造体及びその製造方法
US7052290B1 (en) * 2005-08-10 2006-05-30 Sony Ericsson Mobile Communications Ab Low profile connector for electronic interface modules
TWI263313B (en) * 2005-08-15 2006-10-01 Phoenix Prec Technology Corp Stack structure of semiconductor component embedded in supporting board
TWI365524B (en) * 2007-10-04 2012-06-01 Unimicron Technology Corp Stackable semiconductor device and fabrication method thereof
US8174103B2 (en) * 2008-05-01 2012-05-08 International Business Machines Corporation Enhanced architectural interconnect options enabled with flipped die on a multi-chip package
JP2010225943A (ja) * 2009-03-24 2010-10-07 Toshiba Corp 半導体装置
KR20120079742A (ko) 2011-01-05 2012-07-13 삼성전자주식회사 폴디드 적층 패키지 및 그 제조방법
US9204547B2 (en) * 2013-04-17 2015-12-01 The United States of America as Represented by the Secratary of the Army Non-planar printed circuit board with embedded electronic components
US20150282367A1 (en) * 2014-03-27 2015-10-01 Hans-Joachim Barth Electronic assembly that includes stacked electronic components
US11647678B2 (en) * 2016-08-23 2023-05-09 Analog Devices International Unlimited Company Compact integrated device packages
JP6906228B2 (ja) * 2017-08-18 2021-07-21 ナミックス株式会社 半導体装置
JP7044007B2 (ja) * 2018-07-31 2022-03-30 株式会社オートネットワーク技術研究所 回路構成体

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02239695A (ja) 1989-03-13 1990-09-21 Nec Corp 多層プリント配線板
US6225688B1 (en) * 1997-12-11 2001-05-01 Tessera, Inc. Stacked microelectronic assembly and method therefor
US6121676A (en) * 1996-12-13 2000-09-19 Tessera, Inc. Stacked microelectronic assembly and method therefor
JP3588230B2 (ja) * 1997-07-31 2004-11-10 京セラ株式会社 配線基板の製造方法
US6376769B1 (en) * 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
JP3891743B2 (ja) 1999-09-20 2007-03-14 松下電器産業株式会社 半導体部品実装済部品の製造方法、半導体部品実装済完成品の製造方法、及び半導体部品実装済完成品
US6538210B2 (en) * 1999-12-20 2003-03-25 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module, radio device having the same, and method for producing the same
US6683377B1 (en) * 2000-05-30 2004-01-27 Amkor Technology, Inc. Multi-stacked memory package
JP2002043513A (ja) 2000-07-31 2002-02-08 Sanyo Electric Co Ltd 半導体装置およびその製造方法
US6672882B2 (en) * 2000-12-01 2004-01-06 Via Technologies, Inc. Socket structure for grid array (GA) packages
EP1306900A3 (en) * 2000-12-28 2005-07-06 Texas Instruments Incorporated Chip-scale packages stacked on folded interconnector for vertical assembly on substrates
TW511415B (en) * 2001-01-19 2002-11-21 Matsushita Electric Ind Co Ltd Component built-in module and its manufacturing method
US7071547B2 (en) * 2002-09-11 2006-07-04 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
JP2004363568A (ja) * 2003-05-09 2004-12-24 Matsushita Electric Ind Co Ltd 回路素子内蔵モジュール
US6940158B2 (en) * 2003-05-30 2005-09-06 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
CN1577819A (zh) * 2003-07-09 2005-02-09 松下电器产业株式会社 带内置电子部件的电路板及其制造方法
US6862191B1 (en) * 2003-08-19 2005-03-01 Cardiac Pacemakers, Inc. Volumetrically efficient electronic circuit module
JP2005203674A (ja) * 2004-01-19 2005-07-28 Nitto Denko Corp 電子部品内蔵基板の製造方法
JP4361826B2 (ja) * 2004-04-20 2009-11-11 新光電気工業株式会社 半導体装置

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