CN1761040A - 在表面上形成接触窗开口的方法 - Google Patents

在表面上形成接触窗开口的方法 Download PDF

Info

Publication number
CN1761040A
CN1761040A CN200510059368.6A CN200510059368A CN1761040A CN 1761040 A CN1761040 A CN 1761040A CN 200510059368 A CN200510059368 A CN 200510059368A CN 1761040 A CN1761040 A CN 1761040A
Authority
CN
China
Prior art keywords
dielectric layer
layer
contact window
material surface
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN200510059368.6A
Other languages
English (en)
Inventor
蔡奎昌
赵俊源
萧家顺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Promos Technologies Inc
Original Assignee
Promos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=36145913&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=CN1761040(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Promos Technologies Inc filed Critical Promos Technologies Inc
Publication of CN1761040A publication Critical patent/CN1761040A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

Abstract

一种在半导体材料的表面上形成接触窗开口的方法，此接触窗开口具有对配置于接触窗开口上的介电层进行非等向性蚀刻所制作出的侧壁。保护层配置于半导体材料的表面上。为了保护基底，进行最初的蚀刻而穿过层间介电层，以形成通往基底但并没有穿入的最初的孔洞。并且，在基底上保留至少一部份的保护层。在另一步骤中，形成最终的接触窗开口。在此步骤中，穿过保护层形成开口至半导体材料的表面。

Description

在表面上形成接触窗开口的方法
技术领域
本发明是有关于一种半导体元件的制作方法，且特别是有关于一种半导体元件中材料表面的接触窗开口的形成方法。
背景技术
在半导体元件的制作中，大多希望能提供较小直径的开口以连接到元件。然而此会受限于光罩开口的直径，其中光罩开口是暴露出覆盖于待蚀刻材料上的光阻层。因此，形成比使用的光罩开口及光阻层所暴露的区域小的连接开口直径，是让人期望的。习知技术中已达成上述目的，其技术是利用光罩对光阻层进行曝光后，向下蚀刻出开口，此开口连接至需要被连接的表面。之后，配置覆盖材料至开口与需要被连接的表面上。在覆盖材料沉积之后，进行非等向性蚀刻。因为非等向性蚀刻的特性，在孔洞底部的一部份覆盖材料会被蚀刻去除，而一部份的材料在蚀刻过程中会被保留。因此，在开口底部而需要被连接的表面会再被进行一次蚀刻制程，因而对最后以电性连接而接触的基底材料造成损害。
因此，可以理解的是，在习知技术中，第一次蚀刻形成向下通往需要被连接的表面的开口，接着进行材料的覆盖以及对其进行非等向性蚀刻。使用习知技术在形成开口时会进行二次蚀刻，因此在提供开口底部的材料的接触前，会造成不必要的损害。
因此，需要一单一的蚀刻制程，以在形成覆盖层覆盖开口内的侧壁的同时，在开口底部形成接触区域。
发明内容
本发明提出一种在材料表面形成接触窗开口的方法，可避免习知技术所造成的损害效应。根据本发明的一态样，材料表面的接触窗开口的形成，是先在表面上形成第一介电层，然后在第一介电层上形成第二介电层，接着自第二介电层的表面至材料的接触表面形成第一孔洞，其长度小于第一介电层与第二介电层相连接的厚度。之后，形成第三介电层以覆盖孔洞的表面与暴露出的第一介电层表面。然后，去除第三介电层与第一介电层的一部份，以暴露出材料的连接表面区域的一部份。
在一实施例中，在表面上形成第一介电层的方法例如为在表面上沉积氮化硅层。
在一实施例中，在表面上形成第一介电层的方法例如为在表面上沉积氮氧化硅层。
在一实施例中，形成第一介电层的方法例如为化学气相沉积制程。
在一实施例中，形成第一介电层的方法例如为使用化学气相沉积制程沉积氮氧化硅层。
在一实施例中，去除第三介电层与第一介电层的一部份以暴露出材料的表面的一部份的方法例如为非等向性蚀刻制程。
在一实施例中，在第一介电层上形成第二介电层的方法例如为在第一介电层上形成二氧化硅层。
在一实施例中，形成第一孔洞的方法例如为蚀刻制程。
在一实施例中，蚀刻制程例如为反应离子蚀刻。
在一实施例中，去除第三介电层与第一介电层的一部份的方法例如为反应离子蚀刻。
为让本发明的上述和其他目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合所附图式，作详细说明如下。
附图说明
图1所示为一部份半导体基底的剖面示意图。
图2所示为形成保护层后的图1中的结构的剖面示意图。
图3所示为形成第二介电层与光阻层并进行蚀刻后的图2中的结构的剖面示意图。
图4所示为形成蚀刻至闸极的介层窗开口的结构的剖面示意图。
图5所示为形成第三介电材料后的结构的剖面示意图。
图6所示为进行非等向性蚀刻后的结构的剖面示意图。
1：基底                       2：闸氧化层
3、12：表面                   4：闸极
5、8：保护层                  6：源极
7：汲极                       9：第二介电层
10、13：光阻层                11：接触窗
14、18、19：开口              15：第三介电层
16、17：覆盖层
具体实施方式
请参阅图1所示，为一部份半导体基底的剖面示意图。如图1所示，基底1包括在基底1的表面3上的闸氧化层2与配置于闸氧化层2顶端的闸极4。保护层5配置于闸极4上，有时候称为闸氮化层，其材质例如为氮化硅(Si3N4)。闸氧化层2的材质可以为习知技术中的任何氧化物。闸极4的材质例如为多晶硅。上述结构可以习知技术来形成，在此不另行叙述。图1也绘示出与闸极4结合在一起的源极6与汲极7。值得注意的是，连结闸极、源极与汲极的方式是采对其最小损害的方式相连结，且连结制程将在此描述。
请参阅图2所示，为形成保护层后的图1中的结构的剖面示意图。如图2所示，保护层8，有时候称为阻障层，覆盖于表面3、闸极4、保护层5与闸氧化层2上。保护层8的材质例如为氮化硅或氮氧化硅(Si3OXNY)，其中X与Y可以为0～2。保护层8可以利用习知技术来形成，例如为低压化学气相沉积法(LPCVD)或电浆增强型化学气相沉积法(PECVD)。保护层8的厚度例如为20～500。举例来说，较佳的厚度例如为大约230。
请参阅图3所示，为形成第二介电层与光阻层并进行蚀刻后的图2中的结构的剖面示意图。如图3所示，在保护层8上配置第二介电层9，之后配置光阻层10并使用光罩以提供一开口，再利用此开口形成源极6的接触窗。最初的接触窗11是如图3所示蚀刻穿过第二介电层9。蚀刻穿过第二介电层9后，则停止在保护层8的表面12上。对最初的接触窗11进行蚀刻可以利用一般的蚀刻制程，此蚀刻制程例如为反应离子蚀刻，其蚀刻气体例如为六氟丁二烯(C4F6)/氧气(O2)/氩气(Ar)。如图3所示，形成接触窗11的蚀刻制程在到达保护层8后即停止。因为此蚀刻制程并没有穿过保护层8，所以可避免对基底1上的源极6的接触区域造成损害。第二介电层9在半导体结构的主动(active)层之间提供绝缘的作用，一般被称为层间介电层。第二介电层9的材质可为各种绝缘材料，例如为二氧化硅。
请参阅图4所示，为形成蚀刻至闸极的介层窗开口的结构的剖面示意图。如图4所示，在进行完蚀刻之后，去除光阻层10并以经过曝光的光阻层13代替，然后蚀刻第二介电层9以形成向下延伸至闸极4的最初的开口14。对最初的开口14进行蚀刻则可以利用如上所述与形成最初的接触窗11相同的制程。在形成穿过保护层8与5(有时候也被称为闸氮化层)的开口14之后，去除光阻层13。为了图示的方便，只有图示说明最初的接触窗11替源极6提供开口，然而也可以利用相同的技术替汲极7提供开口。
请参阅图5所示，为形成第三介电材料后的结构的剖面示意图。如图5所示，第三介电层15则使用在提供覆盖层至连接源极6与闸极4的接触窗开口时的最初步骤。第三介电层15的材质例如为氮化硅或氮氧化硅(Si3OXNY)，其中X与Y与前述的保护层8相同。第三介电层15的形成方法例如为低压化学气相沉积法或电浆增强型化学气相沉积法，其合适的厚度例如在20至500之间。一般较佳的厚度例如为150。
请参阅图6所示，为进行非等向性蚀刻后的结构的剖面示意图。如图6所示，进行非等向性蚀刻以去除第二介电层9表面上与通往源极6的接触窗中的保护层8上的第三介电层15。在图6中，除了第三介电层15，蚀刻制程也去除了源极6上方的接触窗中的保护层8。上述的蚀刻制程所使用的蚀刻气体及其特性将在表1中所叙述。其中，蚀刻制程例如为熟知的反应离子蚀刻技术。如表1所示，说明了二个示范的蚀刻制程的蚀刻比。反应离子蚀刻形成了通往源极6的最终开口18中的覆盖层16，与通往闸极4的最终开口19中的覆盖层17。
表1
  三氟甲烷/氩气   四氟甲烷/三氟甲烷/氩气
  蚀刻速率   均匀度(U％)   蚀刻速率   U％
  氮化硅蚀刻速率(/min)   1121或更高   3.65   1721.3或更高 11.90
  二氧化硅蚀刻速率(/min)   766或更高 5.24   1816.7或更高 5.26
  硅蚀刻速率(/min) 420或更高 600或更高
  氮化硅：二氧化硅选择比 1.46或更高 0.95或更高
  氮化硅：硅选择比 2.67或更高 2.87或更高
综上所述，使用上述的技术，在源极6部分的基底只需经过一次的蚀刻制程，因此对基底造成的损害可减至最小。
虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明，任何熟习此技艺者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视后附的申请专利范围所界定者为准。

Claims (10)

1、一种在材料表面形成接触窗开口的方法，其特征在于其包括：
在一材料的一表面上形成一第一介电层；
在该第一介电层上形成一第二介电层；
自该第二介电层的一表面至该材料的该表面形成一第一孔洞，其中该第一孔洞的长度小于该第一介电层与该第二介电层的总厚度；
形成一第三介电层，以覆盖该孔洞的一表面与暴露出的该第一介电层的一表面；以及
去除该第三介电层与该第一介电层的一部份，以暴露出该材料的该表面的一部份。
2、根据权利要求1所述的在材料表面形成接触窗开口的方法，其特征在于其中在该表面上形成该第一介电层的方法包括在该表面上沉积一氮化硅层。
3、根据权利要求1所述的在材料表面形成接触窗开口的方法，其特征在于其中在该表面上形成该第一介电层的方法包括在该表面上沉积一氮氧化硅层。
4、根据权利要求2所述的在材料表面形成接触窗开口的方法，其特征在于其中沉积该氮化硅层的方法包括使用一化学气相沉积制程。
5、根据权利要求3所述的在材料表面形成接触窗开口的方法，其特征在于其中沉积该氮氧化硅层的方法包括使用一化学气相沉积制程。
6、根据权利要求1所述的在材料表面形成接触窗开口的方法，其特征在于其中去除该第三介电层与该第一介电层的一部份以暴露出该材料的该表面的一部份的方法包括进行一非等向性蚀刻制程。
7、根据权利要求1所述的在材料表面形成接触窗开口的方法，其特征在于其中在该第一介电层上形成该第二介电层的方法包括在该第一介电层上形成二氧化硅层。
8、根据权利要求1所述的在材料表面形成接触窗开口的方法，其特征在于其中形成该第一孔洞的方法包括进行一蚀刻制程。
9、根据权利要求8所述的在材料表面形成接触窗开口的方法，其特征在于其中所述的蚀刻制程包括反应离子蚀刻。
10、根据权利要求1所述的在材料表面形成接触窗开口的方法，其特征在于其中去除该第三介电层与该第一介电层的一部份的方法包括进行一反应离子蚀刻。
CN200510059368.6A 2004-10-12 2005-03-29 在表面上形成接触窗开口的方法 Pending CN1761040A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/964,317 US7375027B2 (en) 2004-10-12 2004-10-12 Method of providing contact via to a surface
US10/964,317 2004-10-12

Publications (1)

Publication Number Publication Date
CN1761040A true CN1761040A (zh) 2006-04-19

Family

ID=36145913

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200510059368.6A Pending CN1761040A (zh) 2004-10-12 2005-03-29 在表面上形成接触窗开口的方法

Country Status (3)

Country Link
US (1) US7375027B2 (zh)
CN (1) CN1761040A (zh)
TW (1) TW200612487A (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4334558B2 (ja) * 2006-09-20 2009-09-30 株式会社東芝 パターン形成方法
JP2011009636A (ja) * 2009-06-29 2011-01-13 Oki Semiconductor Co Ltd ビアホールの形成方法
TWI396261B (zh) * 2009-11-11 2013-05-11 Inotera Memories Inc 堆疊式隨機動態存取記憶體之低寄生電容位元線之製造方法
US10692755B2 (en) 2018-10-24 2020-06-23 International Business Machines Corporation Selective deposition of dielectrics on ultra-low k dielectrics

Family Cites Families (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4352185A (en) 1980-07-18 1982-09-28 Uniphase Corporation Gas laser having improved stability against environmental conditions
US4377316A (en) 1981-02-27 1983-03-22 International Business Machines Corporation High density interconnection means for chip carriers
IT1215559B (it) 1987-06-11 1990-02-14 Sgs Microelettronica Spa Processo di fabbricazione per celle di memoria non volatili epromelettricamente cancellabili e cella cosi' ottenuta.
US4942554A (en) 1987-11-26 1990-07-17 Siemens Aktiengesellschaft Three-dimensional, one-transistor cell arrangement for dynamic semiconductor memories comprising trench capacitor and method for manufacturing same
US5278712A (en) 1990-07-19 1994-01-11 Kabushiki Kaisha Toshiba Removable disk drive having two heads formed with a gimbal structure
JPH06216338A (ja) 1992-11-27 1994-08-05 Internatl Business Mach Corp <Ibm> 半導体メモリセル及びその製造方法
EP0677869B1 (en) 1994-04-12 1999-03-17 STMicroelectronics S.r.l. Planarization process for the manufacturing of integrated circuits, particularly for non-volatile semiconductor memory devices
US6093615A (en) 1994-08-15 2000-07-25 Micron Technology, Inc. Method of fabricating a contact structure having a composite barrier layer between a platinum layer and a polysilicon plug
US5915170A (en) 1994-09-20 1999-06-22 Tessera, Inc. Multiple part compliant interface for packaging of a semiconductor chip and method therefor
US5506412A (en) 1994-12-16 1996-04-09 Buttrill, Jr.; Sidney E. Means for reducing the contamination of mass spectrometer leak detection ion sources
US5831276A (en) 1995-06-07 1998-11-03 Micron Technology, Inc. Three-dimensional container diode for use with multi-state material in a non-volatile memory cell
US5631179A (en) 1995-08-03 1997-05-20 Taiwan Semiconductor Manufacturing Company Method of manufacturing metallic source line, self-aligned contact for flash memory devices
US5650760A (en) 1995-11-13 1997-07-22 Hughes Aircraft Company Microwave enclosure
US5676587A (en) 1995-12-06 1997-10-14 International Business Machines Corporation Selective polish process for titanium, titanium nitride, tantalum and tantalum nitride
US5990021A (en) 1997-12-19 1999-11-23 Micron Technology, Inc. Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture
US5985698A (en) 1996-07-22 1999-11-16 Micron Technology, Inc. Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell
US5677227A (en) 1996-09-09 1997-10-14 Vanguard International Semiconductor Corporation Method of fabricating single crown, extendible to triple crown, stacked capacitor structures, using a self-aligned capacitor node contact
US6294040B1 (en) 1996-12-13 2001-09-25 Tessera, Inc. Transferable resilient element for packaging of a semiconductor chip and method therefor
US5795827A (en) 1997-01-15 1998-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing the resistance of self-aligned contacts, for triple polysilicon SRAM devices
US5904800A (en) 1997-02-03 1999-05-18 Motorola, Inc. Semiconductor wafer processing chamber for reducing particles deposited onto the semiconductor wafer
US5945354A (en) 1997-02-03 1999-08-31 Motorola, Inc. Method for reducing particles deposited onto a semiconductor wafer during plasma processing
US5792689A (en) 1997-04-11 1998-08-11 Vanguard International Semiconducter Corporation Method for manufacturing double-crown capacitors self-aligned to node contacts on dynamic random access memory
US5972765A (en) 1997-07-16 1999-10-26 International Business Machines Corporation Use of deuterated materials in semiconductor processing
US5940726A (en) 1997-11-06 1999-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming an electrical contact for embedded memory
US6093611A (en) 1997-12-19 2000-07-25 Advanced Micro Devices, Inc. Oxide liner for high reliability with reduced encroachment of the source/drain region
FR2773262B1 (fr) 1997-12-30 2000-03-10 Sgs Thomson Microelectronics Procede de formation d'elements conducteurs dans un circuit integre
US6129808A (en) 1998-03-31 2000-10-10 Lam Research Corporation Low contamination high density plasma etch chambers and methods for making the same
US5837577A (en) 1998-04-24 1998-11-17 Vanguard International Semiconductor Corporation Method for making self-aligned node contacts to bit lines for capacitor-over-bit-line structures on dynamic random access memory (DRAM) devices
US6218288B1 (en) 1998-05-11 2001-04-17 Micron Technology, Inc. Multiple step methods for forming conformal layers
US6150213A (en) 1998-07-08 2000-11-21 Vanguard International Semiconductor Corporation Method of forming a cob dram by using self-aligned node and bit line contact plug
US5918120A (en) 1998-07-24 1999-06-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and Ti/TiN bit lines
US6197628B1 (en) 1998-08-27 2001-03-06 Micron Technology, Inc. Ruthenium silicide diffusion barrier layers and methods of forming same
US6323081B1 (en) 1998-09-03 2001-11-27 Micron Technology, Inc. Diffusion barrier layers and methods of forming same
US6204172B1 (en) 1998-09-03 2001-03-20 Micron Technology, Inc. Low temperature deposition of barrier layers
US6063548A (en) 1998-09-04 2000-05-16 Taiwan Semiconductor Manufacturing Company Method for making DRAM using a single photoresist masking step for making capacitors with node contacts
US5893734A (en) 1998-09-14 1999-04-13 Vanguard International Semiconductor Corporation Method for fabricating capacitor-under-bit line (CUB) dynamic random access memory (DRAM) using tungsten landing plug contacts
US5895239A (en) 1998-09-14 1999-04-20 Vanguard International Semiconductor Corporation Method for fabricating dynamic random access memory (DRAM) by simultaneous formation of tungsten bit lines and tungsten landing plug contacts
US6180506B1 (en) 1998-09-14 2001-01-30 International Business Machines Corporation Upper redundant layer for damascene metallization
US6277733B1 (en) 1998-10-05 2001-08-21 Texas Instruments Incorporated Oxygen-free, dry plasma process for polymer removal
US6342446B1 (en) 1998-10-06 2002-01-29 Texas Instruments Incorporated Plasma process for organic residue removal from copper
US6121074A (en) 1998-11-05 2000-09-19 Siemens Aktiengesellschaft Fuse layout for improved fuse blow process window
TW396545B (en) 1998-12-21 2000-07-01 Vanguard Int Semiconduct Corp DRAM using oxide plug in bitline contacts during fabrication and its methods
US6136643A (en) 1999-02-11 2000-10-24 Vanguard International Semiconductor Company Method for fabricating capacitor-over-bit-line dynamic random access memory (DRAM) using self-aligned contact etching technology
US6001717A (en) 1999-02-12 1999-12-14 Vanguard International Semiconductor Corporation Method of making local interconnections for dynamic random access memory (DRAM) circuits with reduced contact resistance and reduced mask set
JP4044236B2 (ja) 1999-03-11 2008-02-06 株式会社東芝 半導体装置の製造方法
US6100569A (en) 1999-03-19 2000-08-08 United Microelectronics Corp. Semiconductor device with shared contact
US6242299B1 (en) 1999-04-01 2001-06-05 Ramtron International Corporation Barrier layer to protect a ferroelectric capacitor after contact has been made to the capacitor electrode
US6140178A (en) 1999-04-06 2000-10-31 Vanguard International Semiconductor Corporation Method to manufacture a capacitor with crown-shape using edge contact exposure
US6143604A (en) 1999-06-04 2000-11-07 Taiwan Semiconductor Manufacturing Company Method for fabricating small-size two-step contacts for word-line strapping on dynamic random access memory (DRAM)
US6461367B1 (en) 1999-07-16 2002-10-08 Loma Linda University Medical Center Method and device for urethral-vesicle anastomosis
US6380628B2 (en) 1999-08-18 2002-04-30 International Business Machines Corporation Microstructure liner having improved adhesion
US6258729B1 (en) 1999-09-02 2001-07-10 Micron Technology, Inc. Oxide etching method and structures resulting from same
US6168984B1 (en) 1999-10-15 2001-01-02 Taiwan Semiconductor Manufacturing Company Reduction of the aspect ratio of deep contact holes for embedded DRAM devices
US6441418B1 (en) * 1999-11-01 2002-08-27 Advanced Micro Devices, Inc. Spacer narrowed, dual width contact for charge gain reduction
US6350646B1 (en) 2000-01-18 2002-02-26 United Microelectronics Corp. Method for reducing thermal budget in node contact application
US6420752B1 (en) 2000-02-11 2002-07-16 Advanced Micro Devices, Inc. Semiconductor device with self-aligned contacts using a liner oxide layer
US6534389B1 (en) 2000-03-09 2003-03-18 International Business Machines Corporation Dual level contacts and method for forming
US6228771B1 (en) 2000-03-23 2001-05-08 Infineon Technologies North America Corp. Chemical mechanical polishing process for low dishing of metal lines in semiconductor wafer fabrication
US6486015B1 (en) 2000-04-25 2002-11-26 Infineon Technologies Ag Low temperature carbon rich oxy-nitride for improved RIE selectivity
US6303525B1 (en) 2000-08-18 2001-10-16 Philips Electronics No. America Corp. Method and structure for adhering MSQ material to liner oxide
US6461909B1 (en) 2000-08-30 2002-10-08 Micron Technology, Inc. Process for fabricating RuSixOy-containing adhesion layers
US6306759B1 (en) 2000-09-05 2001-10-23 Vanguard International Semiconductor Corporation Method for forming self-aligned contact with liner
US6495417B1 (en) 2000-09-26 2002-12-17 United Microelectronics Corps. Method for increasing tolerance of contact extension alignment in COB DRAM
US6455371B1 (en) 2001-02-15 2002-09-24 United Microelectronics Corp. Method for forming capacitor of a DRAM having a wall protection structure
KR100408411B1 (ko) 2001-06-01 2003-12-06 삼성전자주식회사 반도체 메모리 소자 및 그 제조방법
US6461959B1 (en) 2001-06-21 2002-10-08 United Microelectronics Corp. Method of fabrication of a contact plug in an embedded memory
US6525419B1 (en) 2002-02-14 2003-02-25 Intel Corporation Thermally coupling electrically decoupling cooling device for integrated circuits

Also Published As

Publication number Publication date
TW200612487A (en) 2006-04-16
US20060079080A1 (en) 2006-04-13
US7375027B2 (en) 2008-05-20

Similar Documents

Publication Publication Date Title
US6803313B2 (en) Method for forming a hardmask employing multiple independently formed layers of a pecvd material to reduce pinholes
US20060199370A1 (en) Method of in-situ ash strip to eliminate memory effect and reduce wafer damage
JP4417439B2 (ja) エッチング・ストップ層を利用する半導体装置構造とその方法
CN1761040A (zh) 在表面上形成接触窗开口的方法
TWI236094B (en) Method for forming multi-layer metal line of semiconductor device
CN1606149A (zh) 半导体器件的制造方法
KR100606532B1 (ko) 반도체 소자의 제조 방법
US20070045227A1 (en) Method of stripping photoresist
US6569784B1 (en) Material of photoresist protect oxide
CN1932652A (zh) 光致抗蚀剂剥离方法
CN1700419A (zh) 利用双镶嵌工艺来形成t型多晶硅栅极的方法
KR0168208B1 (ko) 다중합체 제거방법
CN1240114C (zh) 在同一蚀刻室进行介层窗蚀刻的方法
KR100479969B1 (ko) 반도체 플래시 메모리 소자 제조 방법
KR19990057932A (ko) 콘택홀 프로파일 개선을 위한 반도체 소자 제조 방법
KR100243283B1 (ko) 반도체장치의 커패시터 제조방법
KR100364810B1 (ko) 반도체소자의 제조방법
JPH0226025A (ja) コンタクトホールの形成方法
KR100264237B1 (ko) 홀 형성방법
CN1099132C (zh) 形成半导体器件的隔离层的方法
KR100467817B1 (ko) 반도체 소자의 금속배선 부식 방지방법
KR100399602B1 (ko) 반도체 디바이스용 금속 배선 제조 방법
KR950007571B1 (ko) 반도체소자의 금속배선 형성방법
KR100996161B1 (ko) 반도체 소자의 듀얼 다마신 패턴 형성 방법
CN1523646A (zh) 低介电常数介电质层的蚀刻方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C12 Rejection of a patent application after its publication
RJ01 Rejection of invention patent application after publication