CN1768419A - 形成鳍状场效应晶体管器件中的结构的方法 - Google Patents

形成鳍状场效应晶体管器件中的结构的方法 Download PDF

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CN1768419A
CN1768419A CNA2004800087527A CN200480008752A CN1768419A CN 1768419 A CN1768419 A CN 1768419A CN A2004800087527 A CNA2004800087527 A CN A2004800087527A CN 200480008752 A CN200480008752 A CN 200480008752A CN 1768419 A CN1768419 A CN 1768419A
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fin structure
semiconductor device
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crystal silicon
dielectric
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林明仁
汪海宏
俞斌
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Advanced Micro Devices Inc
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Abstract

一种半导体器件，包括第一鳍状结构(810)、第二鳍状结构(810)及第三鳍状结构(210)。该第一及第二鳍状结构(810)包括单晶硅材料。该第三鳍状结构(210)位于该第一及第二鳍状结构(810)之间，其包括介电材料。该第三鳍状结构(210)产生应力，该应力导引至该第一及第二鳍状结构(810)中的单晶硅材料。

Description

形成鳍状场效应晶体管器件中的结构的方法
技术领域
本发明一般涉及半导体制造，尤其涉及形成鳍状场效应晶体管(FinFET)器件。
背景技术
随着在超大尺寸集成半导体器件领域对高密度及高性能需求的逐渐增强，要求诸如栅极长度等设计特征小于100nm，并具有高可靠性能和不断增加生产率。这种在设计特征尺寸(design features)减小到100nm以下后，对传统方法论的极限提出了挑战。
例如，当传统的平面型金属氧化物半导体场效应晶体管(MOSFET)的栅极长度小于100nm时，短沟道效应引起的例如源极与漏极间的过量漏电流(excessive leakage)问题，变得越来越难克服。此外，迁移率降低以及许多工艺处理方面的问题也使得传统MOSFET很难掌握对尺寸不断减小的器件特性的兼容。因此急待研发一种新器件结构以改善FET的性能并容许器件规模更进一步减小。
双栅极MOSFET描述一种新的结构，该结构已经被认为是替代目前平面型MOSFET的最佳结构。在双栅极MOSFET内，可使用两个栅极控制短沟道效应。而鳍状场效应晶体管(FinFET)是双栅极结构，其有很好的短沟道效应行为，该FinFET包括有形成在垂直鳍状片(Fin)中的沟道。该FinFET结构也可使用类似于传统平面型MOSFET的布图及工艺技术制造。
发明内容
按照本发明的原理的实施例提供单晶硅鳍状结构，该结构形成在介电鳍状结构的相对侧上。该介电鳍状结构的材料经选择以在该单晶硅材料中引起有效应力，从而可增强迁移率。
如这里所包含及广泛描述的与本发明相一致的目的一样，半导体器件包括第一鳍状结构，其包含介电材料且具有第一侧表面及第二侧表面；第二鳍状结构，其包含单晶硅材料且形成在邻近该第一鳍状结构的第一侧表面；第三鳍状结构，其包含该单晶硅材料且形成于邻近该第一鳍状结构的第二表面侧；形成于该第一、第二及第三鳍状结构一端的源极区；形成于该第一、第二及第三鳍状结构另一端的漏极区；以及至少一个栅极。
在按照本发明原理的另一实施例中，揭示一种制造半导体器件的方法，该半导体器件包括衬底以及形成在该衬底上的介电层。该方法包括：蚀刻该介电层以形成第一鳍状结构；沉积无定形硅层；蚀刻该无定形硅层以形成邻近于该第一鳍状结构的第一侧表面的第二鳍状结构以及邻近该第一鳍状结构的第二相对侧表面的第三鳍状结构；至少在该第二鳍状结构及该第三鳍状结构的上表面上沉积金属层；实施金属诱导结晶操作，使该第二鳍状结构及该第三鳍状结构内的无定形硅转变为单晶硅材料；形成源极区及漏极区；在该第一、第二及第三鳍状结构上面沉积栅极材料；以及图形化并蚀刻该栅极材料以形成至少一个栅极电极。
在按照本发明原理的再一实施例中，揭示一种半导体器件，该半导体器件包括第一鳍状结构、第二鳍状结构及第三鳍状结构。该第一及第二鳍状结构包括单晶硅材料。该第三鳍状结构位于该第一及第二鳍状结构之间，其包括介电材料。该第三鳍状结构产生应力，该应力被导引至该第一及第二鳍状结构中的单晶硅材料。
附图说明
以下附图，用以并入并组成说明书的一部分，其阐明本发明的实施例，并一起描述、说明本发明，其中，
图1给出了在按照本发明原理的实施例中用于形成鳍状场效应晶体管器件的鳍状结构的典型工艺；
图2至图9显示了根据图1所示的工艺所制造的鳍状场效应晶体管器件的典型视图；
图10至图15显示了在按照本发明原理的替换实施例中用于形成多鳍状结构的典型视图；以及
图16及图17显示了依据本发明原理的替换实施例用于产生沟槽(trench)的典型视图。
具体实施方式
将参考附图详细说明按照本发明的实施例。在不同的附图中，相同的参考标记可标示相同或相似的元件，并且如下详细说明并非用于限制本发明，相反，本发明的范围如权利要求及其对等的实施例所定义。
按照本发明原理的实施例提供了形成在介电鳍状结构相对侧上的单晶硅鳍状结构。该介电鳍状结构的材料经选择，以在该单晶硅材料中引起有效应力，以增强迁移率。
图1给出了在按照本发明原理的实施例中用于形成鳍状场效应晶体管器件的鳍状结构的典型方法。图2至图9显示了根据图1所示的方法制造鳍状场效应晶体管器件的典型视图。将在下文中说明鳍状场效应晶体管器件的制造。然而须了解，这里所说明的技术可相等地应用于形成多于一个的鳍状场效应晶体管器件。
参考图1及图2(步骤105)，工艺可开始于在半导体器件的衬底200上形成介电鳍状结构210。在一个实施例中，该衬底200可包括硅。在与本发明相一致的可替换的实施例中，该衬底200可包括诸如锗的其它半导体材料或例如硅锗的结合半导体材料。在其它实施例中，衬底200可包含形成于硅或锗衬底上的例如氧化层的绝缘物。该介电鳍状结构210可包含介电材料，该介电材料在双鳍状结构中产生有效张应力(应变)，该双鳍状结构邻近该介电鳍状结构210形成。在一个实施例中，该介电鳍状结构210可包含氧化物或金属镍。
可用传统的方法形成该介电鳍状结构210。例如，在该衬底200上沉积介电材料，沉积的厚度大约在200到1000范围内。在部分的介电材料上可形成屏蔽(mask)，接着可用传统的方法蚀刻该介电材料，在该衬底200上结束蚀刻以形成该介电鳍状结构210。该得到的介电鳍状结构210的宽度大约在100到1000范围内。
在形成该介电鳍状结构210之后，如图3所示(步骤110)，可在该半导体器件上沉积无定形硅层(amorphous silicon layer)310。在一个与本发明的原理相一致的实施例中，该无定形硅层310可沉积的厚度大约在100到1000范围内。
接着，如图4所述(步骤115)，可用传统的方法蚀刻该无定形硅层310，在该衬底200结束蚀刻以形成无定形硅间隔(鳍状)结构410。每个无定形硅鳍状结构410高度大约在200到1000范围内，及其宽度大约在100到1000范围内。
如图5所示(步骤120)，可在该半导体器件上沉积介电层510。在一个与本发明的原理相一致的实施例中，该介电层510可沉积的厚度大约在200到1000范围内，该介电层510可包含氧化物或其它介电材料。
如图6所示(步骤120)，可用化学机械抛光(CMP)(或其它技术)对该半导体器件进行抛光，以平坦化该半导体器件的上表面，使得每个无定形硅鳍状结构410的上表面外露。在化学机械抛光过程中，可以移除部分的介电鳍状结构210及无定形硅鳍状结构410的上表面，以外露出每个无定形硅鳍状结构410的上表面。例如，化学机械抛光之后，鳍状210及410的高度大约在150到200范围内。
如图7所示(步骤125)，可在该半导体器件上沉积例如镍的金属层710。在一个实施例中，镍金属层710可沉积的厚度大约20。
接着，可实施金属诱导结晶(MIC)操作。如图8所示(步骤130)，该MIC操作可包括在大约500℃到550℃温度内对该镍金属层710退火几个小时，其作用就是使镍金属扩散到该无定形硅内，使得该鳍状结构410中的无定形硅转变成单晶硅810。作为MIC操作的结果，镍硅(NiSi)化合物薄层820可形成在衬底200与单晶硅鳍状结构810之间。在一个实施例中，该镍硅层820的厚度大约在20到200范围内。
在该单晶硅鳍状结构810形成之后，可利用传统的FinFET制造处理以完成该晶体管(例如形成源极及漏极区)、接触(contact)、互连(interconnect)以及该FinFET器件的层间介电层。例如，该介电层510可被移除，例如像氮化硅或氧化硅的保护介电层，可形成在该鳍状210及810的上表面，接着，在该单晶硅鳍状结构810的侧表面上形成栅极电介质。然后，在该鳍状210及810各自端部形成源极区及漏极区，接着，形成一个或多于一个的栅极。例如，硅层，锗层，硅锗结合层或各式的金属可作为该栅极材料。接着该栅极材料可被图形化并蚀刻以形成栅极电极。例如，图9说明了在形成源极/漏极区与栅极电极之后，按照本发明原理的半导体器件的典型的顶视图。如图所示，该半导体器件包括具有鳍状210及810的双栅极结构、源极及漏极区910及920、以及栅极电极930及940。
然后，根据特定端器件要求，可对该源极/漏极区910及920掺杂n型或p型杂质。此外，根据特殊的电路要求，在该源极/漏极离子注入前可选择性形成侧壁间隔物，以控制源极/漏极结的位置。接着可进行激活退火以激活该源极/漏极区910及920。
已经按照上述的形成许多鳍状结构说明了本发明。应当了解，根据特殊的电路要求，按照本发明的方法可用于形成任意数量的鳍状。
因此，依照本发明的原理，可形成单晶硅鳍状结构，该单晶硅鳍状结构具有位于该单晶硅鳍状结构之间的介电鳍状结构。该介电鳍状结构的材料可加以选择，以在该单晶硅鳍状结构中引起有效应力(应变)，从而达到增强该单晶硅鳍状结构中的迁移率。
(其它实施例)
图10至图15说明在按照本发明原理的替换实施例中形成多个鳍状结构的示意图。参阅图10，工艺可从半导体器件的处理开始，该半导体器件包括形成在衬底1000上的氧化层1010。该衬底1000可包括硅或诸如锗的其它半导体材料，或硅锗的组合半导体材料。该氧化层1010的高度大约在200到1000范围内。
如图10所示，可蚀刻该氧化层1010以形成沟槽(trench)1020。在一个实施例中，该沟槽1020的宽度大约在200到2000范围内。接着如图11所述，可沉积无定形硅并蚀刻该无定形硅以形成无定形硅间隔1110。每个无定形硅间隔1110的宽度大约在100到1000范围内。如图12所述，介电材料1210可沉积在无定形硅间隔1110之间的间隙内。该介电材料可包含氧化物或其它介电材料。
如图13所示，在无定形硅间隔1110的上表面可沉积镍金属层1310。该镍金属层1310的厚度大约为20。接着可实施金属诱导结晶(MIC)操作。如图14所示，该MIC操作可包括在大约500℃到550℃范围内对该镍金属层1310退火数小时，以使该无定形硅间隔1110转变成单晶硅鳍状结构1410。在MIC操作的结果，镍硅化合物(NiSi)薄层1420可形成在衬底1000与单晶硅鳍状结构1410之间。在一个实施例中，该镍硅层1420的厚度大约在20到200范围内。
接着如图15所示，该氧化层1010可用传统方法移除，从而，可产生间隔导入合并的场效应晶体管(spacer-induced-merged FET)。
在另一个实施例中，间隔(spacer)可用于产生窄沟槽(trench)，能够在该沟槽两侧之间提供耦合效应(coupling effect)。如图16所示，半导体器件可包括氧化层1610，该氧化层1610形成于衬底上(未图标)，且硅层1620形成于该氧化层1610上。可沉积诸如氮化硅、氧化硅等材料并图形化该材料，以形成硬掩膜(hard mask)1640。接着可沉积诸如氮化硅(SiN)、氧化硅(SiO)材料或其它材料的间隔材料，并蚀刻该材料以在硬掩膜1640的侧表面形成间隔1630。接着如图17所示，可用该间隔1630及该硬掩膜1640作为屏蔽来蚀刻该硅层1620，以形成窄沟槽1710。该沟槽1710的宽度大约在100到1000范围内。该沟槽1710有利于在位于沟槽1710两侧的鳍状1620间提供耦合效应。
按照本发明原理的实施例提供单晶硅鳍状结构，该结构形成在介电鳍状结构的相对侧上。可选择该介电硅鳍状结构的材料以在该单晶硅材料中引起有效应力。以此方式，能够提高迁移率。
如前所述的本发明的典型实施例提供了说明及描述，但并不详尽或用于将本发明限定至所揭示的精密成形范围。根据上述的技术或从中获得的教导可对本发明做出修改、变更。例如，为了彻底的了解本发明，在上述中，许多特殊细节被提出，例如像特殊的材料，结构，化学物，工艺等。然而，不使用这里所提出的特殊细节，本发明也可被实践。在其它范例中，为了不模糊本发明的要点，众所周知的处理结构未被详细公布。在本发明的实践中，传统的沉积，光刻及蚀刻技术可被应用，因此，在这里，这些技术的细节并没有详细提出。
在按照本发明的其它实施例中，图1中所揭示的一系列步骤次序可加以改变，而且，无相互依赖的步骤可并行实施。
除非在此明确说明，本申请的描述中使用的非元件的、动作或指令，应被解释为本发明的关键的或必要部分。并且，这里所使用的冠词“一(a)”意指包括一项或更多项的措词。在仅意指某一项对象的地方，可使用该冠词“一个(one)”或类似的术语。
本发明的范围如权利要求及其它对等的实施例所定义。

Claims (10)

1.一种半导体器件，包含：
第一鳍状结构(210)，包含介电材料且包括有第一侧表面及第二侧表面；
第二鳍状结构(810)，包含单晶硅材料且形成于邻近该第一鳍状结构(210)的第一侧表面；
第三鳍状结构(810)，包含该单晶硅材料且形成于邻近该第一鳍状结构(210)的第二侧表面；
源极区(910)，形成于该第一鳍状结构(210)、第二鳍状结构(810)及第三鳍状结构(810)的一端；
漏极区(920)，形成于该第一鳍状结构(210)、第二鳍状结构(810)及第三鳍状结构(810)的另一端；以及
至少一个栅极(930，940)。
2.如权利要求1所述的半导体器件，其中该第一鳍状结构(210)的宽度大约在200到1000范围内。
3.如权利要求1所述的半导体器件，其中该介电材料包括氧化物及氮化物的其中之一。
4.如权利要求1所述的半导体器件，其中该第二鳍状结构(810)及第三鳍状结构(810)的各自宽度大约在100到1000范围内。
5.一种制造半导体器件的方法，该半导体器件包括衬底(200)以及形成在该衬底(200)上的介电层(210)，该方法特征在于：
蚀刻该介电层(210)以形成第一鳍状结构(210)；
沉积无定形硅层(310)；
蚀刻该无定形硅层(310)以形成邻近于该第一鳍状结构(210)的第一侧表面的第二鳍状结构(410)以及邻近于该第一鳍状结构(210)的相对边的第二侧表面的第三鳍状结构(410)；
至少在该第二鳍状结构(410)及该第三鳍状结构(410)的上表面上沉积金属层(710)；
实施金属诱导结晶化操作，使该第二鳍状结构(410)及该第三鳍状结构(410)内的无定形硅转变成单晶硅材料；
形成源极区(910)及漏极区(920)；
在该第一、第二及第三鳍状结构(210，810)上沉积栅极材料；以及
图形化并蚀刻该栅极材料以形成至少一个栅极电极(930，940)。
6.如权利要求5所述的方法，其中该介电层(210)包含氧化物及氮化物的至少其中之一。
7.一种半导体器件，包含：
第一鳍状结构(810)，包含单晶硅材料；
第二鳍状结构(810)，包含该单晶硅材料；以及
位于该第一鳍状结构(810)与第二鳍状结构(810)之间的第三鳍状结构(210)，该第三鳍状结构(210)包含介电材料，该第三鳍状结构(210)在该第一及第二鳍状结构(810)中的单晶硅材料中诱发应力。
8.如权利要求7所述的半导体器件，其中该第一鳍状结构(810)及第二鳍状结构(810)的各自宽度大约在100到1000范围内。
9.如权利要求8所述的半导体器件，其中该第三鳍状结构(210)的宽度大约在100到1000范围内。
10.如权利要求9所述的半导体器件，其中该介电材料包含氧化物及氮化物的至少其中之一。
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