CN1779961A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN1779961A
CN1779961A CNA2005101180996A CN200510118099A CN1779961A CN 1779961 A CN1779961 A CN 1779961A CN A2005101180996 A CNA2005101180996 A CN A2005101180996A CN 200510118099 A CN200510118099 A CN 200510118099A CN 1779961 A CN1779961 A CN 1779961A
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China
Prior art keywords
pad electrode
hole
semiconductor substrate
electrode
semiconductor device
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CNA2005101180996A
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CN100429770C (zh
Inventor
龟山工次郎
铃木彰
梅本光雄
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Publication of CN1779961A publication Critical patent/CN1779961A/zh
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Publication of CN100429770C publication Critical patent/CN100429770C/zh
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Abstract

一种具有贯通电极的半导体装置及其制造方法，谋求半导体装置的可靠性及成品率的提高。蚀刻半导体衬底(10)，形成从半导体衬底(10)到达焊盘电极(12)的通孔(16)。在此，上述蚀刻按使通孔(16)底部的开口直径A比焊盘电极(12)的平面宽度C大这样的蚀刻条件进行。其次，在包括该通孔(16)的半导体衬底(10)的背面上形成在通孔(16)底部使焊盘电极(12)露出的第二绝缘膜(17)。然后，形成与在通孔(16)底部露出的焊盘电极(12)电连接的贯通电极(20)及配线层(21)。进而形成保护层(22)、导电端子(23)。最后，通过切割将半导体衬底(10)切断分离为半导体芯片(10A)。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法，特别是涉及具有贯通电极的半导体装置及其制造方法。
背景技术
近年来，作为三维安装技术，或作为新的封装技术，CSP(芯片尺寸封装Chip Size Package)正在受到人们的关注。CSP是指，具有与半导体芯片的外形尺寸大致相同尺寸的外形尺寸的小型封装。
目前，作为CSP之一种，已知有具有贯通电极的BGA型半导体装置。该BGA型半导体装置具有贯通半导体衬底而与焊盘电极连接的贯通电极。另外，该半导体装置在其背面上格子状配置有多个由焊锡等金属部件构成的球状导电端子。
而且，在将该半导体装置组装在电子设备上时，将各导电端子与电路衬底(例如印刷线路板)上的配线图案连接。
这种BGA型半导体装置与具有向侧部突出的引脚的SOP(Small OutlinePackage)或QFP(Quad Flat Package)等其它CSP型半导体装置相比，具有可设置多个导电端子且可小型化这样的优点。
下面概略说明现有例的具有贯通电极的BGA型半导体装置的制造方法。首先，在介由第一绝缘膜形成有焊盘电极的半导体衬底的表面上介由树脂层粘接支承体。另外，支承体只要根据需要粘接即可，而未必一定进行粘接。
然后，通过蚀刻该半导体衬底，形成从半导体衬底的背面到达焊盘电极的通孔。然后，在包括通孔内的半导体衬底的背面上形成在该通孔底部露出焊盘电极的第二绝缘膜。
然后，在通孔内的第二绝缘膜上形成与在该底部露出的焊盘电极电连接的贯通电极。同时，在半导体衬底背面的第二绝缘膜上形成与上述贯通电极连接的配线层。然后，在包括上述配线层上的半导体衬底的背面上形成保护层。也可以将上述保护层的一部分开口，露出上述配线层的一部分，在该配线层上形成导电端子。然后，通过进行切割，将半导体衬底切断分离成多个半导体芯片。
另外，关联的技术文献例如可列举以下专利文献。
专利文献1：特开2003-309221号公报
下面，参照附图说明上述现有例的半导体装置制造方法的一部分工序。图11及图12是表示现有例的半导体装置的制造方法的剖面图。
在现有例的半导体装置中，如图11所示，通过所谓的前工序，在半导体衬底50的表面介由绝缘膜51形成有焊盘电极52。另外，在之后的工序中，在形成有焊盘电极52的半导体衬底50的表面上介由树脂层53粘接有支承体54。在此，对焊盘电极52发明者考察了蓄积了在其成膜时施加的热应力(残留应力或固有应力)的情况。
但是，如图12所示，当以抗蚀剂层55为掩模，蚀刻半导体衬底50，形成贯通该半导体衬底50的通孔56时，该底部的焊盘电极52虽然本来应保持水平状态，但有时被压入通孔56的空间内而弯曲变形。
该焊盘电极52的变形考虑是由于如下应力释放造成的，在前工序成膜焊盘电极52时蓄积在该焊盘电极52上的上述应力由于热循环测试时等的热负荷而失去之前的均衡，从通孔56底部的焊盘电极52集中释放。另外，在蚀刻绝缘膜51后有时也会弯曲。
另外，在于通孔56内的底部与焊盘电极52连接的例如由铜(Cu)构成的未图示的贯通电极形成后，焊盘电极52由该贯通电极向半导体衬底50的背面侧牵拉而弯曲变形。此时的变形考虑是由在形成贯通电极时蓄积于该贯通电极上的残留应力和蓄积于焊盘电极52上的应力的关系而引起。
另外，存在由于上述这种焊盘电极52的变形而在该焊盘电极52上产生金属疲劳造成的损伤或断线的情况。因此，在包括变形的焊盘电极52上的通孔56内形成例如由铜(Cu)构成的未图示的贯通电极后，存在在该贯通电极和于通孔56内露出的焊盘电极之间产生连接不良的情况。即，存在由于上述焊盘电极52的变形使具有贯通电极的半导体装置的可靠性降低的问题。结果是使具有贯通电极的半导体装置的可靠性及成品率降低。
因此，本发明的目的在于，在具有贯通电极的半导体装置及其制造方法中谋求该半导体装置的可靠性及成品率的提高。
发明内容
本发明的半导体装置及其制造方法是鉴于上述课题而构成的，其具有以下特征。即，本发明的半导体装置具有，介由第一绝缘膜形成有焊盘电极的半导体芯片、和从半导体芯片的背面到达该焊盘电极的通孔，通孔底部的开口直径比所述焊盘电极的平面的宽度大。
另外，本发明的半导体装置在上述结构的基础上，通孔的在深度的中途的开口直径比焊盘电极的平面宽度及通孔底部的开口直径小。
本发明的半导体装置在上述结构的基础上，具有：第二绝缘膜，其形成于包括该通孔内的半导体芯片的背面上，在通孔的底部露出焊盘电极；贯通电极，其形成于通孔内的第二绝缘膜上，且与焊盘电极电连接；配线层，其与贯通电极连接，沿半导体芯片背面的第二绝缘膜上延伸形成；保护层，其形成于包括该配线层上的半导体芯片的背面上，使贯通电极及配线层的一部分露出。在此，还可以在配线层的一部分上形成导电端子。
另外，本发明提供一种半导体装置，其特征在于，具有介由第一绝缘膜形成有焊盘电极的半导体芯片、和从所述半导体芯片的背面到达该焊盘电极的通孔，所述通孔底部的开口端部具有不在所述焊盘电极上的区域。
本发明提供一种半导体装置的制造方法，其特征在于，具有：使用掩模对介由第一绝缘膜形成有焊盘电极的半导体衬底进行蚀刻，形成从该半导体衬底背面的对应该焊盘电极的位置贯通到该半导体衬底的该表面的通孔的工序；蚀刻在通孔底部露出的第一绝缘膜而露出焊盘电极的工序，所述形成通孔的工序的半导体衬底的蚀刻，使通孔底部的开口直径比焊盘电极的平面宽度大。
本发明的半导体装置的制造方法在上述工序的基础上，具有：在包括通孔内的半导体衬底的背面上形成在该通孔底部使焊盘电极露出的第二绝缘膜的工序；形成在通孔内与焊盘电极电连接的贯通电极、及与该贯通电极电连接的在半导体衬底背面的第二绝缘膜上延伸的配线层的工序；在包括贯通电极上及配线层上的半导体衬底的背面上形成露出该配线层一部分的保护层的工序；将半导体衬底切割分离成多个半导体芯片的工序。在此，还可以在配线层的一部分上形成导电端子。
另外，本发明的半导体装置的制造方法，通过在所述形成通孔的工序的所述半导体衬底的蚀刻时进行超量蚀刻，使所述通孔底部的开口直径比所述通孔的深度中途的开口直径大。
本发明提供一种半导体装置的制造方法，其特征在于，具有：蚀刻介由第一绝缘膜形成有焊盘电极的半导体衬底，形成从该半导体衬底背面的对应该焊盘电极的位置贯通到该半导体衬底的该表面的通孔的工序；蚀刻在所述通孔底部露出的第一绝缘膜而使焊盘电极露出的工序，形成所述通孔的工序的半导体衬底的蚀刻，使所述通孔底部的开口端部具有不形成在所述焊盘电极上的区域。
根据本发明，由于通孔底部的开口直径比焊盘电极的平面宽度大，故在通孔的底部，可使焊盘电极蓄积的应力(在该焊盘电极成膜时蓄积的应力)比目前更有效地从焊盘电极释放。
因此，可最大限度地抑止在通孔底部露出的焊盘电极的变形。另外，由于可最大限度地抑制在通孔底部露出的焊盘电极的变形，故该焊盘电极和与其连接的贯通电极的接触不良被抑制，贯通电极和焊盘电极的连接可靠性提高。另外，通过在形成通孔的工序中，通过进行超量蚀刻，使焊盘电极附近的通孔底部的开口直径比通孔上部的开口直径宽，因此，焊盘电极和贯通电极的接触面积增大。这样，可提高具有贯通电极的半导体装置的可靠性及成品率。
附图说明
图1是说明本发明实施例的半导体装置的制造方法的剖面图；
图2是说明本发明实施例的半导体装置的制造方法的剖面图；
图3是说明本发明实施例的半导体装置的制造方法的剖面图；
图4是说明本发明实施例的半导体装置的制造方法的剖面图；
图5是说明本发明实施例的半导体装置的制造方法的剖面图；
图6是说明本发明实施例的半导体装置的制造方法的剖面图；
图7是说明本发明实施例的半导体装置的制造方法的剖面图；
图8是说明本发明实施例的半导体装置的制造方法的剖面图；
图9是说明本发明实施例的半导体装置及其制造方法的剖面图；
图10(a)、(b)、(c)是表示本发明的焊盘电极和通孔的位置关系的图；
图11是表示现有例的半导体装置的制造方法的剖面图；
图12是表示现有例的半导体装置的制造方法的剖面图。
具体实施方式
下面，参照附图说明本发明实施例的半导体装置的制造方法。图1～图9是表示本实施例的半导体装置的制造方法的剖面图。另外，图1～图9表示了在半导体衬底中未图示的切割线的附近。
首先，如图1所示，准备在表面形成有未图示的电子器件的半导体衬底10。在此，未图示的电子器件例如为CCD(Charge Coupled Device)、红外线传感器等光接收元件、或发光元件。或，未图示的电子器件也可以为除上述光接收元件及发光元件以外的电子器件。另外，半导体衬底10由例如硅衬底构成，但也可以为其它材质的衬底。另外，半导体衬底10优选具有约130μm的膜厚。
其次，在含有未图示的电子器件的半导体衬底10的表面上形成第一绝缘膜11作为层间绝缘膜。第一绝缘膜11例如由P-TEOS或BPSG膜等构成。另外，第一绝缘膜11优选形成约0.8μm的膜厚。
另外，在半导体衬底10的表面形成有与未图示的电子器件连接的外部连接用电极即焊盘电极12。焊盘电极12介由第一绝缘膜11形成于半导体衬底10的表面。焊盘电极12例如由铝(Al)构成，优选具有约1μm的膜厚。此时，焊盘电极12保持水平状态成膜，但对应其成膜时的条件会将规定大小的应力蓄积于焊盘电极12上。
以上所述未图示的电子器件、第一绝缘膜11及焊盘电极12在半导体装置的制造工序中的所谓前工序中形成。
其次，根据需要，要在半导体衬底10的表面介由树脂层13粘接支承体14。在此，在未图示的电子器件为光接收元件或发光元件时，支承体14通过例如玻璃这种具有透明或半透明性状的材料粘接。在未图示的电子器件不是光接收元件或发光元件时，支承体14也可以由不具有透明或半透明性状的材料形成。另外，支承体14也可以为锥状。也可以将该支承体14在之后的工序中除去。或，也可以不除去支承体14而将其保留。或省略支承体14的粘接。
其次，如图2所示，在半导体衬底10的背面上选择性地形成第一抗蚀层15。即，第一抗蚀层15在半导体衬底10的背面上对应焊盘电极12的位置具有开口部。
其次，以该第一抗蚀层15为掩模，优选利用干式蚀刻法蚀刻半导体衬底10。在此，上述蚀刻按使通孔16底部的开口直径A比焊盘电极12的平面宽度C大这样的蚀刻条件进行。另外，进一步说，上述蚀刻也可以以如下蚀刻条件进行，该蚀刻条件是：使从通孔16背面侧的开口部到通孔16的深度中途的开口直径B比该通孔16底部的开口直径A及焊盘电极12的平面宽度C小。
例如，蚀刻气体使用含有SF6、O2、C4F8等的气体。而且，在使用SF6或O2作为蚀刻气体时，其蚀刻条件优选例如，其功率约为1.5KW，气体流量为300/30sccm，压力为25Pa。
这样，通过上述蚀刻，在焊盘电极12上从半导体衬底10的背面贯通到其表面的通孔具有以下所示的特征。即，在通孔16的底部，第一绝缘膜11露出。另外，通过在合理蚀刻后继续进行进一步蚀刻，使构成侧面的半导体衬底10的硅进一步被蚀刻，从而形成如图2所示的底部宽的形状的通孔16，使通孔16底部的开口直径A比焊盘电极12的平面宽度C大。此时，观察在通孔16的底部与第一绝缘膜11邻接的焊盘电极12时，其整个面(与通孔16对向一侧的面)介由第一绝缘膜11与通孔16的空间对峙。
这样与上述焊盘电极12对峙的通孔16的空间的面积比现有例中半导体装置的与焊盘电极52对峙的通孔56的空间的面积大。因此，在焊盘电极12成膜时蓄积于该焊盘电极12上的应力在通孔16的底部比现有例更有效地被释放。因此，可最大限度地抑制如现有例那样焊盘电极12被压向通孔16的空间而弯曲变形的情况。另外，由于开口端部不在焊盘电极12上，故可防止以该开口端部为支点的焊盘电极12的变形，因此，可最大限度地抑制在焊盘电极12上产生金属疲劳造成的损伤或断线。
其次，如图3所示，以第一抗蚀层15为掩模，选择性地除去在通孔16底部露出的第一绝缘膜11的一部分。由此，在通孔16的底部使焊盘电极12的一部分露出。然后，除去第一抗蚀层15。
其次，如图4所示，在包括通孔16内的半导体衬底10的背面上形成第二绝缘膜17。第二绝缘膜17由例如氧化硅膜(SiO2膜)或氮化硅膜(SiN膜)构成，通过例如等离子CVD法形成。另外，第二绝缘膜17优选具有约1μm～2μm的膜厚。
其次，如图5所示，优选利用各向异性干式蚀刻从半导体衬底10的背面侧进行第二绝缘膜17的蚀刻。在此，通孔16底部的第二绝缘膜17对应该通孔16的深度形成比半导体衬底10背面上的第二绝缘膜17薄。因此，通过上述蚀刻，在通孔16的底部除去第二绝缘膜17，使焊盘电极12的一部分露出，在半导体衬底10的背面上及通孔16的侧部留下第二绝缘膜17。
其次，如图6所示，在通孔16内及半导体衬底10背面的第二绝缘膜17上形成势垒金属层18。势垒金属层18例如由钨化钛(TiW)层、氮化钛(TiN)层或氮化钽(TaN)层等金属层构成。
势垒金属层18例如通过喷溅法、CVD法、无电解镀敷法、或其它成膜方法形成。
在该势垒金属层18上形成未图示的籽晶层。该籽晶层构成用于镀敷形成后述的配线形成层20A的电极，例如由铜(Cu)等金属构成。
另外，在通孔16侧壁的第二绝缘膜17由氮化硅膜(SiN膜)形成时，由于该氮化硅膜(SiN膜)对铜扩散构成势垒，故也可以将势垒金属层18省略。
其次，覆盖形成于半导体衬底10背面上的势垒金属层18及籽晶层形成配线形成层20A。在此，上述配线形成层20A是通过例如电解镀敷法，由例如铜(Cu)构成的金属层。
然后，如图7所示，在上述配线形成层20A上的规定区域形成第二抗蚀层19。然后，以上述第二抗蚀层19为掩模，对上述配线形成层20A进行构图，形成贯通电极20及与该贯通电极20连续并电连接的配线层21。将镀膜厚调整为将贯通电极20不完全地埋入通孔16内的厚度。或也可以将贯通电极20完全埋入通孔16内。另外，形成上述第二抗蚀层19的上述规定的区域是指，包括通孔16的形成区域的区域，且是具有后述的形成规定图案的配线层21的半导体衬底10背面上的区域。
在此，贯通电极20介由籽晶层及势垒金属层18与在通孔16底部露出的焊盘电极12电连接。另外，与贯通电极20连续的配线层21介由籽晶层及势垒金属层18在半导体衬底10的背面上以规定的图案形成。然后，在除去上述第二抗蚀层19后，以上述配线层21及籽晶层为掩模，构图除去上述势垒金属层18。
另外，上述的贯通电极20和配线层21也可以分别由不同的工序形成。另外，贯通电极20及配线层21的形成也可以不利用上述的使用铜(Cu)的电解镀敷法，而利用其它的金属及成膜方法形成。例如，贯通电极20及配线层21也可以由铝(Al)或铝合金等构成，例如使用喷溅法形成。此时，在包括通孔16的半导体衬底10的背面上形成未图示的势垒金属层后，在除通孔16的形成区域外的该势垒金属层上的规定区域形成未图示的抗蚀层。然后，也可以以该抗蚀层为掩模，通过喷溅法形成由上述金属构成的贯通电极及配线层。或，也可以通过CVD法形成贯通电极20及配线层21。
其次，如图8所示，在包括通孔16内的半导体衬底10的背面上，即第二绝缘膜17上、贯通电极20上及配线层21上将它们覆盖形成由例如抗蚀材料等构成的保护层22。在保护层22中对应配线层21的位置设置开口部。然后，在该开口部露出的配线层21上形成由例如焊锡等金属构成的球状的导电端子23。
其次，如图9所示，沿未图示的切割线切割该半导体衬底10。由此，完成由具有贯通电极20的半导体芯片10A构成的多个半导体装置。
如上所述，根据本实施例的半导体装置及其制造方法，可制造通孔16底部的开口直径A比焊盘电极12的平面宽度C大的半导体装置。因此，在通孔16的底部，可比现有例更有效地释放焊盘电极12蓄积的应力(该焊盘电极成膜时蓄积的应力)。
因此，可最大限度地抑止在通孔16底部露出的焊盘电极12的变形。另外，由于可最大限度地抑制在通孔16底部露出的焊盘电极12的变形，故该焊盘电极12和与其连接的贯通电极20的连接不良被抑制，贯通电极20和焊盘电极12的连接的可靠性提高。结果可提高具有贯通电极20的半导体装置的可靠性及成品率。
另外，上述的实施例不限于形成导电端子23。即，只要贯通电极20及配线层21可与未图示的电路衬底电连接，则导电端子23不必一定形成。例如，在半导体装置为LGA(Land Grip Array)型半导体装置的情况下，不必在从保护层22局部露出的配线层21的一部分上形成导电端子23。
上述的实施例不限于形成配线层21。即，在将贯通孔20完全埋入通孔16内形成的情况下，不必一定形成配线层21。例如，该贯通电极20也可以与未图示的电路衬底直接连接，而不介由配线层21及导电端子23。或，贯通电极20也可以在通孔16的开口部露出的该贯通电极20上具有导电端子23，并介由该导电端子23与未图示的电路衬底连接，而不介由配线层21。
另外，图10是表示本发明的焊盘电极12和通孔16的位置关系的平面图，图10(a)表示通孔16的开口直径比焊盘电极12a的宽度大的例子，图10(b)、(c)是通孔16的开口端部具有不位于焊盘电极12上的区域的例子，表示具有开口直径比焊盘电极12b的宽度大的区域和窄的区域的例子，图10(c)表示在一个焊盘电极12c上开设多个通孔16的例子。在现有的半导体装置中，焊盘电极12以位于焊盘电极上的开口端部为支点开始弯曲，因此，该位置的拉伸度增大，但在本发明中，由于构成这种弯曲的支点的开口端部不在焊盘电极12上，故弯曲被抑止。
如图10(b)、(c)所示，即使在通孔16的开口端部具有不存在于焊盘电极12b、12c上的区域的情况下，即，如图10(a)所示，即使不将焊盘电极12a整体利用开口而开放，也可以抑制焊盘电极12的弯曲。这样，在本发明中，通过至少开口端部具有在焊盘电极12上没有的区域，也可以降低上述弯曲的产生，可提高半导体装置的可靠性。

Claims (10)

1、一种半导体装置，其特征在于，具有介由第一绝缘膜形成有焊盘电极的半导体芯片、和从半导体芯片的背面到达该焊盘电极的通孔，所述通孔底部的开口直径比所述焊盘电极的平面的宽度大。
2、如权利要求1所述的半导体装置，其特征在于，所述通孔深度的中途的开口直径比所述焊盘电极的平面宽度及所述通孔底部的开口直径小。
3、如权利要求1或2所述的半导体装置，其特征在于，具有：第二绝缘膜，其形成于包括所述通孔内的所述半导体芯片的背面上，且在该通孔的底部露出所述焊盘电极；贯通电极，其形成于所述通孔内的第二绝缘膜上，且与所述焊盘电极电连接；配线层，其与所述贯通电极电连接，在所述半导体芯片背面的第二绝缘膜上延伸形成；保护层，其形成于包括所述贯通电极上及所述配线层上的半导体芯片的背面上，使所述配线层的一部分露出。
4、如权利要求3所述的半导体装置，其特征在于，在所述配线层的一部分上具有导电端子。
5、一种半导体装置，其特征在于，具有介由第一绝缘层形成有焊盘电极的半导体芯片、和从所述半导体芯片的背面到达该焊盘电极的通孔，所述通孔底部的开口端部具有不在所述焊盘电极上的区域。
6、一种半导体装置的制造方法，其特征在于，具有：对介由第一绝缘膜形成有焊盘电极的半导体衬底进行蚀刻，形成从该半导体衬底背面的对应该焊盘电极的位置到达该半导体衬底的该表面的通孔的工序；蚀刻在所述通孔底部露出的第一绝缘膜，使焊盘电极露出的工序，形成所述通孔的工序的半导体衬底的蚀刻，使所述通孔底部的开口直径比所述焊盘电极的平面宽度大。
7、如权利要求6所述的半导体装置的制造方法，其特征在于，具有：在包括所述通孔内的所述半导体衬底的背面上形成在该通孔底部使所述焊盘电极露出的第二绝缘膜的工序；形成在所述通孔内与所述焊盘电极电连接的贯通电极、及与该贯通电极电连接且在所述半导体衬底背面的第二绝缘膜上延伸的配线层的工序；在包括所述贯通电极上及所述配线层上的所述半导体衬底的背面上形成使该配线层的一部分露出的保护层的工序；将所述半导体衬底切割分离成多个半导体芯片的工序。
8、如权利要求7所述的半导体装置的制造方法，其特征在于，具有在所述配线层的一部分上形成导电端子的工序。
9、如权利要求6所述的半导体装置的制造方法，其特征在于，通过在形成所述通孔的工序的所述半导体衬底蚀刻时进行超量蚀刻，使所述通孔底部的开口直径比所述通孔的深度中途的开口直径大。
10、一种半导体装置的制造方法，其特征在于，具有：蚀刻介由第一绝缘膜形成有焊盘电极的半导体衬底，形成从该半导体衬底背面的对应该焊盘电极的位置贯通到该半导体衬底的该表面的通孔的工序；蚀刻在所述通孔底部露出的第一绝缘膜使焊盘电极露出的工序，形成所述通孔的工序的半导体衬底的蚀刻，使所述通孔底部的开口端部具有不形成在所述焊盘电极上的区域。
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