CN1783484A - 金属氧化物半导体场效应晶体管和肖特基二极管结合的瘦小外形封装 - Google Patents

金属氧化物半导体场效应晶体管和肖特基二极管结合的瘦小外形封装 Download PDF

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CN1783484A
CN1783484A CN200410084702.9A CN200410084702A CN1783484A CN 1783484 A CN1783484 A CN 1783484A CN 200410084702 A CN200410084702 A CN 200410084702A CN 1783484 A CN1783484 A CN 1783484A
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mosfet
lead
schottky diode
wire
utmost point
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CN100359686C (zh
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施震宇
汪利民
石磊
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Nixi Semiconductor Technology Shanghai Co ltd
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All Time Semiconductor Component (shanghai) Co Ltd
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Priority to US11/792,010 priority patent/US8089139B2/en
Priority to PCT/CN2005/001658 priority patent/WO2006058477A1/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

本发明提供一种MOSFET和肖特基二极管结合的瘦小外形封装，其包含MOSFET S极，MOSFET G极，MOSFET D极，肖特基二极管的K极和A极，该MOSFET的D极与肖特基二极管的A极位于同一侧；还包含一引线框架，该引线框架包含第一引线为肖特基二极管的K极，与肖特基二极管的第二载片台相连；第四引线为MOSFET的D极，其和MOSFET的第一载片台相连；MOSFET的D极与肖特基二极管的K极位于相对的两侧。本发明使MOSFET的D极与肖特基二极管的K极位于封装器件的同一侧，简化外部输出的结构，缩短电流路径，有效提升了电源的效率，降低设计的复杂程度，延长电池的使用时间。

Description

金属氧化物半导体场效应晶体管和肖特基二极管结合的瘦小外形封装
技术领域
本发明涉及一种瘦小外形封装，具体地说，是涉及一种金属氧化物半导体场效应晶体管(MOSFET)与肖特基二极管(Shottky Diode)结合的瘦小外形封装(TSOP，Thin Small Outline Package)。
背景技术
DC-DC的电源转换器(图1)应用于便携式电子产品显得越来越重要。现有技术中的瘦小外形金属氧化物半导体场效应晶体管20’(MOSFET)与肖特基二极管30’(Shottky Diode)结合的封装使用双芯片引线框架10’，如图2所示，其第一引线1’为肖特基二极管30’的A极，呈T形结构；第二引线2’为MOSFET S极，呈I形结构；第三引线3’为MOSFET G极，呈T形结构；第四引线4’为MOSFET D1极，与MOSFET的第一载片台11’相连；第五引线5’为N/A极，呈I形结构；第六引线6’为肖特基二极管K极，与肖特基二极管的第二载片台12’相连。
上述封装作为一种电池和适配器之间的保护开关被广泛使用。然而，在使用此封装作为DC-DC的电源转换器时，会有如下问题。如图3所示，为该瘦小外形封装引线框架应用于便携式电子产品的DC-DC的电源转换器的实施方式，其具体内部电路图见图1。电流由电感L(图1中的40’)流向第一引线1’(肖特基二极管的A极)，即外部电流，后经肖特基二极管(图1中的30’)流向第六引线6’(肖特基二极管的K极)，即内部电流，然后流向外设输出(如图3中红色线条标识)。可以看出，应用此结构，外部电流的路径很长，而电源转换器的效率和电流路径的长短有关。电流路径越长，电源转换器的效率越低。同时也增加了电源转换器的设计复杂程度。
发明内容
本发明提供一种瘦小外形封装，其使MOSFET的D极与肖特基二极管的A极位于封装器件的同一侧，以简化外部输出的结构，缩短电流路径，有效的提升了电源的效率，降低设计的复杂程度，延长电池的使用时间。
为达到上述目的，本发明提供一种瘦小外形封装，其包含一引线框架，该引线框架包含第二引线为MOSFET的S极；第三引线为MOSFET的G极，第四引线为MOSFET的D1极，第五引线为空置或MOSFET的D2极，该D2极可做为MOSFET备用的D极；第四引线D1极和MOSFET的第一载片台相连，特点是，其MOSFET的D极与肖特基二极管的A极位于封装器件的同一侧，具体表现为：其第一引线为肖特基二极管的K极，与肖特基二极管的第二载片台相连，第六引线为肖特基二极管的A极；这样，在实际应用过程中，电源转换器的电流路径就大大缩短了，从而提高电源转换器的效能。且降低了外部印刷线路板(PCB)的排线的复杂程度。
所述的第六引线A极呈T形结构；
所述第二引线的打线区域为L形，有利于提供结构强度，同时也增大了打线面积；
所述第五引线和MOSFET的第一载片台相连，这样有利于散热，提高结构强度。
所述的第六引线的打线区域可加长，这样有利于结构稳定并可增加打线数量。
附图说明
图1为背景技术内部的具体应用的电路示意图；
图2为背景技术瘦小外形封装引线框架的结构示意图；
图3为背景技术瘦小外形封装引线具体应用的示意图；
图4为本发明6脚瘦小外形封装引线框架的结构示意图；
图5为本发明6脚瘦小外形封装引线具体应用的示意图；
图6为本发明内部的具体应用的电路示意图。
具体实施方式
以下根据图4和图5，以MOSFET和肖特基二极管结合的6脚瘦小外形封装为例，说明本发明的一种较佳实施方式。
本发明提供的MOSFET和肖特基二极管结合的6脚瘦小外形封装，其包含一引线框架10，如图4所示，为本发明提供的6脚瘦小外形封装引线框架10的结构示意图；其包含第二引线2为MOSFET的S极；第三引线3为MOSFET的G极，第四引线4为MOSFET的D1极，第五引线5为空置或MOSFET的D2极(该第五引线也可以视不同的工作场合省略)；第四引线4为MOSFET的D1极和MOSFET(如图6所示20)的第一载片台11相连，且第四引线4为MOSFET的D极与第六引线6，即肖特基二极管的A极位于封装器件的同一侧，该引线框架还包含第一引线1为肖特基二极管(如图6所示30)的K极，与肖特基二极管(如图6所示30)的第二载片台12相连。
所述的第六引线6，肖特基二极管的A极呈T形结构；第二引线2，MOSFET的S极的打线区域为L形，有利于提供结构强度，同时也增大了打线面积；所述第五引线5和MOSFET的第一载片台11相连，这样有利于散热，提高结构强度。同时，第六引线6的打线区域可加长，这样有利于该封装器件的结构稳定并可增加打线数量。
如图5所示，为本发明6脚瘦小外形封装引线具体应用的示意图。电感(如图6所示40)电流(即外部电流)流经第六引线A极，以最短路径流出肖特基二极管(如图6所示30)的K极，即为内部电流(如图5中红色线条标识)。可以看出，应用此结构，外部电流的路径有效缩短，有效的提升了电源的效率。也降低了设计复杂程度，延长电池的使用时间。
上述实施方式只是用于更好的说明本发明，而不是限定本发明的范围，例如第5引线可以省略或是第4，5和6引线可以在封装的外部或内部相连，或者MOSFET的G极和S极位置互换。本发明的范围以权利要求书界定的范围为准。

Claims (10)

1.一种MOSFET和肖特基二极管结合的瘦小外形封装，其包含MOSFET S极，MOSFET G极，MOSFET D极，肖特基二极管的K极和A极，特征在于，MOSFET的D极与肖特基二极管的A极位于同一侧。
2.如权利要求1所述的MOSFET和肖特基二极管结合的瘦小外形封装，其特征在于，还包含一引线框架，
该引线框架包含第一引线(1)为肖特基二极管的K极，与肖特基二极管的第二载片台(12)相连；
第四引线(4)为MOSFET的D极，其和MOSFET的第一载片台(11)相连；
MOSFET的D极与肖特基二极管的A极位于该封装引线伸出端的同一侧。
3.如权利要求2所述的MOSFET和肖特基二极管结合的瘦小外形封装，其特征在于，该引线框架还包含一第五引线，该第五引线(5)和MOSFET的第一载片台(11)相连。
4.如权利要求2或3所述的MOSFET和肖特基二极管结合的瘦小外形封装，其特征在于，该引线框架还包含一第六引线，该第六引线(6)为MOSFET的D极，和MOSFET的第一载片台(11)内部相连。
5.如权利要求4所述的MOSFET和肖特基二极管结合的瘦小外形封装，其特征在于，所述的第四、五和六引线最少有二者在封装器件内部或外部相连。
6.如权利要求2所述的MOSFET和肖特基二极管结合的瘦小外形封装，其特征在于，还包含第二引线，该第二引线(2)的打线区域为L形。
7.如权利要求4所述的MOSFET和肖特基二极管结合的瘦小外形封装，其特征在于，所述的第六引线(6)呈T形结构。
8.如权利要求4所述的MOSFET和肖特基二极管结合的瘦小外形封装，其特征在于，所述的第六引线(6)的打线区域加长。
9.如权利要求6所述的MOSFET和肖特基二极管结合的瘦小外形封装，其特征在于，所述的第二引线(2)为MOSFET的S极，或是MOSFET的G极。
10.如权利要求3所述的MOSFET和肖特基二极管结合的瘦小外形封装，其特征在于，第五引线可以省略。
CNB2004100847029A 2004-11-30 2004-11-30 金属氧化物半导体场效应晶体管和肖特基二极管结合的瘦小外形封装 Expired - Fee Related CN100359686C (zh)

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CNB2004100847029A CN100359686C (zh) 2004-11-30 2004-11-30 金属氧化物半导体场效应晶体管和肖特基二极管结合的瘦小外形封装
US11/792,010 US8089139B2 (en) 2004-11-30 2005-10-09 Small outline package in which MOSFET and Schottky diode being co-packaged
PCT/CN2005/001658 WO2006058477A1 (fr) 2004-11-30 2005-10-09 Emballage externe mince et compact renfermant un mosfet et une diode schottky

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US8089139B2 (en) 2012-01-03
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