CN1783496A - 将应力施加到pfet和nfet晶体管沟道以改善性能的结构和方法 - Google Patents
将应力施加到pfet和nfet晶体管沟道以改善性能的结构和方法 Download PDFInfo
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Abstract
提供了一种半导体器件结构，它包括第一半导体器件；第二半导体器件；以及排列在第一和第二半导体器件二者上的单一应力膜。此应力膜具有重叠第一半导体器件的第一部分，此第一部分将第一幅度的压应力赋予第一半导体器件的导电沟道，此应力膜还具有重叠第二半导体器件的第二部分，此第二部分不将第一幅度的压应力赋予第二半导体器件的导电沟道，第二部分包括不存在于第一部分中的离子浓度，致使第二部分将幅度比第一幅度小得多的压应力、零应力、以及张应力之一赋予第二半导体器件的导电沟道。
Description
技术领域
本发明涉及到半导体集成电路的制造，更确切地说是涉及到制作应变沟道互补金属氧化物半导体(CMOS)晶体管的装置和方法。
背景技术
理论和实验研究都已经显示，当幅度足够的应力被施加到晶体管的导电沟道以在其中产生应变时，能够大幅度提高载流子在晶体管中的迁移率。应力被定义为单位面积的力。应变是一种无量纲的量，被定义为个体特定尺度与该个体初始尺度相关的单位改变，例如百分比改变。应变的一个例子是当力沿该个体尺度的方向例如沿其长度的方向被施加时，长度相对于原来长度的改变。应变可以是伸张的或压缩的。在p型场效应晶体管中，纵向压应力的施加，亦即沿导电沟道长度方向的压应力的施加，在导电沟道中产生应变，已知会提高PFET的驱动电流。但若同样的压应力被施加到NFET的导电沟道，则其驱动电流减小。然而，当张应力被施加到n型场效应晶体管(NFET)时，NFET的驱动电流提高。
因此，已经提出借助于将纵向张应力施加到NFET的导电沟道来提高NFET的性能，同时借助于将纵向压应力施加到导电沟道来提高PFET的性能。已经提出了几种方法，来将不同种类的应力施加到包含NFET和PFET的晶片的不同区域。在一个例子中，借助于改变排列在FET导电沟道邻近的浅沟槽隔离区(STI)中的材料，以便对其施加所希望的应力来控制机械应力。其它的建议集中在对存在于间隔物特征中的本征应力进行调制。还有一些建议集中在引入诸如包括氮化硅的腐蚀停止层。
发明内容
根据本发明的一种情况，提供了一种半导体器件结构，它包括第一半导体器件；第二半导体器件；以及排列在第一和第二半导体器件二者上的单一应力膜。此应力膜具有重叠第一半导体器件的第一部分，此第一部分将第一幅度的压应力赋予第一半导体器件的导电沟道，此应力膜还具有重叠第二半导体器件的第二部分，此第二部分不将第一幅度的压应力赋予第二半导体器件的导电沟道，第二部分包括不存在于第二部分中的离子浓度，致使第二部分将幅度比第一幅度小得多的压应力、零应力、以及张应力之一赋予第二半导体器件的导电沟道。
在一个实施方案中，第一和第二半导体器件分别包括p型场效应晶体管(PFET)和n型场效应晶体管(NFET)。在一个优选实施方案中，第二应力膜被排列在第一应力膜上，并重叠PFET和NFET二者。一个中间层被提供成在第一与第二应力膜之间重叠PFET，但不重叠NFET。由于插入了中间层，故第二应力膜将张应力赋予NFET的导电沟道，但不赋予PFET的导电沟道。
附图说明
图1示出了根据本发明一个实施方案的一种结构，它包括PFET和NFET。
图2A-10示出了根据本发明一个实施方案的制造PFET和NFET过程中的各个阶段。
具体实施方式
图1是剖面图，示出了本发明的一个实施方案。如图1所示，示出了一个单晶半导体区14，其中提供了诸如互补金属氧化物半导体(CMOS)电路的NFET 10和PFET 20之类的二个半导体器件。NFET和PFET被浅沟槽隔离(STI)区50分隔开。如早先所述，施加到晶体管沟道区的适当的应力能够显著地提高载流子迁移率，导致改进了的性能。如图1所示，单一的应力膜900被排列在PFET 20和NFET10二者上，以便将应力赋予各个晶体管。
在图1所示的示例性结构中，单一应力膜900包括二个部分，亦即，将第一幅度的压应力赋予PFET 20的导电沟道91的第一部分901以及重叠NFET 10的第二部分902。虽然第二部分902与第一部分901都是相同的单一应力膜900的一部分，但第二部分不将第一幅度的压应力赋予NFET 10的导电沟道92。这是因为第二部分902包括不存在于第一部分中的离子浓度。此离子浓度使第二部分902具有不同幅度的应力，甚至不同类型的应力亦即张应力。第二部分902具有幅度比第一幅度小得多的压应力、零应力、或张应力。举例来说，在本发明的一个实施方案中，单一应力膜900主要由诸如氮化硅之类的氮化物组成，且第二部分中的离子浓度包括锗(Ge)离子。
在图1所示的优选实施方案中，第二应力膜990被排列在单一应力膜的第一部分901和第二部分902上。第二应力膜990是张应力膜，将张应力赋予NFET 10的导电沟道。于是，第二应力膜被同时排列在应力膜900的压应力的第一部分901上和第二部分902上。为了第二张应力膜990不影响由下方压应力第一部分901施加到PFET的压应力，中间层550被排列在PFET 20上，以便将第二膜与下方单一应力膜的压应力部分901分隔开足够的距离。中间层550被排列在第一应力膜900上，但仅仅重叠PFET 20而不重叠NFET 10。
第二应力膜990可以由各种材料组成。在一个优选实施方案中，第二应力膜990主要由诸如氮化硅之类的氮化物组成。在一个实施方案中，中间层550的厚度为100-300埃，且包括共形介质材料，层550优选包括诸如二氧化硅之类的氧化物。
此结构还包括介质填料1000以及导电通道1100和1102，导电通道1100与重叠NFET 10和PFET 20的源和漏区24的硅化物区32接触，导电通道1102与NFET和PFET的栅导体的硅化物区28接触。
于是，在所示结构中，永久性张应力和压应力被分别施加到NFET和PFET，以改善各自的性能。由于张应力和压应力二者都被施加到其中排列NFET和PFET的晶片的局部区域，故能够施加高水平的应力。
如稍后要描述的那样，施加到个区域的应力的幅度可以由膜厚度和离子注入的特性来控制。结构12的优点在于，在其中制作PFET和NFET的晶片的各个区域之间，晶片的形貌更一致。这是由于诸如反应离子刻蚀(RIE)工艺之类的有限的工艺被应用于此结构以便形成应力膜，且比较薄的氧化物层被用作应力膜之间的中间层而造成的。
图1所示NFET 10和PFET 20由衬底16形成。衬底16可以是体衬底，或更优选是诸如绝缘体上硅(SOI)衬底之类的绝缘体上半导体衬底，其中，半导体的比较薄的单晶半导体区14如所示被形成在绝缘层18上。当场效应晶体管(FET)被制作在这种SOI衬底中时，由于晶体管的沟道区与体衬底之间的结电容被消除，故常常得到更快速的开关工作。硅的单晶半导体区14被优选提供作为绝缘层上半导体。
此处参照了沟道区排列在衬底的单晶硅区内的NFET和PFET晶体管。但本发明不局限于在纯硅晶体中制造晶体管。可以主要由诸如硅锗之类的半导体合金取代硅来组成单晶半导体区14。本发明的论述还被理解为用来在其它类型的半导体材料中制造晶体管，例如在诸如组分为AlAInBGaCAsDPENF的III-V族化合物半导体之类的半导体材料中，其中，A、B、C、D、E、F表示半导体晶体中各个元素Al、In、Ga、As、P、N的百分比，此百分比加起来为百分之百。砷化镓(GaAs)、磷化铟(InP)、氮化镓(GaN)、以及InGaAsP，是这种半导体的普通例子。
继续参照图1，NFET和PFET的栅导体具有根据各种晶体管所需的功函数而提供的掺杂剂类型和浓度。PFET的栅导体是p+掺杂的，例如用硼，而NFET的栅导体是n+掺杂的，例如用磷或砷。借助于对栅导体的多晶硅下层26进行重掺杂，优选掺杂到大约每立方厘米1018-1020的浓度，来达到这一点。
各个栅导体优选包括排列在多晶硅部分26上的低阻部分28。低阻部分28的电阻比多晶硅部分26的低得多，低阻部分优选包括金属、金属硅化物、或二者。在一个优选实施方案中，低阻部分28包括由自对准工艺形成的硅化物(“salicide”)，它是一种诸如但不局限于镍、钨、钛、钴之类的硅化物前体金属的导电硅化物。此硅化物更优选是一种钴的化合物(CoSi2)。或者，各个栅导体可以包括诸如已经完成晶体管源和漏区的高温加工之后形成作为代替栅是金属层之类的代替多晶硅层26的金属层。
NFET 10包括沟道区92，而PFET包括沟道区91，二种沟道区都排列在各自栅导体28的下方，其间用栅介质27分隔开。栅介质27优选包括从单晶半导体区14表面热生长的二氧化硅层。
NFET和PFET还包括排列在栅导体侧壁上的第一间隔物40。间隔物40优选由共形淀积的诸如氧化物例如二氧化硅或例如氮化硅的氮化物之类的介质材料组成。
晕环和延伸区22被排列在栅导体26邻近，它们的位置决定于间隔物40的厚度。第二间隔物30被排列在第一间隔物40的侧壁上。各个晶体管还包括排列在栅导体二侧上的源和漏区24，源和漏区的位置决定于第一和第二间隔物30和40的组合厚度。
图2A-10示出了根据本发明一个实施方案制造结构12过程中的各个阶段。图2A示出了多晶硅栅导体(GC)层26被形成为重叠衬底16单晶半导体区14的NFET器件区15和PFET器件区17的阶段。为了便于说明，从图2A-10中省略了绝缘层18和绝缘层下方的衬底16部分。多晶硅GC层26被优选为热生长在单晶半导体区14表面上的氧化物的栅介质27分隔于各个器件区15和17。如上所述，栅导体的功函数掺杂优选已经由此制造阶段提供了。还提供了间隔物40，并在此阶段已经提供了浅沟槽隔离区50。
如图2B所示，用离子注入方法，利用多晶硅GC层26和间隔物40作为决定注入区边沿的掩模，延伸和晕环区22被形成在NFET和PFET二者器件区15和17内。当对NFET器件区15执行注入时，用形成在PFET器件区上的掩模来防止PFET器件区17被注入。当对PFET器件区17执行注入时，用形成在NFET器件区上的掩模来防止NFET器件区15被注入。
然后，如图3所示，第二间隔物30被形成在第一间隔物40的侧壁上。然后，以相似于执行晕环和延伸注入的方式，执行离子注入，以便确定NFET和PFET的源和漏区24。
然后，如图4所示，硅化物区28和32被形成为重叠晶体管的栅导体26以及源和漏区。优选借助于淀积硅化物前体，使之与下方硅金属反应，然后通过例如湿法清洗工艺清除剩余的任何不反应的金属，以自对准的方式，来形成这些硅化物区。这一步骤的结果是完全制作了NFET 10和PFET 20。
在图5中，单一的压应力膜500被形成在PFET 20和NFET 10上。如图5所示，膜500优选由诸如氮化硅之类的氮化物组成。膜500的厚度及其淀积参数优选被选择成达到特定的应力幅度。
然后，优选为不受应力的中间膜550，被淀积在此结构上。膜550的性质优选是介质层而不是导电的或半导电的，且优选与下方形貌轮廓共形。膜550优选包括氧化物，优选是二氧化硅，且例如能够从诸如原硅酸四乙酯(TEOS)前体之类的低温淀积来形成这种层。在一个优选实施方案中，此层的厚度为50-150埃。
然后，如图6所示，PFET 20被掩蔽，同时执行一个步骤来清除重叠NFET 10的中间膜550。
图7示出了中间膜550从NFET 10被清除之后的结构。如所示，对下方氮化物膜500有选择性的腐蚀技术，被用来从重叠NFET 10的区域清除氧化物膜550。
然后，如图8所示，暴露的和重叠NFET 10的应力膜500部分，如箭头805所示被离子注入，优选被锗(Ge)离子注入。在这一步骤中，用掩模810来保护重叠PFET 20的应力膜500。
离子注入的剂量和能量能够被调节成使注入的膜500中的应力被降低到接近0的数值。此离子注入借助于击破硅与氮原子之间的键而降低膜的应力，从而引起位错。实验已经表明，张应力和压应力二者都能够通过离子注入被降低到接近0的数值。作为离子注入的结果，存在于重叠NFET 10的氮化硅膜500中的应力被弛豫，而重叠PFET20的区域内的同一个膜500保持压应力。而且，当进行诸如退火之类的热循环时，膜500的注入部分能够被转换成张应力膜。
随后，优选进行热退火工艺。由于在重叠NFET 10的膜500部分内存在着注入离子浓度(Ge)，故此退火工艺使重叠NFET 10的膜500部分转换成应力幅度比原来淀积的膜小得多的膜。作为这一工艺的结果，膜的注入部分甚至可以被转换成张应力膜。在图1中，重叠NFET的应力膜500部分被称为902。重叠PFET 20的膜的其余部分在图1中被称为901。
如图9进一步所示，第二应力膜990优选被特别形成来将张应力膜涂敷到NFET 10。如所示，此第二应力膜990被形成位重叠NFET 10和PFET 20二者。第二层膜990优选包括诸如氮化硅之类的张应力的氮化物膜，用来将张应力施加到NFET 10。此第二膜990的厚度和特性被选择成将所需水平的张应力赋予NFET 10的沟道区。
一旦形成了第二应力膜990，先前形成的氧化物层550就起作用来使应力膜990与下方受压应力的PFET 20保持足够的距离，以便不干扰希望要引入在PFET 20沟道区中的压应力的大小。
如图10进一步所示，介质材料1000被淀积在包含NFET 10和PFET 20的结构上。此介质层可以由各种绝缘材料组成，诸如例如TEOS淀积的氧化物之类的氧化物、诸如硼磷硅酸盐(BPSG)玻璃之类的掺杂的玻璃、或诸如有机材料之类的低介电常数介质。
再次参照图1，为了完成此结构，导电通道被形成在介质区中，以便提供接触排列在源和漏区上的硅化物区32的导电通道1100以及接触栅导体的硅化物区28的导电通道1102。用诸如金属或金属硅化物之类的导电材料来填充导电通道，以便提供到NFET和PFET的电连接。
在本发明的范围内尝试了许多变化。在一个实施方案中，应力膜被形成来将应力赋予PFET和NFET之外的器件(例如仅仅作为例子有选通二极管、可控硅整流器、三端双向闸流晶体管等)的导电沟道。
在这种变化中，代替形成第二应力膜之前在PFET上的中间层淀积和图形化，可以在NFET和PFET上形成第二应力膜，然后图形化以便从重叠PFET的部分上清除此膜，倘若这些步骤在比较低的温度下并在避免改变单一应力膜压应力部分901(图1)的特性的条件下被执行的话。
在上述实施方案的一种变化中，淀积在NFET和PFET上的单一应力膜具有第一幅度的张应力。此膜将具有所需高幅度的张应力赋予NFET的导电沟道。在形成单一应力膜之后，NFET被掩蔽，并将离子(例如Ge离子)注入到重叠PFET的单一应力膜部分中。在退火之后，重叠PFET的单一应力膜部分就具有幅度比第一幅度小得多的张应力、或零应力、或压应力。在这一实施方案中，重叠PFET的第二应力膜最好具有高幅度的压应力，以便将所希望的高幅度压应力提供给PFET的导电沟道。
虽然参照其一些优选实施方案已经描述了本发明，但本技术领域熟练人员可以理解的是，在不偏离本发明的范围和构思的情况下能够作出的许多修正和增强，仅仅受到所附权利要求的限制。
Claims (20)
1.一种半导体器件结构，它包含：
第一半导体器件；
第二半导体器件；
设置在所述第一和第二半导体器件二者上的单一应力膜，所述应力膜具有重叠所述第一半导体器件的第一部分，所述第一部分将第一幅度的压应力赋予所述第一半导体器件的导电沟道，所述应力膜还具有重叠所述第二半导体器件的第二部分，所述第二部分不将所述第一幅度的压应力赋予所述第二半导体器件的导电沟道，所述第二部分包括不存在于所述第二部分中的离子浓度，致使所述第二部分将幅度比所述第一幅度小得多的压应力、零应力、以及张应力之一赋予所述第二半导体器件的所述导电沟道。
2.权利要求1所述的半导体器件结构，其中，所述第一半导体器件包括p型场效应晶体管即PFET，且所述第二半导体器件包括n型场效应晶体管即NFET。
3.权利要求2所述的半导体器件结构，其中，所述单一应力膜包括氮化硅，且所述离子浓度包括注入的锗即Ge离子的浓度。
4.权利要求3所述的半导体器件结构，还包含重叠所述PFET和所述NFET的第二应力膜，所述第二应力膜将张应力赋予所述NFET的所述导电沟道，还包含在所述第一和所述第二应力膜之间重叠所述PFET的中间层，所述中间层不重叠所述NFET。
5.权利要求2所述的半导体器件结构，其中，所述第二应力膜主要由氮化物组成。
6.权利要求2所述的半导体器件结构，其中，所述第二应力膜由氮化硅组成。
7.权利要求2所述的半导体器件结构，其中，所述中间层包括共形介质材料。
8.权利要求2所述的半导体器件结构，其中，所述中间层主要由氧化物组成。
9.权利要求8所述的半导体器件结构，其中，所述中间层由二氧化硅组成。
10.权利要求8所述的半导体器件结构，其中，所述中间层的厚度为100-300埃。
11.一种半导体器件结构，它包含：
第一半导体器件；
第二半导体器件；
设置在所述第一和第二半导体器件二者上的单一应力膜，所述应力膜具有重叠所述第一半导体器件的第一部分，所述应力膜将第一幅度的张应力赋予所述第一半导体器件的导电沟道，所述应力膜还具有重叠所述第二半导体器件的第二部分，所述第二部分不将所述第一幅度的张应力赋予所述第二半导体器件的导电沟道，所述第二部分包括不存在于所述第二部分中的离子浓度，致使所述第二部分将幅度比所述第一幅度小得多的张应力、零应力、以及压应力之一赋予所述第二半导体器件的所述导电沟道。
12.一种制造半导体器件结构的方法，它包含：
制作p型场效应晶体管即PFET和n型场效应晶体管即NFET，所述NFET和所述PFET各具有设置在衬底的单晶半导体区中的导电沟道；
在所述PFET和所述NFET上形成具有第一幅度压应力的应力膜；
用掩模来覆盖所述PFET，同时暴露所述NFET；
对重叠所述NFET的所述应力膜的一部分进行离子注入，所述掩模保护重叠所述PFET的所述应力膜的其它部分免受所述离子注入；以及
对所述衬底进行退火，
从而，所述应力膜的所述被注入部分的所述压应力，通过所述退火从所述第一幅度大幅度地降低，致使重叠所述NFET的所述被注入的部分将幅度大幅度地降低了的压应力、零应力、以及张应力之一赋予所述NFET的所述导电沟道，且所述其它部分继续将所述第一幅度的压应力赋予所述PFET的所述导电沟道。
13.权利要求12的方法，还包含下列步骤：
形成在所述第一与所述第二应力膜之间重叠所述PFET的中间层，所述中间层不重叠所述NFET；以及
形成重叠所述PFET和所述NFET的第二应力膜，所述第二应力膜将张应力赋予所述NFET的所述导电沟道。
14.权利要求13的方法，其中，所述第二应力膜主要由氮化硅组成。
15.权利要求13的方法，其中，所述中间层主要由氧化物组成。
16.权利要求15的方法，其中，所述中间层主要由二氧化硅组成。
17.权利要求16的方法，其中，所述二氧化硅层在低温下被淀积。
18.权利要求17的方法，其中，所述二氧化硅从原硅酸四乙酯即TEOS前体被淀积。
19.权利要求12的方法，其中，所述应力膜的厚度被改变，以便调节所述应力的幅度。
20.权利要求12的方法，其中，所述离子注入的特性被改变，以便调节所述应力的幅度。
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-
2005
- 2005-08-23 CN CNB2005100915726A patent/CN100411175C/zh not_active Expired - Fee Related
- 2005-11-24 SG SG200507470A patent/SG122926A1/en unknown
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2007
- 2007-01-24 US US11/657,154 patent/US7442611B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101207126B (zh) * | 2006-12-22 | 2010-06-09 | 国际商业机器公司 | 可缩放的应变fet器件及其制备方法 |
| CN101393919B (zh) * | 2007-09-21 | 2012-09-05 | 株式会社半导体能源研究所 | 半导体装置 |
| CN102709194A (zh) * | 2012-06-21 | 2012-10-03 | 上海华力微电子有限公司 | Nmos器件制作方法 |
| CN102709194B (zh) * | 2012-06-21 | 2015-06-17 | 上海华力微电子有限公司 | Nmos器件制作方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US7193254B2 (en) | 2007-03-20 |
| SG122926A1 (en) | 2006-06-29 |
| US7442611B2 (en) | 2008-10-28 |
| CN100411175C (zh) | 2008-08-13 |
| US20060113568A1 (en) | 2006-06-01 |
| US20070122982A1 (en) | 2007-05-31 |
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