CN1790700A - 半导体器件的结构和制造方法 - Google Patents

半导体器件的结构和制造方法 Download PDF

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CN1790700A
CN1790700A CNA2005101143253A CN200510114325A CN1790700A CN 1790700 A CN1790700 A CN 1790700A CN A2005101143253 A CNA2005101143253 A CN A2005101143253A CN 200510114325 A CN200510114325 A CN 200510114325A CN 1790700 A CN1790700 A CN 1790700A
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via hole
conductive component
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CN100452388C (zh
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杨海宁
朱慧珑
C·H·沃恩
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

本发明提供了一种包括具有第一部分和第二部分的半导体器件区的结构。提供水平地在所述第一部分上但不在所述第二部分上延伸的导电部件。如应力施加膜的第一膜，在所述第二部分上和只部分地在所述导电部件上延伸，以暴露所述部件的接触部分。提供与所述部件的所述接触部分导电连通的第一接触过孔，第一接触过孔具有自对准含硅化物区。提供与所述半导体器件区的所述第二部分导电连通的第二接触过孔，所述第二接触过孔延伸穿过所述第一膜。

Description

半导体器件的结构和制造方法
技术领域
本发明涉及半导体器件的结构和制造方法。
背景技术
在常规体半导体晶片中制造集成电路的过程中，在相反电导率的衬底中注入p型或n型电导率的阱。然而，在互补金属氧化物半导体(CMOS)技术中，同时利用p型和n型阱。通过注入与阱相反的n型或p型电导率的扩散区形成源极区/漏极区，以形成金属氧化物半导体场效应晶体管(MOSFET)。最近的理论和试验研究也表明当给晶体管的导电沟道施加足量的应力以致在其内部产生应变时，可以增加晶体管内的载流子迁移率。可以通过给n型场效应晶体管(NFET)的导电沟道施加纵向拉伸应力获得NFET的性能的提升。可以通过给p型场效应晶体管(PFET)的导电沟道施加纵向压缩应力获得PFET的性能的提升。
可以淀积应力施加膜，下文中也称作“应力”膜，以覆盖半导体器件区，以在其上施加应力，用于加强例如NFET或PFET器件的晶体管的电导率。氮化硅是可以这样淀积的材料中的一种，其中所得材料层给与它接触的第二材料层施加拉伸应力或压缩应力。为了提高NFET和PFET的电导率，可以形成施加拉伸应力的氮化物覆盖NFET器件区并可以形成施加压缩应力的氮化物覆盖PFET器件区。
从制造的角度看，可以通过施加每层具有不同内部应力的两层膜实现这一目的。在此情况下，如图1的截面示意图所示，可以在构图第一层膜102之后，淀积并构图第二层膜104，以制造层叠边界100。然而，层叠边界可以产生某些问题。
一个这样的问题涉及在浅沟槽隔离(STI)区110之上的位置上，即，在两种不同应力的膜之间的边界220处，到例如硅化多晶硅导体225的导电部件的接触过孔210的制造。在蚀刻其它接触孔，例如用于到多晶硅导体225的接触过孔212的接触孔时，很难进行在边界220处的接触孔的蚀刻。该难度的引起是因为在形成接触过孔212处覆盖硅化多晶硅导体225的膜104相比于在边界220处层叠的应力膜102和应力膜104的组合厚度之间的厚度变化。图2进一步示出了通过应力膜102以接触硅化半导体器件区202的另一个接触过孔230。如从图1-2明显所示，在边界220处层叠的应力膜102、104远厚于在形成接触过孔212处的膜104和在形成接触过孔230处的膜102。由于总的膜厚度的变化，用于接触过孔210的接触孔的蚀刻将不能被蚀刻到足够深度以完全接触硅化多晶硅导体225的可能性会增加。实际上，如图1中220处明显所示，可能导致接触开口的失败。接触开口的失败会在导电接触过孔和多晶硅导体之间的界面处出现远高于正常的接触电阻。接触开口的失败会在接触孔不能被充分蚀刻时出现。
从而，需要其中可以提供不止一个应力膜同时允许在更低的难度下蚀刻接触过孔的半导体器件的结构及其制造方法。
发明内容
根据本发明的一个方面，提供了一种包括具有第一部分和第二部分的半导体器件区的结构。提供水平地在所述第一部分上但不在所述第二部分上延伸的导电部件。如应力施加膜的第一膜，在所述第二部分上和只部分地在所述导电部件上延伸，以暴露所述部件的接触部分。提供与所述部件的所述接触部分导电连通的第一接触过孔，第一接触过孔具有自对准含硅化物区。提供与所述半导体器件区的所述第二部分导电连通的第二接触过孔，所述第二接触过孔延伸穿过所述第一膜。
根据本发明的优选方面，在半导体器件区中设置如p型场效应晶体管(PFET)的晶体管，并且第一膜施加压缩应力给PFET的导电沟道。根据本发明的更优选方面，在另一半导体器件区中设置如n型场效应晶体管(NFET)的另一晶体管，在其上设置拉伸应力膜，该膜施加拉伸应力给NFET的导电沟道。
附图说明
图1是截面图，示出了其中施加并构图每层具有不同内部应力的两层膜以产生在其处将要形成第一导电接触过孔的层叠边界的半导体器件结构。
图2是截面图，示出了在其处将要形成第二导电接触过孔的图1所示的半导体器件结构的不同位置。
图3是自顶向下的示图，示出了根据本发明的一个实施例具有未重叠(underlapped)应力膜和导电接触过孔的结构。
图4-10是截面图，示出了根据本发明的实施例制造图3所示的结构中的阶段。
具体实施方式
虽然未重叠结构实现了在NFET和PFET上提供双重应力施加膜的目的，并降低了在层叠边界中蚀刻的影响，但它没有解决前面讨论的所有蚀刻的影响。解决蚀刻问题的一个潜在方法是减小将要蚀刻的膜的厚度或将其除去，并添加延迟蚀刻处理的结构。现在将参考图3到10描述这种解决方案。
图3为自顶向下的示图，示出了本发明的一个实施例。如图3中所示，在半导体衬底中提供了半导体器件区302、304。在图3的实施例中，半导体器件区302、304通过围绕它们的浅沟槽隔离350被隔离。器件区302、304被处理以在区域302中形成p-型场效应晶体管(PFET)而在区域304中形成n-型场效应晶体管(NFET)。
其中制造了NFET 304和PFET 302的半导体区可以包括衬底或晶片的单晶半导体区，晶片可以是体衬底或绝缘体上半导体衬底。例如，在绝缘体上硅(SOI)衬底中，设置半导体的相对薄单晶区作为绝缘层上的器件区。当在这样的SOI衬底中形成场效应晶体管(FETs)时，通常可以获得比其它方式更快的切换操作，这是因为消除了晶体管的沟道区和体衬底之间的结电容。
分别包括用于PFET和NFET的栅极导体322和324的部分的导电部件330在用作半导体器件区302、304的沟道区的第一部分310上延伸，导电部件也在它们之间的STI区302上延伸。该导电部件提供了从PFET器件区302的外端306延伸到NFET器件区304的外端308的导电部件。导电部件330也保持两个NFET和PFET的栅导体322，324在公共电位。导电部件既可以由单层构成也可以由多层构成。例如，在本发明的一个实施例中，导电部件包括多晶半导体层。在此情况下，导电部件称作“多晶导体”(PC)。然而，在可选实施例中，导电部件由设置在多晶半导体层上的硅化物层构成。在图3中不能充分地图示这种多层导电部件的细节，而是如下描述。
多晶硅是在导电部件330的制造中用作“多晶导体”以提供与用于PFET和NFET的晶体管栅极匹配的功函数的优选材料。没有导电部件330穿过的器件区302、304的第二部分320用于晶体管的源极区/漏极区，对于各自的晶体管类型适当地掺杂和处理这些区域。在导电部件的侧壁上设置例如氮化硅或氧化硅隔离物的介质隔离物380。将如下全面描述的应力膜402、404置于包括导电部件的器件区302、304之上。虚线代表应力膜从器件区沿介质侧壁隔离物380垂直上升的位置。
还如图3所示，提供与导电部件330导电连通的接触过孔342。例如，在344处示出了到PFET的源极区的单独接触过孔。虽然为了易于参考在图3中只示出了一个这样的到PFET的源极的接触过孔，但是可以将类似接触提供给PFET和NFET的源极区和漏极区。通过在各自的位置上形成接触孔来形成这样的接触过孔，并接着充填它们以制造器件接触342和344。
图4为穿过图3中所示的实施例的线A-A的截面图。图4更清楚地示出了包括具有如掺杂多晶硅的材料的第一层334和具有硅化物的第二层332的多层导电部件330。
在半导体器件结构上构图应力施加膜402、404(在这里也称作“应力膜”)，以使两层膜不在中间相遇，即以两层膜“未重叠”的方式。第一拉伸应力膜404在NFET器件区304上延伸，如图4所示。按这样的方法形成膜404以给导电部件330下面的器件区304中的NFET的沟道区中设置的半导体材料施加拉伸应力。该应力膜404提高了位于其上的NFET的性能。可以使用的该膜的优选实例为氮化硅膜(SiN4)。提供另一压缩应力膜402以给位于其上的PFET器件区302施加压缩应力。在所示的结构中，在拉伸应力膜404上设置氧化物层406。可选地省略该氧化物层。在两层膜402和404之间提供间隙410。
通过在包括PFET器件区302、NFET器件区304、和导电部件330、以及STI区350的整个结构上第一覆盖淀积拉伸应力膜404，淀积并构图应力膜402、404，然后可选地在整个结构上淀积氧化物层406。然后通过光刻和蚀刻，一起构图氧化物层406和拉伸应力氮化物层404。在一个实施例中，除去氧化物层，因为具体地不需要它来形成图4所示的结构。然后，在整个结构上覆盖淀积压缩应力膜402，并接着通过光刻和蚀刻构图该膜以形成所示的结构。
图5通过与图4所示相同的视图示出了该结构的制造中的后续阶段。如图5所示，在该结构上形成介质区460，该介质区包括如通常被提供作为层间介质材料的材料。在一个实施例中，介质材料是自平面化的，以便在淀积时介质区的上表面462具有基本上平坦的表面。例如，如掺杂的硅酸盐玻璃例如硼磷硅酸盐玻璃(BPSG)、硼硅酸盐玻璃(BSG)或其它硅酸盐玻璃例如未掺杂的硅酸盐玻璃(USG)的高流动性氧化物用于此目的。作为选择，可以淀积并热处理旋涂玻璃(SOG)材料，以提供相对平坦的上表面。从原硅酸四乙酯(TEOS)前体淀积的氧化物也可以获得相对的平坦性。作为选择，或此外，可以在淀积之后进行特定处理，例如通过化学机械抛光(CMP)，以帮助平面化介质区460。
在一个实施例中，以与本申请同日提出的美国专利申请号-未给定中描述的方法提供阻挡层，该申请的发明人为Haining S.Yang，题目为“STRUCTURE AND METHOD FOR STRAINED CHANNEL FIELDEFFECT TRANSISTOR PAIR HAVING UNDERLAPPED DUALLINERS”。在此结合该申请作为参考。在此实施例中，设置基本覆盖半导体器件区302、304的所有面积的阻挡层作为下介质区和上介质区之间的中间层。与应力膜相邻垂直设置下介质区，下介质区具有基本平坦的上表面。在阻挡层上设置上介质区。阻挡层用于充分防止污染物例如金属如铜从上介质区上的空间扩散到阻挡层之下的如半导体器件区302、304的结构。层间介质层460的厚度说明性地在约4000到5000之间。
其后，如图5和6所示，同时蚀刻接触孔542、644作为制造上述关于图3的接触过孔342、344的初始步骤。在蚀刻的该初始阶段，将接触孔542蚀刻到它的最大蚀刻深度。然而，只将接触孔644蚀刻到朝向它的最大蚀刻深度的一部分距离。如果可能，很难提供以相同速率蚀刻两种完全不同的材料的蚀刻工艺。因此，蚀刻接触孔542穿过氧化物介质区460并进入硅化物区332和多晶硅导体330的多晶硅部分334的相同蚀刻步骤，导致接触孔644只被蚀刻穿过介质区460，以在应力氮化物膜402内部分地延伸。
图7示出了形成接触过孔的第二阶段。如其中所示，在接触孔542和导电部件330的多晶硅部分334之间的界面544处形成自对准含硅化物区702。通过淀积金属形成含硅化物区作为硅化物前体，此金属形成沿接触孔的底部544和侧壁543的层。优选硅化物前体金属基本上包括如钛(Ti)、钴(Co)、镍(Ni)、钽(Ta)、铂(Pt)、钨(W)或其组合的金属，而区域702包括该金属的硅化物。硅化物前体金属可以是与用于形成覆盖栅极导体的多晶硅部分334的第一硅化物332相同或不同的金属。这样，依赖于淀积的硅化物前体金属，硅化物层702的材料的实例包括但不局限于：TiSix、CoSix尤其是CoSi2、TiCoSix、NiSi和/或NiSi2、NiCoSix、TaSi2、PtSi2、NiPtSix、WSix和其混合物。沿接触孔542的侧壁543的金属层可以具有均匀的厚度，或从接触孔544的底部到介质区460的上表面462变化的厚度。当淀积金属进入开口时，淀积金属的厚度变化基于将要淀积的材料源的表面的邻近状况发生。因此，更接近介质区460的外表面462的接触孔542的部分更可能在淀积金属层进入开口期间允许更厚的金属层。另一方面，更接近接触孔的底部544的接触孔542的部分更可能在淀积期间允许更薄的金属层。这里描述的本发明的实施例适合使用，尽管淀积的硅化物前体金属在接触孔544的不同位置上的厚度变化。
然后淀积的金属与和它接触的多晶硅层334发生发应，通过退火形成硅化物区702。此后通过留下基本未受影响的下面的结构的清洁工艺选择地除去未接触多晶硅层334的淀积金属的部分。
图8为截面图，示出了在上述关于图7的处理进行完之后的接触孔644处的结构。虽然，如上所述，沿孔的侧壁645和底部666在包括进入接触孔644的整个结构上淀积了硅化物前体金属，但是由于淀积的金属没有和下面的应力膜402的氮化物反应，所以没有形成硅化物。这样从接触孔644的侧壁和底部除去未反应的金属，以使它在当它被初始蚀刻(图6)之后充分地出现。然而，注意，当接触孔被导电填充物充分填充时，除去硅化物前体金属的未反应部分的步骤是可选择的。
然后，如图9和10所示，用导电填充物填充接触孔以形成接触过孔342和344。说明性地，通过淀积例如导电氮化物如氮化钛(TiN)的导电阻挡材料作为保护性阻挡，填充接触过孔，接着淀积可以通过化学气相淀积(CVD)工艺淀积的优选为钨的金属。接着例如用CMP、或回蚀刻工艺进行处理，以从介质区的上表面462除去过剩淀积的金属和导电氮化物材料。
尽管已经参考其特定优选实施例描述了本发明，本领域的技术人员将理解只要不脱离只通过所附权利要求限制的本发明的真实范围和精神，可以进行许多修改和改进。

Claims (20)

1.一种结构，包括：
半导体器件区，包括第一部分和第二部分；
导电部件，水平地在所述第一部分上但不在所述第二部分上延伸；
第一膜，在所述第二部分上和只部分地在所述导电部件上延伸，以暴露所述部件的接触部分；
第一接触过孔，与所述部件的所述接触部分导电连通，所述第一接触过孔包括自对准含硅化物区；以及
第二接触过孔，与所述第二部分导电连通，所述第二接触过孔延伸穿过所述第一膜。
2.根据权利要求1的结构，其中所述部件为第一导电部件，所述结构还包括第二导电部件，以及一部分所述第一接触过孔设置在所述第一和第二部件之间。
3.根据权利要求2的结构，其中所述第一膜基本上包括氮化物。
4.根据权利要求3的结构，其中所述第一膜基本上包括氮化硅。
5.根据权利要求4的结构，其中所述第一膜具有内部应力，以使所述第一膜施加应力给所述半导体器件区的所述第一部分。
6.根据权利要求5的结构，还包括具有在所述第一部分中设置的导电沟道和在所述第二部分中设置的源极区和漏极区的第一晶体管，其中所述第一膜施加应力给所述导电沟道。
7.根据权利要求6的结构，其中所述半导体器件区还包括第三部分和第四部分，所述导电部件在所述第三部分上但不在所述第四部分上延伸，所述结构还包括具有在所述第三部分中设置的导电沟道和在所述第四部分中设置的源极区和漏极区的第二晶体管，并还包括第二膜，所述第二膜在至少所述第四部分上和只部分地在所述导电部件上延伸，以暴露所述部件的所述接触部分。
8.根据权利要求7的结构，其中所述第一晶体管为具有p型导电沟道的场效应管(“PFET”)而所述第二晶体管为具有n型导电沟道的场效应晶体管(“NFET”)，其中所述导电部件包括所述PFET和NFET的栅极导体。
9.根据权利要求8的结构，其中所述第一膜具有压缩内部应力，以使所述第一膜施加压缩应力给所述PFET的所述导电沟道。
10.根据权利要求9的结构，其中所述第二膜具有拉伸内部应力，以使所述第二膜施加拉伸应力给所述NFET的所述导电沟道。
11.根据权利要求4的结构，其中所述导电部件包括多晶半导体。
12.根据权利要求8的结构，还包括覆盖所述第一膜和第二膜中的至少一个的蚀刻停止层，以及覆盖并密封所述晶体管的介质区，其中所述第一接触过孔延伸穿过所述介质区并接触在所述蚀刻停止层下面的位置上的所述导电部件。
13.根据权利要求12的结构，还包括给所述第一和第二接触过孔添加的金属衬里，所述金属衬里包括在所述第一接触过孔的所述自对准含硅化物区中包含的所述硅化物的前体金属。
14.一种结构，包括：
p型场效应晶体管(PFET)和n型场效应晶体管(NFET)，具有在半导体器件区的第一部分中设置的导电沟道和在半导体器件区的第二部分中设置的源极区和漏极区；
导电部件，水平地在所述半导体器件区的所述第一部分上但不在所述第二部分上延伸；
第一膜，具有内部压缩应力，所述第一膜在所述PFET的所述器件区的所述第二部分上和只部分地在所述导电部件上延伸，以暴露所述部件的所述接触部分；
第二膜，具有内部拉伸应力，所述第二膜在所述NFET的所述器件区的所述第二部分上和只部分地在所述导电部件上延伸，以暴露所述部件的所述接触部分；
第一接触过孔，与所述部件的所述接触部分导电连通，所述第一接触过孔包括自对准含硅化物区；
第二接触过孔，与所述PFET的所述第二部分导电连通，所述第二接触过孔延伸穿过所述第一膜；以及
第三接触过孔，与所述NFET的所述第二部分导电连通，所述第三接触过孔延伸穿过所述第二膜。
15.一种形成到半导体结构的接触的方法，包括以下步骤：
包括第一部分和第二部分的半导体器件区；
形成水平地在半导体器件区上的第一部分上但不在所述半导体器件的第二部分上延伸的导电部件；
形成在所述第二部分上和只部分地在所述导电部件上延伸以暴露所述部件的接触部分的第一膜；
同时形成a)与所述部件的所述接触部分导电连通并具有自对准含硅化物区的第一接触过孔，以及b)与所述第二部分导电连通的第二接触过孔，所述第二接触过孔延伸穿过所述第一膜。
16.根据权利要求15的方法，其中所述第一膜基本上包括氮化物。
17.根据权利要求16的方法，其中所述第一膜基本上包括氮化硅。
18.根据权利要求15的方法，其中所述部件为第一导电部件，其中所述方法还包括在所述第一导电部件和第二导电部件之间形成一部分所述第一接触过孔。
19.根据权利要求18的方法，还包括在所述半导体器件区的所述第一和第二部分内形成p型场效应晶体管(PFET)，所述PFET具有作为栅极导体的所述导电部件，其中所述第一膜具有压缩内部应力，以使所述第一膜施加压缩应力给所述PFET的沟道区。
20.根据权利要求19的结构，其中所述导电部件包括多晶半导体。
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