CN1812089A - 半导体装置及其制造方法、电路基板、以及电子仪器 - Google Patents

半导体装置及其制造方法、电路基板、以及电子仪器 Download PDF

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Publication number
CN1812089A
CN1812089A CNA2005101377203A CN200510137720A CN1812089A CN 1812089 A CN1812089 A CN 1812089A CN A2005101377203 A CNA2005101377203 A CN A2005101377203A CN 200510137720 A CN200510137720 A CN 200510137720A CN 1812089 A CN1812089 A CN 1812089A
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electrode
semiconductor device
resin bed
semiconductor substrate
wiring layer
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CN100428465C (zh
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伊东春树
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

一种半导体装置,备有:半导体基板,其具有能动面和背面;集成电路,其形成在所述能动面上;贯通电极,其将所述半导体基板贯通、从所述能动面及所述背面突出;第1树脂层,其设置在所述半导体基板的能动面上、具有比从所述能动面突出的所述贯通电极的一部分的高度要大的厚度、具有至少使所述贯通电极的一部分露出的开口;配线层,其设置在所述第1树脂层上、通过所述开口连接在所述贯通电极上;和外部连接端子,其连接在所述配线层上。

Description

半导体装置及其制造方法、电路基板、以及电子仪器
技术领域:
本发明是涉及半导体装置、半导体装置的制造方法、电路基板、以及电子仪器。
背景技术:
近年来,在移动电话、笔记本电脑、PDA(Personal data assistance)等的便携式电子仪器中,伴着对小型化或轻量化的要求,谋求着在其内部设置着的半导体装置等的各种电子部件的小型化。在这样的背景下,提出了半导体装置的3维安装技术的方案。该3维安装技术,是将具有一样功能的半导体装置彼此、或具有不同功能的半导体装置进行层叠的技术。例如,特开2003-282819号公报,展示了将具有贯通电极的半导体装置进行多层层叠、将成为最下层的半导体装置安装在内插(interposer)基板上,通过执行再配置配线而安装在基板上的技术。
但是,即使在所述基板上安装的半导体装置的层叠体中,也还要求希望更小更薄;由此,必需根据这样的要求,寻求更多的改善。
发明内容
本发明是鉴于所述情况而做出的,其目的在于提供一种半导体装置、半导体装置的制造方法、电路基板、以及具备了该电路基板的电子仪器;本发明对具备贯通电极而已经能够进行3维安装的半导体装置,能够更为小型化、薄型化。
本发明者,为了解决所述问题而精心研究的结果,得到了以下的见解。
所述半导体装置的层叠体,通过不要(没有)使最下层的半导体装置进行安装的内插基板,能谋求其薄型化。于是,考虑:为了达到不要内插基板,便形成和从半导体基板突出的贯通电极连接的配线层,进行半导体装置的再配线化,谋求半导体装置的薄型化的方法。但是,该情况下,由于所述贯通电极和所述半导体基板之间的阶梯差(段差),产生出所述配线层中容易断线的新问题。
为此,考虑到通过在半导体基板上设置树脂层而使所述的阶梯差变小、配线层的断线的情况,完成了本发明。
本发明的半导体装置,具有:半导体基板,其具有能动面和背面;集成电路,其形成于所述能动面;贯通电极,其将所述半导体基板贯通、而从所述能动面及所述背面突出;第1树脂层,其设置于所述半导体基板的能动面上、具有比从所述能动面突出了的所述贯通电极的一部分的高度还大的厚度、并具有至少使所述贯通电极的一部分露出的开口;配线层,其设置于所述第1树脂层上、通过所述开口而连接在所述贯通电极;和外部连接端子,其连接于所述配线层。
根据本发明的半导体装置,通过设置有第1树脂层、在将配线层形成时,所述开口的高度、例如在比半导体基板和贯通电极之间所产生的阶梯差低的情况下,通过所述开口成为可防止所述贯通电极和所述配线之间的断线的装置。此外,例如在设置于第1树脂层的开口呈锥形(taper)形状的情况下,通过沿锥形形状顺利地形成所述配线层,成为也没有断线而连接于贯通电极的装置。
再有,通过设置有第1树脂层,即使将半导体装置在基板上进行安装时在外部连接端子及配线层上施加外力的情况下,所述第1树脂层也作为应力缓和层而作用,以使配线层和贯通电极的到连接部的力进行缓和。由此,则成为该连接部中的连接可靠性高。
再有,通过具有与贯通电极连接的外部连接端子,不是利用内插基板而成为在半导体装置上形成了再配置配线的装置。由此,半导体装置,成为不要内插基板、而可谋求更为小型化、薄型化的装置。
再有,所述半导体装置,备有第2树脂层;作为优选,所述第2树脂层,设置于所述第1树脂层上、具有比所述配线层的厚度还大的厚度、具有比所述第1树脂层的厚度还小的厚度、并露出在所述配线层中的连接所述外部连接端子的部分。
若这样进行,第2树脂层,因为露出与所述外部连接端子连接的配线层,所以在形成外部连接端子时,能将所述第2树脂层作为隔壁进行利用。此外,因为备有将所述配线层覆盖的第2树脂层,所以能保护配线层。而且,因为所述第2树脂层形成得比第1树脂层薄,所以第2树脂层的膜应力能变小,能缓和在半导体基板上生成的翘曲。
再有,所述半导体装置中,作为优选,所述第2树脂层在其俯视时,形成于所述第1树脂层的内侧的区域。
若这样进行,形成于第1树脂层上的第2树脂层的面积变小,能将在半导体基板上生成的翘曲变为更小。
再有,所述半导体装置,备有第3树脂层,作为优选,所述第3树脂层,设置于所述半导体基板的背面上、至少使所述贯通电极的端面露出。
若这样进行,因为在半导体基板的背面设置有第3树脂层,所以通过形成于半导体基板的能动面的第1树脂层及第2树脂层能缓和在半导体基板上生成的翘曲。此外,因为所述第3树脂使贯通电极的至少一部分露出,所以通过连接于所述背面侧的贯通电极而能将半导体装置进行层叠。
再有,作为优选,在所述半导体装置中,在所述半导体基板的背面突出了的所述贯通电极上,连接着其他的半导体装置、或电子部件。
若这样进行,在不要内插基板的半导体装置上,因为使其他的半导体层或电子部件进行层叠,所以成为小型且高密度下具有高功能的半导体装置。
再有,作为优选,所述半导体装置,具有与在所述半导体基板的背面突出的所述贯通电极相连接的第2配线层。
若这样进行,因为具有与在所述半导体基板的背面突出的所述贯通电极相连接的第2配线层,所以例如通过使该第2配线层配置为各种各样,能提高在半导体装置上可安装的半导体装置、以及电子部件的选择自由度。
再有,作为优选,所述半导体装置,备有:将在所述背面上安装的其他的半导体装置、或将电子部件进行密封的树脂。
若这样进行,通过由树脂层的密封,能可靠地保持半导体装置上被安装的其他的半导体装置、或电子部件,能提高半导体装置的可靠性。
本发明的电路基板,备有所述半导体装置。
根据本发明的电路基板,因为不使用内插基板而能在电路基板上进行安装、防止在配线部中的断线、备有谋求着薄型化及高密度化的半导体装置,所以成为该半导体装置的电路基板自身也成为小型高可靠性的基板。
本发明的电子仪器,具有所述电路基板。
根据本发明的电子仪器,因为具有所述小型而高可靠性的电路基板,所以具备有该电路基板的电子仪器也成为小型高可靠性的仪器。
本发明的半导体装置的制造方法,包括如下工序:准备半导体基板,其具有具有集成电路的能动面、和背面;形成贯通电极,其将所述半导体基板贯通而从所述能动面及所述背面突出;形成第1树脂层,其具有比从所述能动面突出了的所述贯通电极的高度还大的厚度、具有使所述贯通电极的至少一部分露出的开口;形成配线层,其通过所述开口而连接在所述第1电极;形成外部连接端子,其连接于所述配线层。
根据本发明的半导体装置的制造方法,在所述开口的高度,例如形成为比在能动面侧突出的贯通电极和半导体基板的阶梯差要低的情况下,通过所述开口能防止所述贯通电极和所述配线之间的断线。此外,例如如果设置于第1树脂的开口为锥形形状,配线层沿锥形形状能圆满地与第1配线连接。由此,通过半导体基板和贯通电极之间产生的凹凸,能防止配线层的断线。
再有,因为形成了与所述配线层连接的外部连接端子,所以即使在将半导体装置已安装在基板上时在外部连接端子上施加外力的情况下,也可使第1树脂层作为应力缓和层起作用。由此,能提高配线层和贯通电极的连接部中的连接可靠性。
进而,通过形成与贯通电极连接的外部连接端子,不必利用内插基板,而能在半导体装置上形成再配置配线。由此,可不要内插基板,能谋求半导体装置的小型化、薄型化。
此外,作为优选,在所述半导体装置的制造方法中,作为所述半导体基板利用半导体晶片(wafer),在所述半导体晶片上形成了多个所述半导体装置后,将半导体晶片切断为每一个所述半导体装置。
若这样进行,在一个半导体晶片上形成了多个半导体装置后,因为通过切断能形成单片化了的半导体装置,所以能提高半导体装置的生产性。
再有,作为优选,在所述半导体装置的制造方法中,将所述第1树脂层,形成为以不重合在所述半导体基板的切断部分上。
若这样进行,因为所述第1树脂层不形成在切断部分,所以能防止在将半导体装置进行单片化时的所述第1树脂层的剥离。
再有,作为优选,在所述半导体装置的制造方法中,在形成所述贯通电极的工序中,在所述半导体基板的能动面上形成将贯通已形成在所述能动面的所述集成电路的导电部的孔;在所述孔内形成导电部;通过将所述半导体基板从背面侧进行薄厚加工,形成贯通电极。
例如,在半导体基板上形成贯通孔,并形成贯通电极时,如果半导体基板薄则有破裂之虞。因而,如果采用本发明,在半导体基板上形成了孔后,因为在该孔上形成导电部,从背面侧将半导体基板变薄而形成贯通电极,所以能获得具备贯通电极、且防止半导体基板的破裂的小型的半导体装置。
再有,作为优选,在所述半导体装置的制造方法中,在所述半导体基板的背面,形成至少使所述贯通电极露出的第3树脂层。
若这样进行,通过在所述半导体基板的背面上所形成了的第3树脂层、抑制在所述能动面上形成了的所述第1树脂层的膜应力,能缓和半导体基板及半导体晶片的翘曲。
再有,作为优选,在所述半导体装置的制造方法中,通过在形成所述第3树脂层时、利用感光性树脂而进行曝光、显影,形成至少使在所述背面上突出的贯通电极露出的开口;在形成所述开口后,通过已溶解的树脂的流动而使所述贯通电极和所述第3树脂层接触,将所述感光性树脂进行固化。
若这样进行,因为形成有至少使所述贯通电极露出的开口,所以即使在所述贯通电极的形状较小的情况下,也能容易进行使相对于在形成所述第3树脂层时的贯通电极的直线对准(aligement)。再有,在使第3树脂层固化前,由于溶解了的第3树脂层的流动而使第3树脂层和贯通电极接触,其后固化第3树脂层。由此,例如在将半导体装置层叠时,即使在设置于贯通电极间的焊料下垂的情况下,也因为通过第3树脂层不直接接触半导体基板,所以能防止短路。
再有,作为优选,在所述半导体装置的制造方法中,在形成所述第3树脂层时,用所述第3树脂以覆盖所述贯通电极的方式进行涂布后,通过等离子体(plasma)处理而使所述贯通电极露出。
若这样进行,在形成所述第3树脂时,因为不需和所述半导体装置的对准,所以能简化制造工序。此外,与所述的情况相同地,通过所述第3树脂层,能防止半导体装置在层叠时的短路。
再有,作为优选,在所述半导体装置的制造方法中,在形成所述第3树脂层时,通过聚合物薄膜(polymer film)覆盖所述贯通电极,在该状态下进行加热的同时并进行压接,在所述聚合物薄膜上,贯通从所述背面侧突出了的贯通电极。
若这样进行,在形成所述第3树脂时,因为不需和所述半导体装置的对准,所以能简化制造工序。此外,与所述的情况相同地,通过所述第3树脂层,能防止半导体装置在层叠时的短路。
附图说明
图1是本发明的半导体装置的侧截面图。
图2是半导体装置的制造工序的说明图。
图3是半导体装置的制造工序的说明图。
图4是半导体装置的制造工序的说明图。
图5是半导体装置的制造工序的说明图。
图6是半导体装置的制造工序的说明图。
图7是半导体装置的制造工序的说明图。
图8是半导体装置的制造工序的说明图。
图9是半导体装置的制造工序的说明图。
图10是半导体装置的制造工序的说明图。
图11是半导体装置的制造工序的说明图。
图12是半导体装置的制造工序的说明图。
图13是半导体装置的制造工序的说明图。
图14是半导体装置的制造工序的说明图。
图15是半导体装置的制造工序的说明图。
图16是半导体装置的制造工序的说明图。
图17是表示半导体装置的其他的实施方式的图。
图18是表示具备了半导体装置的电路基板的图。
图19是表示具备了所述电路基板的电子仪器的图。
具体实施方式
以下,对本发明的半导体装置、半导体装置的制造方法、电路基板、及电子仪器进行说明。
首先,对本发明的半导体装置进行说明。
图1是表示本发明的半导体装置1的图。如图1所示,半导体装置1,备有:半导体基板10,其由切断了硅晶片(silicon wafer)的硅基板构成;所述半导体基板10的能动面10A,其由晶体管或存储元件、其他的电子元件构成的集成电路(未图示)所形成;和贯通电极12,其贯通所述能动面10A和该能动面的相反侧的背面10B。本实施方式中的贯通电极12,是能动面侧的端子部分的外形、比背面侧的端子部分的外形要大、形成为俯视圆形状或正方形状等的电极。再有,在所述半导体基板10上,形成有用于形成所述贯通电极12的孔部12H。
在所述孔部12H上设置有绝缘膜13,以便使所述贯通电极12和所述半导体基板10电绝缘。此外,在以下的说明中,使在所述能动面10A上突出的贯通电极12设为第1电极部12A,使在所述背面10B上突出的贯通电极12设为第2电极部12B。
在所述半导体基板10的能动面10A上设置有基底层11。基底层11,例如由二氧化硅(SiO2)等的绝缘性材料形成。此外,在基底层11上设置有电极15,在设置有该电极15区域以外的区域上设置有第1绝缘层14。进而,所述电极15电连接在贯通电极12的所述第1电极部12A上。
再有,优选从所述能动面10A到所述第1电极部12A的上面的高度,作成为低于20μm。
因而,在所述能动面10A侧的所述半导体基板10上,形成有第1树脂层18,其比在所述能动面10A侧突出了的所述第1电极部12A的高度要厚(本实施方式中,20μm)、由聚酰亚胺(polyimide)树脂等的感光性树脂构成。
在所述第1树脂层18上,形成有开口18H,该开口至少露出一部分在所述能动面10A上突出的第1电极部12A的上面。此外,所述开口18H,成为面向所述第1电极部12A将内径变狭的锥形形状。因而,在所述第1树脂层18上,通过所述开口18H,形成有连接在所述第1电极部12A的配线层21。由此,由于所述配线层21沿锥形形状顺利地形成,则可防止由所述半导体基板10和所述第1电极部12A之间的阶梯差引起的配线层21的断线。
在所述第1树脂18上,形成有第2树脂层22,其比所述配线层21的厚度厚、比所述第1树脂层18薄。所述第2树脂层22,以使设置于所述第1树脂18上的所述配线层21覆盖,能将所述配线层21从外力进行保护。因而,由于使所述第2树脂层21比所述第1树脂层18薄,能使第2树脂层22的膜应力变小,以便缓和半导体基板10的翘曲。
再有,所述第2树脂层22,成为使连接在后述的外部连接端子的部分露出的状态。因而,在从所述第2树脂层22露出的配线层21上,设置有焊球23。此外,优选所述第2树脂层22,形成为作为在形成焊球23时的隔壁所能利用程度的厚度。
再有,所述焊球23,通过介由所述配线层21而连接在所述贯通电极12上,电连接在设置于所述半导体基板10的能动面10A的集成电路上。
因此,由所述焊球23及所述配线层21,通过相对于设置于所述半导体基板10的贯通电极12而形成再配置配线,则可使半导体装置1的安装性提高。
再有,在半导体基板10的背面10B侧,形成有第3树脂层24、其至少使所述第2电极部12B的端面露出。所述第3树脂层24,和所述的第1树脂层18相同地、由聚酰亚胺树脂构成。再有,所述第3树脂层24,通过形成于所述半导体基板10的能动面10A侧的第1树脂层18及第2树脂层22可使半导体基板10所产生的翘曲缓和。再有,在本实施方式中,因为所述贯通电极12贯通所述第3树脂层24,所以可形成为使所述第3树脂层24和所述贯通电极12的侧面部密接。因此,由为将半导体基板10进行绝缘,所以在所述半导体装置1上如后述那样将半导体部件进行安装时,能够仅在贯通所述第3树脂层24的第2电极部12B上使所述半导体部件和半导体装置1进行连接。
接着,参照图,对本发明的半导体装置1的制造方法进行说明。在此,在本实施方式中说明:在形成半导体装置1时,通过利用W-CSP(Waferlevel Chip Scale Package)技术,在硅晶片(半导体晶片)上将多个半导体装置1同时一起形成,并通过形成再配置配线而密封树脂来将半导体装置1单片化的制造方法。此外,在表示制造半导体装置1的途中工序的图2~图12中,对图进行简化,表示在硅晶片上形成一个半导体装置1。再有,在以下的制造工序的说明中所利用的硅晶片和半导体基板10是相同的部件。
〖贯通电极的形成工序〗
首先,如图2所示,在由硅晶片构成的半导体基板10的能动面10A上形成基底层11,在该基底层11上形成电极15。在此,在半导体基板10的所述能动面10A上,例如形成有集成电路(未图示),该集成电路包括晶体管、存储元件、其他的电子元件。所述基底层11是绝缘层,由硅(Si)的氧化膜(SiO2)构成。所述电极15,由钛(Ti)、氮化钛(TiN)、铝(Al)、铜(Cu)等所形成、电连接在所述集成电路。因而,以覆盖基底层11及电极15,形成第1绝缘层14。
所述第1绝缘层14,可以由聚酰亚胺(polyimide)树脂、硅变性聚酰亚胺树脂、环氧树脂、硅变性环氧树脂、丙烯酸树脂、苯酚树脂、苯环丁烯(benzo-cyclobutene:BCB)、聚苯并噁唑(polybenzo-oxazole:PBO)等所形成。或,所述第1绝缘层14,由二氧化硅(SiO2)、氮化硅(SiN)等、也可以由具有绝缘性的其他的物质所形成。
然后,通过旋涂法等在所述第1绝缘层14上的全面上涂布抗蚀剂(未图示)。并且,在利用已形成规定图案的蚀刻掩模而进行曝光处理后,进行显影处理。由此,感光性树脂被图案化为规定形状。
进而,进行蚀刻处理,将覆盖电极15的第1绝缘层14的一部分除去,而形成开口部。接着,将形成了所述开口部的第1绝缘层14上的抗蚀剂作为蚀刻掩模,通过进行干式蚀刻(dry etching),将电极15贯通,而除去基底层11、及半导体基板10的一部分。由此,如图3所示,能在半导体基板10的能动面10A侧的一部分上形成孔部12H。
接着,如图4所示,在第1绝缘层14上及孔部12H的内壁及底面上形成绝缘膜13。所述绝缘膜13,为了防止电流漏出(leak)的发生、氧及水分等引起的半导体基板10的腐蚀而被设置,能利用:利用PECVD(等离子体化学气相沉积法Plasma Enhanced Chemical Vapor Deposition)而形成的正硅酸四乙酯(tetra ethyl ortho silicate:Si(OC2H5)4:以下,称为TEOS)、即利用PE-TEOS、及臭氧(ozone)CVD而形成了的TEOS、即利用O3-TEOS、或CVD而形成了的二氧化硅(SiO2)。此外,绝缘膜13,如果有绝缘性、也可以是其他的物质、也可以是树脂。另外,简单起见,设置在第1绝缘层14上的绝缘膜13省略其图示。因而,将设置在电极15上的绝缘膜13及第1绝缘层14进行蚀刻而除去。
接着,如图5所示,利用电化学电镀(ECP)法,在所述孔部12H的内侧及电极15上实施电镀处理,在该孔部12H的内侧上填埋用于形成贯通电极12的导电性材料。作为用于形成所述贯通电极12的导电性材料,例如能利用铜(Cu)、在孔部12H上填埋铜(Cu)。由此,在电极15上形成突出了的形状的贯通电极12。这时,优选在所述半导体基板10的能动面侧10A上突出的贯通电极12的第1电极部12A的高度成为不足20μm。
再有,在本实施方式中的形成贯通电极12的工序中,包括通过溅射法形成(层叠)TiN、Cu的工序、和通过电镀法形成Cu的工序。另外,也可以包括通过溅射法形成(层叠)TiW、Cu的工序、和通过镀制法形成Cu的工序。再有,作为贯通电极12的形成方法,不限于所述了的方法,也可以将导电膏(paste)、熔融金属、金属丝进行填埋。
〖第1树脂层的形成工序〗
接着,如图6所示,在所述半导体基板10的能动面10A上,形成比在该能动面10A侧突出了的所述第1电极部12A的高度厚的、厚度为20μm的第1树脂层18。这时,所述第1树脂层18,作为优选以不重合于后述的硅晶片(silicon wafer,半导体基板10)的切断部分的方式形成。由此,在将硅晶片切断而将半导体装置1进行单片化时,能防止切断所述第1树脂层18、并将其剥离。
作为形成该第1树脂层18的方法,利用作为感光性树脂的所述的聚酰亚胺树脂,在所述能动面10A上进行涂布。因而,通过进行曝光、显影,在所述聚酰亚胺树脂上形成至少使所述贯通电极12的第1电极部12A的一部分露出的开口18H。再有,作为形成所述开口18H的方法,也可以利用干式蚀刻等。另外,取代所述聚酰亚胺树脂,也可以利用硅变性聚酰亚胺树脂、环氧树脂、硅变性环氧树脂、丙烯酸树脂、苯酚树脂、苯并环丁烯(benzo-cyclobutene:BCB)、聚苯并噁唑(polybenzo-oxazol:PBO)等具有绝缘性的树脂。
此外,所述开口18H的形状,通过形成为面向所述第1电极部12而将内径变狭的锥形形状,能防止在以后的工序中所形成的配线层21的断线。另外,在本实施方式中,所述开口18H的高度比在半导体基板10和所述第1电极部12A之间产生的阶梯差要低。
这样,在所述半导体基板10上能形成第1树脂层18。
〖配线层的形成工序〗
接着,如图7所示,通过开口18H将连接在所述第1电极部12A的配线层21形成在所述第1树脂层18上。
所述配线层21,由包含铜(Cu)、铬(Cr)、钛(Ti)、镍(Ni)、钨化钛(TiW)、金(Au)、银(Ag)、铝(Al)、钒化镍(NiV)、钨(W)、氮化钛(TiN)、钯(Pd)中的至少一种的材料而形成,例如通过溅射法形成。再有,也可以通过将这些材料中的至少2种材料进行层叠而形成配线层21。在形成本实施方式中的配线层21的工序中,以TiW、Cu的顺序、通过溅射法形成,包括将铜(Cu)进行电镀的工序。再有,利用喷墨法,通过喷出导电材料并烧成,也可以形成所述配线层21。
在此,如所述,因为所述开口18H呈锥形形状,所述配线层21沿锥形形状顺利地被形成。由此,能防止由半导体基板10和贯通电极12之间生成的阶梯差引起的所述配线层21的断线。再有,所述开口18H的高度,因为如所述比半导体基板10和贯通电极12的阶梯差低,所以与在所述贯通电极12上直接形成配线层21的情况相比,更能可靠地防止所述配线层21的断线。
这样,通过所述开口18H,能形成与所述第1电极部12A连接的配线层21。
〖第2树脂层的形成工序〗
接着,如图8所示,在所述第1树脂18上,形成比所述配线层21的厚度(20μm未满)厚、比所述第1树脂层18薄的第2树脂层22。此外,作为所述第2树脂层22的材料,能利用和所述第1树脂层18相同的材料。
作为所述第2树脂层22的形成方法,例如以使所述第1树脂层18的全面覆盖,在所述第1树脂层18上进行涂布。这时,例如作为所述第2树脂层22而利用感光性树脂。由此,利用曝光掩模,通过进行曝光并显影,将只是连接后述的焊球23的部分通过显影的工序而除去,形成为使所述配线层21的一部分露出的状态。再有,通过利用液滴喷出法,通过在期望的位置上喷出树脂,也可以形成使所述焊球23的连接部露出的第2树脂层22。
这样,因为所述配线层21由第2树脂层22覆盖住,所以能将所述配线层21从外力等进行保护。因而,由于将第2树脂层22比所述第1树脂层18薄,所以能将第2树脂层22的膜应力变小,能缓和半导体基板10的翘曲。再有,优选所述第2树脂层22,在俯视的状态下形成在所述第1树脂层18的内侧的区域。
若这样进行,能将在所述第1树脂层18上所形成的的第2树脂层22的面积变小,能将在半导体基板上所产生的翘曲变得更小。再有,由于形成在所述第1树脂层18上,如上所述没有重合于硅晶片(半导体基板10)的切断部分的情况,则能防止在将半导体装置1进行单片化时的所述第2树脂层22的剥离。
〖半导体基板的薄型处理〗
接着,如图9所示,通过由紫外光(UV光)的照射可剥离的粘合剂28,在所述半导体基板10的能动面10A侧将玻璃板200粘贴。该玻璃板200是被称为WSS(Wafer Support System)的物质的一部分;半导体基板(硅晶片10)则成为被玻璃板200支撑的状态。于是,在将半导体基板(硅晶片)10在玻璃板200上粘贴的状态下,实施对于半导体基板10的研削处理或干式蚀刻处理、或湿式蚀刻处理等的规定的薄型加工。此外,也可以并用这些处理。
由此,如图10所示,在使半导体基板10变薄的同时,贯通电极12的一端部,通过从背面侧10B侧露出,成为第2电极部12B。这时,所述第2电极部12B的侧面部变成为由绝缘层13而一部分覆盖的状态。
通常,在变薄了的半导体基板10上形成贯通孔时,半导体基板10有破裂之虞。因而,如果采用本发明,在半导体基板10上形成孔部12H后,通过利用所述的WSS(Wafer Support System),在支撑于玻璃基板200的状态下,通过从背面10B侧将半导体基板10变薄,所以能获得具备了贯通电极12的已薄型加工的半导体基板10。
〖第3树脂层的形成工序〗
接着,如图11所示,在所述半导体基板10的背面10B上,形成至少使所述贯通电极12的第2电极部12B的端面露出的第3树脂层24。此外,所述第2电极部12B的端面的露出,例如在所述第2电极部12B上通过焊料等而将半导体芯片(chip)进行安装时,所述半导体芯片的端子和所述第2电极部12B、露出得能导通程度。
在此,作为形成所述第3树脂层24的方法,有以下的方法。
作为第1方法,例如在利用聚酰亚胺树脂等的感光性树脂材料在所述半导体基板10的背面10B上进行涂布后,通过利用曝光掩模,曝光、乃至显影的工序,形成比在背面10B侧上突出的第2电极部12B的外径要大的开口。由此,即使在所述贯通电极12的形状较小的情况下,也能容易进行相对于在形成所述第3树脂层24时的贯通电极12的对准。
并且,在使该感光树脂热固化前,通过利用溶解了的树脂的流动,使所述贯通电极12和所述感光性树脂密接、使感光性树脂热固化。这样,第3树脂层24,则成为形成为使所述贯通电极12贯通的状态的树脂层。
再有,在所述半导体基板10的背面10B上所形成的第3树脂层24,通过抑制在所述能动面10A上形成的第1树脂层18、及第2树脂层22的膜应力,能缓和半导体基板10的翘曲。再有,因为贯通电极12将第3树脂层24贯通,所以则使所述贯通电极12和第3树脂层24的侧壁部进行接触。由此,在半导体装置1上将半导体芯片进行安装,即使设置于所述贯通电极12间的焊料下垂时,也不是直接接触在背面10B侧的半导体基板10的硅部分,能防止短路。
作为第2方法,将聚酰亚胺树脂、例如通过旋涂法以使第2电极部12B覆盖而在所述半导体基板10的背面10B前面上进行涂布后,利用等离子体处理,通过使第2电极部12B露出而形成第3树脂层24。
这时,优选将由旋涂法涂布的树脂的膜厚形成得从所述背面10B突出的第2电极部12B刚好覆盖。由此,由等离子体处理所除去的树脂量变少,能将进行等离子体处理的时间变短。
再有,在形成所述第3树脂24时,因为利用旋涂法,所以不需进行相对于所述半导体基板10的正确的对准,能将所述第3树脂层24的制造工序简化。
作为第3方法,将在所述半导体基板10的背面10B上突出的贯通电极12的第2电极部12B,由成为第3树脂层的聚合物薄膜覆盖。而且,在该状态下加热的同时进行压接,将所述聚合物薄膜粘贴在所述背面10B上。这样,从所述背面10B突出的所述第2电极部12B,碰到所述聚合物薄膜,而且变成使所述聚合物薄膜贯通。再有,在所述第2电极部12B不能将所述聚合物薄膜充分地贯通的情况下,也可以利用等离子体处理。再有,作为所述聚合物薄膜,能利用半固化状态的聚合物薄膜、或液晶聚合物薄膜。
这样,第3树脂层24,形成为被所述贯通电极12贯通的状态。
同样,因为不需进行相对于所述半导体基板10的正确的对准,所以能将所述第3树脂层24的制造工序简化。
接着,如图12所示,作为在从所述半导体基板10的背面10B侧突出的第2电极部12B上的焊料,例如通过设置由Sn-Ag构成的焊接层50,将具有和所述贯通电极12相同端子之配置的存储IC等的电子部件60多个层叠。作为这样的层叠方法,例如通过利用焊头(bonding tool)将所述电子部件60加热、压接的方法,或利用逆流(reflow)技术,能适当地利用将所述电子部件60一起地在半导体装置1上进行安装的方法。
在半导体装置上层叠所述电子部件60以后,如图13所示,通过用于保护这些已层叠的半导体装置1及电子部件60的连接部的、例如由环氧树脂、硅树脂等构成的树脂70而铸模。再有,在图13~图16中,是表示在硅晶片(半导体基板10)100上制造多个半导体装置1的工序的图。再有,在图13~图17中,为了简化图,对所述的符号省略了图示。
这时,优选树脂70利用低应力树脂,以便难于生成由铸模的树脂70引起的残留应力。通过这样,由于层叠了的半导体装置由树脂覆盖,所以尤其能提高耐湿度可靠性,能提高具备该层叠部的半导体装置1的可靠性。
接着,如图14所示,将由支撑着半导体基板10的WSS(Wafer SupportSystem)的一部分构成的玻璃板200进行剥离。这时,如上所述那样、所述玻璃基板200,则为通过由紫外光(UV光)的照射可剥离的粘合剂28被粘贴于所述半导体基板10上的部件。因而,通过从玻璃基板200侧照射紫外光(UV光),能将所述粘合剂28进行剥离。为此,能将所述玻璃基板200和所述半导体基板10进行分离。
接着,如图15所示,在将设置于所述第2树脂层22的所述配线层21露出的部分上,例如搭载由无铅焊锡构成的焊球23。此时,第2树脂层22,因为将连接于所述焊球23的配线层21露出,所以在形成所述焊球23时,能将所述第2树脂层作为隔壁而利用。此外,取代设置焊球23,也可以是将焊接膏(paste)在所述配线层21上进行印刷的方式。
最后,在图15中,通过由双点锁线所示的切割线(dicing line),通过将硅晶片100切断,对形成在所述半导体基板10上的半导体装置1进行单片化。
这样,如图16所示,能获得层叠了多个所述电子部件60的半导体装置1。
根据本发明的半导体装置1,在形成配线层21时,所述开口18H的高度,因为和从半导体基板10突出的贯通电极12的高度相比要低,所以能防止由所述开口18H引起的所述配线层21的断线。再有,因为所述开口18H的形状为锥形,所以配线层21沿锥形形状能顺利地与贯通电极12连接。此外,即使将半导体装置1在半导体基板10上进行安装时在焊球23上施有外力的情况下,由于第1树脂层18作为应力缓和层起作用,也能提高配线层21和贯通电极12的连接部中的连接可靠性。
再有,通过形成连接在贯通电极12的焊球23,能在半导体装置1上形成再配置配线,可以不要内插基板。由此,使内插基板变为无,便能谋求半导体装置1的小型化。
再有,因为在不要内插基板的半导体装置1上安装有电子部件60,所以能获得小型而且具有高功能的半导体装置1。
此外,本发明不是限定于所述内容,可作种种的变更。在本实施方式中,虽然对贯通电极12和第1电极部12A和第2电极部12B的外径是不同形状的情况进行了说明,但也可以从半导体基板10的能动面10A及背面10B突出的电极部的形状为相同。
再有,在本实施方式中,虽然对在硅晶片100上将半导体装置1同时一起地形成的情况进行了说明,但也可以是将半导体装置1在半导体基板10上各自地形成、在该半导体装置1上将其他的半导体部件60进行层叠。
再有,在本实施方式中,虽然在半导体装置1上多个层叠具有相同端子之配置的存储IC等的电子部件60,但也可以层叠具有不同种的端子配置的半导体芯片或电子部件80。此时,如图17所示,形成与在所述半导体基板10的背面10B侧突出的第2电极部12B相连接的第2配线层27,通过该第2配线层27,能层叠不同端子配置的半导体芯片等的电子部件80。
这样,因为具有与第2电极部12B连接的第2配线层27,所以通过使该第2配线层各种各样地配置,能提高将在该半导体装置1上能安装的不同种的半导体装置、及电子部件80的端子的配置形状或配置的位置等进行决定的自由度。
再有,在形成所述第2配线层27时,也可以是形成感应器、电阻、电容器等。此外,在所述第2电极部12B上,也可以是连接弹性表面波元件、水晶振荡器、压电振荡器、压电音叉等的电子元件。
接着,对具备了本发明的半导体装置1的电路基板进行说明。图18是表示根据本发明的一实施方式的电路基板的示意构成的立体图。正如图18所示,在该实施方式的电路基板150上,搭载有在半导体装置1上层叠了半导体芯片等的层叠体2。电路基板150,例如因为是由玻璃环氧树脂基板等的有机类基板构成的部件,所以例如形成为由铜等构成的配线图案(未图示)成为期望的电路,而且在锥形配线图案上设置有电极垫(pad)。
因而,通过在该电气垫上电连接半导体装置1的焊球23,所述层叠体2安装在电路基板150上。
根据本发明的电路基板150,能将具备了不要内插基板的半导体装置1的层叠体2在电路基板150上进行安装。
再有,因为具备防止再配置配线中的断线、谋求着小型化及薄型化的半导体装置1,所以具备了包括该半导体装置1的层叠体2的电路基板150自身则也成为小型而且可靠性高的部件。
接着,对具备了本发明的电路基板150的电子仪器进行说明。图19是表示作为根据本发明的一实施方式的电子仪器的、移动电话机300的示例。所述电路基板150,设置在所述移动电话机300的内部。
根据本发明的移动电话机300,因为具备所述小型而且可靠性高的电路基板150,所以具备了该电路基板150的电子仪器自身则也成为小型而且可靠性高的装置。
再有,电子仪器,并非限于所述移动电话机300,能适用于各种的电子仪器。例如,可适用于液晶投影仪、多媒体对应的个人计算机(PC)及工程工作站(engineering workstation:EWS)、寻呼机(pager)、文字处理机(word-processor)、电视、寻像器(view finder)型及监视器(monitor)直视型的录像机(video tape recorder)、电子笔记本、电子计算器、汽车导航(car navigation)装置、POS终端、具有接触式面板(touch panel)装置的电子仪器。

Claims (17)

1、一种半导体装置,其中备有:
半导体基板,其具有能动面和背面;
集成电路,其形成在所述能动面上;
贯通电极,其将所述半导体基板贯通、从所述能动面及所述背面突出;
第1树脂层,其设置在所述半导体基板的能动面上,具有比从所述能动面突出的所述贯通电极的一部分的高度要大的厚度,并具有使所述贯通电极的至少一部分露出的开口;
配线层,其设置在所述第1树脂层上、通过所述开口连接在所述贯通电极上;和
外部连接端子,其连接在所述配线层上。
2、根据权利要求1所述的半导体装置,其中,
备有第2树脂层;
所述第2树脂层,设置于所述第1树脂层上、具有比所述配线层的厚度要大的厚度、具有比所述第1树脂层的厚度要小的厚度、使在所述配线层中的所述外部连接端子被连接的部分露出。
3、根据权利要求2所述的半导体装置,其中,
所述第2树脂层,在俯视时,形成在所述第1树脂层的内侧的区域。
4、根据权利要求1至3的任一项所述的半导体装置,其中,
备有第3树脂层;
所述第3树脂层,设置于所述半导体基板的背面上、至少使所述贯通电极的端面露出。
5、根据权利要求1至4的任一项所述的半导体装置,其中
在所述半导体基板的背面上突出的贯通电极上,连接着其他的半导体装置、或电子部件。
6、根据权利要求5所述的半导体装置,其中
具有与在所述半导体基板的背面突出了的与所述贯通电极相连接的第2配线层。
7、根据权利要求5或6所述的半导体装置,其中
备有将在所述背面上安装的其他的半导体装置、或电子部件进行密封的树脂。
8、一种半导体装置的制造方法,其中,按如下工序进行:
准备半导体基板,其具有具备集成电路的能动面、和背面;
形成贯通电极,其将所述半导体基板贯通而从所述能动面及所述背面突出;
形成第1树脂层,其具有比从所述能动面突出了的所述贯通电极的高度要大的厚度、具有将所述贯通电极的至少一部分露出的开口;
形成配线层,其通过所述开口而连接在所述第1电极上;
形成外部连接端子,其连接于所述配线层。
9、根据权利要求8所述的半导体装置的制造方法,其中,
利用作为所述半导体基板的半导体晶片,
在所述半导体晶片上形成多个所述半导体装置后,将所述半导体晶片切断为每一个所述半导体装置。
10、根据权利要求8或9所述的半导体装置的制造方法,其中,
将所述第1树脂层,形成为以不重合于所述半导体基板的切断部分。
11、根据权利要求8至10的任一项所述的半导体装置的制造方法,其中,
在形成所述贯通电极的工序中,
将贯通所述能动面上所形成的所述集成电路的导电部的孔,形成在所述半导体基板的能动面上;
在所述孔内形成导电部;
通过将所述半导体基板从背面侧进行薄厚加工,形成贯通电极。
12、根据权利要求8至10的任一项所述的半导体装置的制造方法,其中,
在所述半导体基板的背面,形成至少使所述贯通电极露出的第3树脂层。
13、根据权利要求12所述的半导体装置的制造方法,其中,
在形成所述第3树脂层时,通过利用感光性树脂而进行曝光、显影,形成至少使在所述背面上突出的贯通电极露出的开口,
在形成所述开口后,通过流动溶解了的树脂而使所述贯通电极和所述第3树脂层接触,将所述感光性树脂固化。
14、据权利要求12所述的半导体装置的制造方法,其中,
在形成所述第3树脂层时,用所述第3树脂以覆盖所述贯通电极的方
式进行涂布后,通过等离子体处理使所述贯通电极露出。
15、根据权利要求12所述的半导体装置的制造方法,其中
在形成所述第3树脂层时,通过聚合物薄膜覆盖所述贯通电极,在该状态下进行加热的同时进行压接,在所述聚合物薄膜上,贯通从所述背面侧突出了的贯通电极。
16、一种电路基板,具备了权利要求1至7中的任一项所述的半导体装置。
17、一种电子仪器,具备了根据权利要求16所述的电路基板。
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