CN1839465A - 掩蔽法 - Google Patents

掩蔽法 Download PDF

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CN1839465A
CN1839465A CNA2004800241784A CN200480024178A CN1839465A CN 1839465 A CN1839465 A CN 1839465A CN A2004800241784 A CNA2004800241784 A CN A2004800241784A CN 200480024178 A CN200480024178 A CN 200480024178A CN 1839465 A CN1839465 A CN 1839465A
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boron
amorphous carbon
substrate
masking material
doped amorphous
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CN1839465B (zh
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尹志平
G·S·桑德胡
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本发明涉及掩蔽法。在一个实施方案中，含硼掺杂的无定形碳的掩蔽材料在形成于半导体基底上的结构元件上形成。所述掩蔽材料包括至少约0.5原子％的硼。掩蔽材料基本上进行各向异性蚀刻，在结构元件侧壁上有效形成含硼掺杂无定形碳的被各向异性地蚀刻的侧壁隔离体。然后，对最接近隔离体的基底进行加工，同时使用含硼掺杂无定形碳的隔离体作为掩膜。在最接近隔离体的基底进行加工后，含硼掺杂无定形碳的隔离体从基底进行蚀刻。而且，也考虑了其它实施方案和方面。

Description

掩蔽法
技术领域
本发明涉及在集成电路制备中掩蔽半导体基底的方法。
背景技术
集成电路通常形成在半导体基底如硅晶片或其它半导体材料上。通常，使用半导体的、导电的或绝缘的各种材料层形成集成电路。作为举例，各种材料使用各种工艺进行掺杂、离子注入、沉积、蚀刻、生长等。半导体加工中一直在为减小单个电子元件尺寸这一持续目标而奋斗，因而集成电路变得更小且更密集。
用于使半导体基底形成图案和加工的一种技术是光刻法。这种技术通常包括光致抗蚀剂层的沉积，然后所述光致抗蚀剂层可以加工，以改进该层在某些溶剂中的溶解性。例如，光致抗蚀剂层的多个部分可以在通过掩模/标线的光化学能量下曝光，以改变曝光区域与未曝光区域相比于沉积状态溶解性的溶剂溶解性。随后，可以根据光致抗蚀剂种类除去曝光或未曝光部分，由此使光致抗蚀剂的掩模图案留在基底上。邻接着被掩蔽部分的基底的相邻面积可以例如通过蚀刻或离子注入进行加工，以使邻近掩蔽材料的基底进行所需加工。
在某些情况下，多个不同的光致抗蚀剂层可在给定掩蔽/光刻步骤中使用。此外，光刻掩蔽和形成图案可以与一个或多个其它层结合。这样的一种工艺在一层或多层光致抗蚀剂层沉积之前的基底上形成了通常所称的“硬掩膜”。然后，例如如上所述抗蚀剂层形成图案，以在该硬掩模上形成掩蔽块。然后，硬掩模使用作为掩模的光致抗蚀剂进行蚀刻，以使光致抗蚀剂的图案转移给硬掩模。随后，抗蚀剂可以立即除去或不立即除去。硬掩模，比如上面所描述的那种掩模比只使用抗蚀剂的情况可提供更坚固的掩蔽图案，例如抗蚀剂在蚀刻过程中应当完全被腐蚀/蚀刻除去的情况。
用作硬掩模的一种材料是无定形碳。当使用无定形碳作为硬掩模蚀刻氧化物材料时，氧化物通常以比除去无定形碳快约10倍的速率被蚀刻除去。
除光刻工艺比如上述的那种外，还存在其它掩蔽法。例如，场效应晶体管使用导电门极(conductive gate)，所述导电门极通常容纳在半导体材料通道区(channel region)上。导电掺杂源极/漏极半导体材料区域通常容纳在通道区的相反两侧，其间具有与这种通道区相重叠或位于这种通道区下的门极。在某些情况下，理想的是，穿过源极/漏极区域的掺杂剖面(dopingprofile)比源极/漏极区域的远端稍微没有那么接近通道区。提供这种掺杂剖面的一种工艺方法是首先在半导体基底的所需通道区上形成所需的导电门极外形。然后，利用阻止这种注入进入通道区的门极结构(gateconstruction)向基底的半导体材料中提供了合适注入量的增强导电性的杂质。然后，绝缘层可以共形地(conformally)沉积在门极结构上，并且进行各向异性蚀刻，在门极上形成绝缘侧壁隔离体。这些侧壁隔离体有效地起着掩模的作用，它可以保护门极侧壁以及阻止随后在刚形成的隔离体下发生的注入。因此，侧壁隔离体可以用作用于随后更高剂量源极/漏极注入的掩模，以完成所需源极/漏极区域外形的形成。
尽管本发明是为解决上述问题而进行的，但本发明决不是限制于这些。本发明只是受逐字描述的所附权利要求限制(说明书的其它部分或附图没有解释性或其它限制性参考对上述背景技术的描述)。
发明内容
本发明涉及掩蔽法。在一个实施方案中，包含硼掺杂的无定形碳的掩蔽材料在形成于半导体基底上的结构元件(feature)上形成。该掩蔽材料包括至少约0.5原子％的硼。该掩蔽材料基本上进行各向异性蚀刻，以在结构元件的侧壁上有效地形成各向异性蚀刻的含硼掺杂无定形碳的侧壁隔离体。然后，在最接近隔离体的地方对基底进行加工，同时使用含硼掺杂无定形碳的隔离体作为掩模。最接近隔离体的基底加工之后，将含硼掺杂无定形碳的隔离体从基底上蚀刻掉。
其它方面和实施方案也加以考虑。
附图说明
下面，参考下列附图，描述本发明的优选实施方案。
图1是在根据本发明一个方面的工艺步骤中半导体晶片碎片的示意性截面图。
图2所示为在图1所述工艺步骤之后的工艺步骤中的图1晶片碎片。
图3所示为在图2所述工艺步骤之后的工艺步骤中的图2晶片碎片。
图4是图3所述工艺步骤的备选/另外工艺步骤。
图5是图3所述工艺步骤的另一个备选/另外工艺步骤。
图6是图3所述工艺步骤的再另一个备选/另外工艺步骤。
图7所示为图3所述工艺步骤之后的工艺步骤中图3的晶片碎片。
图8所示为图7所述工艺步骤之后的工艺步骤中图7的晶片碎片。
图9是在根据本发明一个方面的工艺步骤中另一个半导体晶片碎片的示意性截面图。
图10所示为图9所述工艺步骤之后的工艺步骤中图9的晶片碎片。
图11所示为图10所述工艺步骤之后的工艺步骤中图10的晶片碎片。
图12所示为图11所述工艺步骤之后的工艺步骤中图11的晶片碎片。
图13是在根据本发明一个方面的工艺步骤中再另一个半导体晶片碎片的示意性截面图。
图14所示为图13所述工艺步骤之后的工艺步骤中图13的晶片碎片。
图15所示为图14所述工艺步骤之后的工艺步骤中图14的晶片碎片。
具体实施方案
下面，参考图1-8开始描述本发明示范性的掩蔽法。首先对于图1，半导体基底碎片通常使用标记数字10表示。在本文献的上下文中，术语“半导体基底”或“半导电基底”定义为表示含半导体材料的任一结构，包括但不限制于块状半导体材料如半导体晶片(单独或其上含其它材料的组件)以及半导体材料层(单独或其上含其它材料的组件)。术语“基底”指的是任意支撑结构，包括但不限制于上述的半导体基底。而且在本文献的上下文中，除非另有说明，否则术语“层”包括单层和多层。
在所描述的实施例中，基底10包括块状单晶硅基底12。其上形成某结构元件14。是存在还是仍要发展的任何可识别结构元件都在考虑之中。只作为举例，这些实例包括形成图案的光致抗蚀剂层、部分或完全场效应晶体管门极或其它电路结构，在基底内的蚀刻区域、等。只作为举例，图1中的结构元件14被描述为在基底上12上形成的一些有图案材料的形式。这样的结构元件具有在所解释的实施方案中基本上垂直于相对基底12的方向的侧壁16。包括、基本上由、或由硼掺杂无定形碳构成的掩蔽材料18形成在结构元件14上。这样的掩蔽材料包括至少约0.5原子％的硼。一个示例性的优选实施方案包括约1.0原子％～约16原子％的硼浓度。只作为举例，备选实施例包括1.0原子％～5.0原子％的硼；更大的是从大于5.0原子％到10.0原子％的硼；再更大为从大于10.0原子％到15.0原子％的硼；还更大为从大于15.0原子％到20.0原子％的硼；还再更大为从大于20.0原子％到75.0原子％的硼。
在一个示例性实施方案中，结构元件可以包括没有掺杂硼的无定形碳。在本文献的上下文中，“没有掺杂硼”意味着没有任何可检测到的硼。如果至少结构元件14的最外部分是没有掺杂硼的无定形碳，则掩蔽材料18将在其上形成(意味着接触)这种无定形碳材料。
形成硼掺杂的无定形碳材料18的一个优选实施例是使用化学气相沉积(CVD)进行，并且所述化学气相沉积可以用等离子体增强或不用等离子体增强。此外，硼掺杂可以在化学气相沉积过程中或之后进行。在一个优选实施方案中，化学气相沉积使用C2H6、C2H4、C2H2、C3H6和C3H8中的至少一种。此外，在一个优选实施方案中，化学气相沉积使用B2H6、B4H10和BH3CO中的至少一种，由此在沉积时将原样形成原位硼掺杂的无定型碳。
只作为举例，示范性的化学气相沉积工具包括从Applied Materials ofSanta Clara，California购买的涂敷材料Centura处理器(the Applied MaterialsCentura Processor)以及生产处理器(the Producer Processor)。此外并且只作为举例，下面提供了化学气相沉积材料18使用这样处理器的示范性优选方法。一种示范性加工气体为具有300sccm～900sccm示范性流速的C3H6，在具体实施例中，流速可以为600sccm。B2H6是示范性的硼源气体，它可以随C3H6流动，并且根据其它气体的流速以及根据在要形成的硼掺杂无定形碳层中的所需硼浓度，其示范性流速为100sccm～2000sccm。也可以使用其它示范性载体或其它反应性或非反应性气体，例如，0sccm～500sccm的He和/或H2。在3托～7托的示范性优选压力范围内，示范性优选基底温度为400℃～650℃。从晶片表面到发射气体喷嘴的示范性优选距离为190mils到240mils。在电容偶合、单电极等离子体沉积工具(如上所述那些)中的示范性优选应用功率范围对于200mm晶片为100瓦～800瓦。此外，只作为举例，示范性非等离子体增强的CVD参数包括约500～800℃的温度、50～200毫托的压力、50sccm～1000sccm的C3H6流速，100sccm～2000sccm的B2H6流速，以及存在或不存在任何He和/或H2。
沉积过程中的硼掺杂量确定影响到材料18在结构元件各阶梯的沉积共形性(conformality)。一般地说，硼浓度越高，阶梯覆盖(step coverage)越好。例如，在上述参数范围内，B2H6与C3H6的体积流量比为0.4时给出在相对于水平表面的垂直阶梯上的覆盖率约为26％，而B2H6与C3H6的流量比为2.1时相比于水平表面给出在垂直阶梯上的覆盖率约为64％。0.4的比率使材料18中原子硼浓度约为3.0％硼，而2.1的流量比使原子硼浓度约为16％硼。确定电极上的RF功率，使其相对于共形性不会有特别影响。在一个示范性的相当于实用的实施例中，喷头/晶片表面距离为215mils，功率为250瓦，前体流速B2H6为1250sccm，C3H6为650sccm，基底温度为550℃以及室压力为5托时，相对于水平表面垂直线上的阶梯覆盖为约74％。根据应用，可以有或没有理想的高度共形性。
参考图2，掩蔽材料18基本上进行各向异性蚀刻，以在结构元件14的侧壁16上有效形成包括硼掺杂无定形碳的各向异性蚀刻的侧壁隔离体20。只作为举例，用于各向异性蚀刻这种材料的示范性工艺包括使用5sccm～20sccm的CF4和/或其它含氟化物的气体的组合，20sccm～60sccm的SO2，以及50sccm～120sccm的O2。示范性基底温度为5～75℃，室压力为5毫托～15毫托，源极等离子体功率为150～250W，每200mm晶片直径的偏压为30～100瓦。
含硼掺杂无定形碳的隔离体接着用作掩膜，同时加工最接近所述隔离体的基底。只作为举例，这种使用含硼掺杂无定形碳的隔离体作为掩膜对基底进行的加工可以包括将离子注入基底、蚀刻基底和在基底上沉积中的任一种或它们的组合。例如，图3描述了离子注入形式的形成扩散区域22的示范性加工。图4描述了蚀刻形式的形成相对于基底的凹口或槽部分24的示范性加工。图5作为举例描述了在基底12上沉积出层26的沉积工艺，它是利用用作掩膜的含硼掺杂无定形碳的隔离体20立即在被隔离体20所覆盖的基底材料12上沉积层26。图6只是举例描述了用含硼掺杂无定形碳的隔离体20掩蔽在该加工下的基底材料12，在基底材料12上/从基底材料12选择性沉积/加工形成层28的一些形式。只作为举例，这样可以构成外延硅生长和/或热加工和/或其它已存在或仍待开发的选择性沉积/形成方法。
在基底的这种加工之后，含硼掺杂无定形碳的隔离体从基底进行蚀刻。图7示范性描述了图3所述加工工艺之后的加工工艺。一种用于蚀刻含硼掺杂无定形碳的隔离体的最优选工艺使用含氧等离子体。只作为举例，示范性优选工艺使用O2灰化等离子体室，该室的基底温度为300～650℃、基底与喷头距离为400～800mils、压力为4～9托、O2气流量为1000～2500sccm、等离子体功率范围为200～1000瓦。在这种条件下的加工可以在约75秒内使含硼掺杂无定形碳的隔离体的1500埃厚度的膜基本上各向同性蚀刻，所述隔离体由0.5～1.0％硼构成。
结合上述加工工艺，发现硼掺杂浓度使阶梯覆盖和各向同性只含O2(O2-only)的等离子体蚀刻容易度之间获得平衡。尽管越高的硼浓度导致约好的阶梯覆盖，但是越高的硼浓度，只含O2的等离子体从基底蚀刻这种材料会越困难。当硼掺杂超过10原子％时，在上述条件下的只含O2的等离子体蚀刻会认为变得不能接受的低/缓慢。只作为举例，含CF4的蚀刻气体蚀刻含无定形碳的隔离体时，这种蚀刻与硼掺杂量无关。
在从基底上蚀刻牺牲隔离体(sacrificial spacer)过程中可以使用含O2等离子体会提供特殊的优点，因为这种蚀刻可以在对二氧化硅、氮化硅、单晶硅和多晶硅中的任一种基本上有选择性的上述条件下进行。在可比较蚀刻速率中的这种主要选择性是硼掺杂无定形碳与二氧化硅、氮化硅、单晶硅和多晶硅中的任一种相比为至少2∶1。因此，如果存在任一种这样的材料，即在从基底上蚀刻含硼掺杂无定形碳的牺牲隔离体之前或过程中立即暴露在基底上的材料，则这种蚀刻对这些暴露材料中的任一种都可以是有利地有选择性的。
参考图8，并且在一个示范性实施方案中，结构元件14(未示出)也从基底蚀刻。当然，这种蚀刻能够在从基底蚀刻含硼掺杂无定形碳的隔离体20之前或之后进行。备选地，根据所形成的结构和所形成结构元件的可能种类，结构元件可以残留在基底上一段时间或构成一部分已完成/最终电路结构。
只作为举例的备选示范性工艺参考图9～12进行描述。图9描述了一种包括半导体基底材料42的基底碎片40。在基底材料42上形成一对门极结构44和46。只作为举例，该门极结构包括门极氧化层48、导电多晶硅层50、耐火金属或耐火金属硅化物层52以及绝缘盖54。门极结构44和46可以看作一对其上可以形成有上述掩蔽材料并且随后进行上述加工的相邻结构元件。在一个示范性被考虑的方面，结构元件44和46可以通过使用具有某一最小开口尺寸例如相应于结构元件44和46的最接近壁之间分离距离的尺寸“A”的掩膜的光刻工艺形成。在掩膜/标线内的尺寸“A”可以比图9所示结构之间的所得尺寸“A”稍小或稍大，例如，这取决于光刻工艺方面和/或误差。在一个所考虑的实施方案中，这种最小的开口尺寸(例如尺寸“A”)理想上是在此处描述的掩蔽法之前或之后的半导体基底的任一种或所有光刻工艺中使用的最小开口尺寸。例如，在结构元件44和46之间通过光刻工艺获得的距离可以是在基底加工时可生产工艺中技术上可获得的最小尺寸。示范性扩散区域58相对于基底42形成。
参考图10，含硼掺杂无定形碳的掩蔽材料60在所解释的结构元件和基底上形成。这种材料优选具有与第一所述实施方案的掩蔽材料18相同的任一种上述属性。
参考图11，掩蔽材料60已经被基本上各向异性蚀刻，有效形成多对间隔-相邻各向异性蚀刻侧壁隔离体62和侧壁隔离体64。相邻各向异性蚀刻侧壁隔离体62被最短距离“B”隔开，所述最短距离“B”比图9尺寸“A”所示范的最小开口尺寸小。最靠近隔离体的基底的示范性加工以注入形成区域66并且最靠近隔离体的方式进行。
参考图12，含硼掺杂无定形碳的隔离体62和64例如使用上述工艺从基底进行蚀刻。
只作为举例的备选示范性工艺参考图13-15进行描述。图13描述了一种含半导体基底材料72的基底碎片70。在材料72上形成层74例如二氧化硅。在材料74上接收了另一层76，例如没有掺杂硼的无定形碳。具有壁78的开口77穿过层76形成。壁78可以看作是层76的相邻结构元件的局部，所述层76至少限定开口77的某一部分。在一个示范性被考虑的方面，结构元件78可以通过使用具有某一最小开口尺寸的掩膜的光刻工艺形成，所述最小开口尺寸例如相当于限定开口77的最接近壁之间的分隔距离的尺寸“C”。当使用上述尺寸“A”时，在掩膜/标线内的尺寸“C”可以比图13所示结构之间的所得尺寸“C”稍小或稍大，例如，这取决于光刻工艺方面和/或误差。在一个被考虑的实施方式中，这种最小开口尺寸(例如，尺寸“C”)理想上是在此处描述的掩蔽法之前或之后的半导体基底的任一种或所有光刻工艺中使用的最小开口尺寸。例如，在结构元件78之间通过光刻工艺获得的间隔可以是在基底加工时可生产工艺中技术上可获得的最小尺寸。
含硼掺杂无定形碳的掩蔽材料80在所解释的结构元件和基底上形成。这种材料优选具有与第一所述实施方案的掩蔽材料18相同的任一种上述属性。
参考图14，掩蔽材料80已经基本上被各向异性蚀刻，有效形成多对间隔-相邻各向异性蚀刻侧壁隔离体82。相邻各向异性蚀刻侧壁隔离体82被最短距离“D”隔开，所述最短距离“D”比图13尺寸“C”所示范的最小开口尺寸小。最靠近隔离体的基底的示范性加工以蚀刻层74方式进行，以形成对最靠近隔离体82的基底材料72的开口84。
参考图15，含硼掺杂无定形碳的隔离体82例如使用上述工艺从基底进行蚀刻。
此处并入美国专利申请系列号10/463,185，作为参考，该专利是在2003年6月17日提交的，题目为“Boron-Doped Amorphous Carbon Film For UseAs A Hard Etch Mask During The Formation of A Semiconductor Device”，发明人为Zhiping Yin和Gurtej Sandhu。

Claims (44)

1.一种掩蔽法，其包括如下步骤：
在形成于半导体基底上的结构元件上形成含硼掺杂无定形碳的掩蔽材料，所述掩蔽材料包括至少约0.5原子％的硼；
基本上各向异性地蚀刻掩蔽材料，以在所述结构元件侧壁上有效形成含硼掺杂无定形碳的被各向异性蚀刻的侧壁隔离体；
使用含硼掺杂无定形碳的所述隔离体作为掩膜，同时加工最靠近该隔离体的基底；和
基底进行所述加工之后，从基底上蚀刻含硼掺杂无定形碳的所述隔离体。
2.根据权利要求1的方法，其中在其上形成掩蔽材料的结构元件包括没有掺杂硼的无定形碳。
3.根据权利要求2的方法，其中所述掩蔽材料形成在没有掺杂硼的无定形碳上。
4.根据权利要求1的方法，其中所述掩蔽材料形成在一对相邻结构元件上，所述基本上各向异性地蚀刻有效形成一对间隔、相邻的被各向异性地蚀刻的侧壁隔离体。
5.根据权利要求4的方法，其中，
所述相邻结构元件通过使用具有最小开口尺寸的掩膜的光刻工艺形成；所述最小开口尺寸是在所述掩蔽法之前和之后的半导体基底的任意和所有光刻工艺中使用的最小开口尺寸；和
所述相邻的被各向异性地蚀刻的侧壁隔离体被分开最短距离，所述最短距离比最小开口尺寸更小。
6.根据权利要求1的方法，其中所述掩蔽材料基本上由硼掺杂无定形碳组成。
7.根据权利要求1的方法，其中所述掩蔽材料由硼掺杂无定形碳组成。
8.根据权利要求1的方法，其中所述形成包括CVD。
9.根据权利要求8的方法，其中所述CVD是等离子体增强的。
10.根据权利要求8的方法，其中所述CVD不是等离子体增强的。
11.根据权利要求8的方法，其中硼掺杂在CVD过程中进行。
12.根据权利要求8的方法，其中硼掺杂在CVD之后进行。
13.根据权利要求1的方法，其中所述形成包括使用C2H6、C2H4、C2H2、C3H6和C3H8中至少一种的CVD；以及包括使用B2H6、B4H10和BH3CO中至少一种的CVD。
14.根据权利要求13的方法，其中所述CVD是等离子体增强的。
15.根据权利要求13的方法，其中所述CVD不是等离子体增强的。
16.根据权利要求1的方法，其中所述结构元件侧壁基本上垂直于基底。
17.根据权利要求1的方法，其中所述掩蔽材料包括1.0原子％～5.0原子％的硼。
18.根据权利要求1的方法，其中所述掩蔽材料包括从大于5.0原子％到10.0原子％的硼。
19.根据权利要求1的方法，其中所述掩蔽材料包括从大于10.0原子％到15.0原子％的硼。
20.根据权利要求1的方法，其中所述掩蔽材料包括从大于15.0原子％到20.0原子％的硼。
21.根据权利要求1的方法，其中所述掩蔽材料包括从大于20.0原子％到75.0原子％的硼。
22.根据权利要求1的方法，其中使用含硼掺杂无定形碳的隔离体作为掩膜进行的基底加工包括蚀刻所述基底。
23.根据权利要求1的方法，其中使用含硼掺杂无定形碳的隔离体作为掩膜进行的基底加工包括将离子注入到基底中。
24.根据权利要求1的方法，其中使用含硼掺杂无定形碳的隔离体作为掩膜进行的基底加工包括在基底上的沉积。
25.根据权利要求1的方法，其中蚀刻使用含O2的等离子体。
26.根据权利要求1的方法，还包括，在所述基底加工之后，从基底蚀刻结构元件。
27.根据权利要求26的方法，其中含硼掺杂无定形碳的隔离体从基底蚀刻之后，将所述结构元件从基底进行蚀刻。
28.一种掩蔽法，其包括如下步骤：
在形成于半导体基底上的结构元件上化学气相沉积含硼掺杂无定形碳的掩蔽材料，所述掩蔽材料包括约1.0原子％到约20原子％的硼；
基本上各向异性地蚀刻掩蔽材料，以在所述结构元件的侧壁上有效形成含硼掺杂无定形碳的被各向异性地蚀刻的侧壁隔离体；
使用含硼掺杂无定形碳的所述隔离体作为掩膜，同时加工离隔离体最近的基底；和
在基底进行所述加工之后，使用含O2等离子体从基底上蚀刻含硼掺杂无定形碳的隔离体，所述含氧等离子体对暴露的二氧化硅、氮化硅和硅中的至少一种基本上有选择性。
29.根据权利要求28的方法，其中在其上形成掩蔽材料的结构元件包括没有掺杂硼的无定形碳。
30.根据权利要求29的方法，其中所述掩蔽材料形成在没有掺杂硼的无定形碳上。
31.根据权利要求28的方法，其中所述掩蔽材料形成在一对相邻结构元件上，所述基本上各向异性地蚀刻对于形成一对间隔、相邻的被各向异性地蚀刻的侧壁隔离体是有效的。
32.根据权利要求31的方法，其中，
所述相邻结构元件通过使用具有最小开口尺寸的掩膜的光刻工艺形成；所述最小开口尺寸是在所述掩蔽法之前和之后的半导体基底的任意和所有光刻工艺中所使用的最小开口尺寸；和
所述相邻的被各向异性地蚀刻的侧壁隔离体被分开最短距离，所述最短距离比最小开口尺寸更小。
33.根据权利要求28的方法，其中所述掩蔽材料基本上由硼掺杂无定形碳组成。
34.根据权利要求28的方法，其中所述CVD是等离子体增强的。
35.根据权利要求28的方法，其中所述CVD不是等离子体增强的。
36.根据权利要求28的方法，其中硼掺杂在CVD过程中进行。
37.根据权利要求28的方法，其中硼掺杂在CVD之后进行。
38.根据权利要求28的方法，其中所述化学气相沉积使用C2H6、C2H4、C2H2、C3H6和C3H8中至少一种；以及使用B2H6、B4H10和BH3CO中至少一种。
39.根据权利要求28的方法，其中所述结构元件侧壁基本上垂直于所述基底。
40.根据权利要求28的方法，其中使用含硼掺杂无定形碳的隔离体作为掩膜的基底加工包括蚀刻所述基底。
41.根据权利要求28的方法，其中使用含硼掺杂无定形碳的隔离体作为掩膜的基底加工包括将离子注入到基底中。
42.根据权利要求28的方法，其中使用含硼掺杂无定形碳的隔离体作为掩膜的基底加工包括在基底上的沉积。
43.根据权利要求28的方法，还包括在所述基底加工后，从基底上蚀刻所述结构元件。
44.根据权利要求43的方法，其中含硼掺杂无定形碳从基底蚀刻之后，所述结构元件从基底蚀刻。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102637581A (zh) * 2012-04-06 2012-08-15 上海华力微电子有限公司 一种防止硼掺杂层释气的方法
CN103975388A (zh) * 2011-12-16 2014-08-06 应用材料公司 通过为硬盘驱动器图案化媒体应用c掺杂的磁性媒体的去磁
CN105529250A (zh) * 2014-09-30 2016-04-27 中芯国际集成电路制造(上海)有限公司 高能离子注入方法及半导体结构

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100498475B1 (ko) * 2003-01-07 2005-07-01 삼성전자주식회사 모스 전계 효과 트랜지스터 구조 및 그 제조 방법
US7105431B2 (en) * 2003-08-22 2006-09-12 Micron Technology, Inc. Masking methods
US6936539B2 (en) * 2003-09-24 2005-08-30 Micron Technology, Inc. Antireflective coating for use during the manufacture of a semiconductor device
US6998657B2 (en) * 2003-10-21 2006-02-14 Micron Technology, Inc. Single poly CMOS imager
US7354631B2 (en) * 2003-11-06 2008-04-08 Micron Technology, Inc. Chemical vapor deposition apparatus and methods
US7115524B2 (en) * 2004-05-17 2006-10-03 Micron Technology, Inc. Methods of processing a semiconductor substrate
US20060166423A1 (en) * 2005-01-21 2006-07-27 Seiji Iseda Removal spacer formation with carbon film
US7842558B2 (en) 2006-03-02 2010-11-30 Micron Technology, Inc. Masking process for simultaneously patterning separate regions
US7476933B2 (en) 2006-03-02 2009-01-13 Micron Technology, Inc. Vertical gated access transistor
US7902074B2 (en) * 2006-04-07 2011-03-08 Micron Technology, Inc. Simplified pitch doubling process flow
KR100898659B1 (ko) * 2006-08-09 2009-05-22 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조방법
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8481417B2 (en) 2007-08-03 2013-07-09 Micron Technology, Inc. Semiconductor structures including tight pitch contacts and methods to form same
US7790531B2 (en) 2007-12-18 2010-09-07 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
US7892900B2 (en) * 2008-04-07 2011-02-22 Globalfoundries Singapore Pte. Ltd. Integrated circuit system employing sacrificial spacers
JP2009295785A (ja) * 2008-06-05 2009-12-17 Toshiba Corp 半導体装置の製造方法
US8101497B2 (en) 2008-09-11 2012-01-24 Micron Technology, Inc. Self-aligned trench formation
US8093146B2 (en) * 2010-03-17 2012-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating gate electrode using a hard mask with spacers
TW201216331A (en) 2010-10-05 2012-04-16 Applied Materials Inc Ultra high selectivity doped amorphous carbon strippable hardmask development and integration
CN102456553B (zh) * 2010-10-29 2015-05-20 中芯国际集成电路制造(上海)有限公司 一种掺杂阱的制作方法
US9299581B2 (en) * 2011-05-12 2016-03-29 Applied Materials, Inc. Methods of dry stripping boron-carbon films
KR20130075158A (ko) 2011-12-27 2013-07-05 삼성전자주식회사 반도체 소자의 제조 방법
US8609529B2 (en) 2012-02-01 2013-12-17 United Microelectronics Corp. Fabrication method and structure of through silicon via
JP2013197417A (ja) 2012-03-21 2013-09-30 Toshiba Corp 不揮発性半導体記憶装置の製造方法
WO2013180179A1 (ja) * 2012-06-01 2013-12-05 東京エレクトロン株式会社 プラズマエッチング方法
US20140216498A1 (en) 2013-02-06 2014-08-07 Kwangduk Douglas Lee Methods of dry stripping boron-carbon films
WO2015069613A1 (en) * 2013-11-06 2015-05-14 Mattson Technology, Inc. Novel mask removal process strategy for vertical nand device
JP2017507477A (ja) 2014-01-08 2017-03-16 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ アモルファスカーボンフィルムの中へのイオン注入による高エッチング選択性ハードマスク材料の開発
US10418243B2 (en) 2015-10-09 2019-09-17 Applied Materials, Inc. Ultra-high modulus and etch selectivity boron-carbon hardmask films
CN116631865A (zh) * 2016-01-20 2023-08-22 应用材料公司 用于侧向硬模凹槽减小的混合碳硬模
KR102262750B1 (ko) * 2016-03-28 2021-06-10 주식회사 히타치하이테크 플라스마 처리 방법 및 플라스마 처리 장치
US10580661B2 (en) 2016-12-14 2020-03-03 Mattson Technology, Inc. Atomic layer etch process using plasma in conjunction with a rapid thermal activation process
CN108400085B (zh) 2017-02-06 2019-11-19 联华电子股份有限公司 形成半导体元件图案的方法
JP2019036650A (ja) * 2017-08-17 2019-03-07 株式会社Ｓｃｒｅｅｎホールディングス 基板エッチング方法
CN112437973A (zh) * 2019-06-26 2021-03-02 株式会社日立高新技术 等离子处理方法
JP7202489B2 (ja) * 2019-06-26 2023-01-11 株式会社日立ハイテク プラズマ処理方法

Family Cites Families (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1582231A (en) * 1976-08-13 1981-01-07 Nat Res Dev Application of a layer of carbonaceous material to a surface
US4436797A (en) * 1982-06-30 1984-03-13 International Business Machines Corporation X-Ray mask
US4510176A (en) * 1983-09-26 1985-04-09 At&T Bell Laboratories Removal of coating from periphery of a semiconductor wafer
US4675265A (en) * 1985-03-26 1987-06-23 Fuji Electric Co., Ltd. Electrophotographic light-sensitive element with amorphous C overlayer
US4732785A (en) * 1986-09-26 1988-03-22 Motorola, Inc. Edge bead removal process for spin on films
JPS63210275A (ja) 1987-02-24 1988-08-31 Semiconductor Energy Lab Co Ltd プラズマ反応装置内を清浄にする方法
US4886728A (en) * 1988-01-06 1989-12-12 Olin Hunt Specialty Products Inc. Use of particular mixtures of ethyl lactate and methyl ethyl ketone to remove undesirable peripheral material (e.g. edge beads) from photoresist-coated substrates
US4994404A (en) * 1989-08-28 1991-02-19 Motorola, Inc. Method for forming a lightly-doped drain (LDD) structure in a semiconductor device
US5198263A (en) 1991-03-15 1993-03-30 The United States Of America As Represented By The United States Department Of Energy High rate chemical vapor deposition of carbon films using fluorinated gases
US5260236A (en) 1991-06-07 1993-11-09 Intel Corporation UV transparent oxynitride deposition in single wafer PECVD system
US5433794A (en) * 1992-12-10 1995-07-18 Micron Technology, Inc. Spacers used to form isolation trenches with improved corners
KR100188508B1 (ko) * 1993-03-26 1999-06-01 세끼사와 다까시 비정질탄소막을 사용하는 패턴형성방법과 에칭방법 및 비정질탄소막 형성방법
US5508368A (en) 1994-03-03 1996-04-16 Diamonex, Incorporated Ion beam process for deposition of highly abrasion-resistant coatings
US5679215A (en) 1996-01-02 1997-10-21 Lam Research Corporation Method of in situ cleaning a vacuum plasma processing chamber
US6218237B1 (en) * 1996-01-03 2001-04-17 Micron Technology, Inc. Method of forming a capacitor
US5754390A (en) * 1996-01-23 1998-05-19 Micron Technology, Inc. Integrated capacitor bottom electrode for use with conformal dielectric
US6653733B1 (en) 1996-02-23 2003-11-25 Micron Technology, Inc. Conductors in semiconductor devices
US5952050A (en) * 1996-02-27 1999-09-14 Micron Technology, Inc. Chemical dispensing system for semiconductor wafer processing
US5814433A (en) * 1996-05-17 1998-09-29 Clariant Finance (Bvi) Limited Use of mixtures of ethyl lactate and N-methyl pyrollidone as an edge bead remover for photoresists
US6291315B1 (en) 1996-07-11 2001-09-18 Denso Corporation Method for etching trench in manufacturing semiconductor devices
US5788778A (en) 1996-09-16 1998-08-04 Applied Komatsu Technology, Inc. Deposition chamber cleaning technique using a high power remote excitation source
US6066548A (en) 1996-10-31 2000-05-23 Micron Technology, Inc. Advance metallization process
US6188097B1 (en) * 1997-07-02 2001-02-13 Micron Technology, Inc. Rough electrode (high surface area) from Ti and TiN
US6333255B1 (en) * 1997-08-21 2001-12-25 Matsushita Electronics Corporation Method for making semiconductor device containing low carbon film for interconnect structures
JPH11214290A (ja) 1998-01-29 1999-08-06 Miyazaki Oki Electric Co Ltd レジスト膜及び半導体装置の製造方法
US6417108B1 (en) * 1998-02-04 2002-07-09 Canon Kabushiki Kaisha Semiconductor substrate and method of manufacturing the same
US20010048095A1 (en) * 1998-07-01 2001-12-06 Steven N. Towle Method for improving thermal stability of fluorinated amorphous carbon low dielectric constant materials
US6475868B1 (en) * 1999-08-18 2002-11-05 Advanced Micro Devices, Inc. Oxygen implantation for reduction of junction capacitance in MOS transistors
US6306702B1 (en) * 1999-08-24 2001-10-23 Advanced Micro Devices, Inc. Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate length
US6472283B1 (en) * 1999-09-24 2002-10-29 Advanced Micro Devices, Inc. MOS transistor processing utilizing UV-nitride removable spacer and HF etch
US6344396B1 (en) * 1999-09-24 2002-02-05 Advanced Micro Devices, Inc. Removable spacer technology using ion implantation for forming asymmetric MOS transistors
US6342423B1 (en) * 1999-09-24 2002-01-29 Advanced Micro Devices, Inc. MOS-type transistor processing utilizing UV-nitride removable spacer and HF etch
KR20010063852A (ko) * 1999-12-24 2001-07-09 박종섭 반도체소자의 자기정렬적인 콘택 형성방법
KR100767762B1 (ko) 2000-01-18 2007-10-17 에이에스엠 저펜 가부시기가이샤 자가 세정을 위한 원격 플라즈마 소스를 구비한 cvd 반도체 공정장치
US6297112B1 (en) * 2000-02-04 2001-10-02 United Microelectronics Corp. Method of forming a MOS transistor
US6476432B1 (en) * 2000-03-23 2002-11-05 Micron Technology, Inc. Structures and methods for enhancing capacitors in integrated circuits
US6453916B1 (en) * 2000-06-09 2002-09-24 Advanced Micro Devices, Inc. Low angle solvent dispense nozzle design for front-side edge bead removal in photolithography resist process
US6368986B1 (en) * 2000-08-31 2002-04-09 Micron Technology, Inc. Use of selective ozone TEOS oxide to create variable thickness layers and spacers
US6524775B1 (en) * 2000-10-20 2003-02-25 Clariant Finance (Bvi) Limited Edge bead remover for thick film photoresists
US6901512B2 (en) * 2000-12-12 2005-05-31 Hewlett-Packard Development Company, L.P. Centralized cryptographic key administration scheme for enabling secure context-free application operation
US6495312B1 (en) * 2001-02-01 2002-12-17 Lsi Logic Corporation Method and apparatus for removing photoresist edge beads from thin film substrates
JP4304884B2 (ja) * 2001-06-06 2009-07-29 日本電気株式会社 半導体装置及びその製造方法
JP2002368194A (ja) 2001-06-08 2002-12-20 Sanyo Electric Co Ltd 化合物半導体スイッチ回路装置
JP4131786B2 (ja) * 2001-09-03 2008-08-13 株式会社東芝 半導体装置の製造方法およびウエハ構造体
US6786996B2 (en) * 2001-10-16 2004-09-07 Applied Materials Inc. Apparatus and method for edge bead removal
US6767692B1 (en) 2001-11-28 2004-07-27 Lsi Logic Corporation Process for inhibiting edge peeling of coating on semiconductor substrate during formation of integrated circuit structure thereon
EP1324414A3 (en) 2001-12-25 2003-11-26 Matsushita Electric Industrial Co., Ltd. Hydrogen generation system and fuel cell system having the same
US6559017B1 (en) * 2002-06-13 2003-05-06 Advanced Micro Devices, Inc. Method of using amorphous carbon as spacer material in a disposable spacer process
US6500756B1 (en) * 2002-06-28 2002-12-31 Advanced Micro Devices, Inc. Method of forming sub-lithographic spaces between polysilicon lines
US6605514B1 (en) * 2002-07-31 2003-08-12 Advanced Micro Devices, Inc. Planar finFET patterning using amorphous carbon
US6815308B2 (en) * 2002-08-15 2004-11-09 Micron Technology, Inc. Use of a dual-tone resist to form photomasks including alignment mark protection, intermediate semiconductor device structures and bulk semiconductor device substrates
US6875664B1 (en) * 2002-08-29 2005-04-05 Advanced Micro Devices, Inc. Formation of amorphous carbon ARC stack having graded transition between amorphous carbon and ARC material
US7126198B2 (en) * 2002-09-03 2006-10-24 Agere Systems Inc. Protruding spacers for self-aligned contacts
US20040077178A1 (en) * 2002-10-17 2004-04-22 Applied Materials, Inc. Method for laterally etching a semiconductor structure
US6750127B1 (en) * 2003-02-14 2004-06-15 Advanced Micro Devices, Inc. Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance
US6939794B2 (en) 2003-06-17 2005-09-06 Micron Technology, Inc. Boron-doped amorphous carbon film for use as a hard etch mask during the formation of a semiconductor device
US20050080160A1 (en) 2003-08-14 2005-04-14 Seabrook Samuel G. Paints, coatings and polymers containing phytochemical agents and methods for making and using same
US7105431B2 (en) 2003-08-22 2006-09-12 Micron Technology, Inc. Masking methods
US7129180B2 (en) 2003-09-12 2006-10-31 Micron Technology, Inc. Masking structure having multiple layers including an amorphous carbon layer
US7132201B2 (en) 2003-09-12 2006-11-07 Micron Technology, Inc. Transparent amorphous carbon structure in semiconductor devices
US7354631B2 (en) * 2003-11-06 2008-04-08 Micron Technology, Inc. Chemical vapor deposition apparatus and methods
US7115524B2 (en) * 2004-05-17 2006-10-03 Micron Technology, Inc. Methods of processing a semiconductor substrate
US7074710B2 (en) 2004-11-03 2006-07-11 Lsi Logic Corporation Method of wafer patterning for reducing edge exclusion zone

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103975388A (zh) * 2011-12-16 2014-08-06 应用材料公司 通过为硬盘驱动器图案化媒体应用c掺杂的磁性媒体的去磁
US10233538B2 (en) 2011-12-16 2019-03-19 Applied Materials, Inc. Demagnetization of magnetic media by C doping for HDD patterned media application
CN102637581A (zh) * 2012-04-06 2012-08-15 上海华力微电子有限公司 一种防止硼掺杂层释气的方法
CN105529250A (zh) * 2014-09-30 2016-04-27 中芯国际集成电路制造(上海)有限公司 高能离子注入方法及半导体结构
CN105529250B (zh) * 2014-09-30 2020-10-09 中芯国际集成电路制造(上海)有限公司 高能离子注入方法及半导体结构

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