CN1846307B - 喷涂或层压处理厚ild层的方法及装置 - Google Patents

喷涂或层压处理厚ild层的方法及装置 Download PDF

Info

Publication number
CN1846307B
CN1846307B CN200480025653XA CN200480025653A CN1846307B CN 1846307 B CN1846307 B CN 1846307B CN 200480025653X A CN200480025653X A CN 200480025653XA CN 200480025653 A CN200480025653 A CN 200480025653A CN 1846307 B CN1846307 B CN 1846307B
Authority
CN
China
Prior art keywords
metal level
layer
interconnect metal
backend interconnect
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN200480025653XA
Other languages
English (en)
Other versions
CN1846307A (zh
Inventor
R·马特尔
P·穆恩
D·艾尔斯
R·利斯特
S·金
S·托勒
K·李
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority claimed from PCT/US2004/028949 external-priority patent/WO2005024912A2/en
Publication of CN1846307A publication Critical patent/CN1846307A/zh
Application granted granted Critical
Publication of CN1846307B publication Critical patent/CN1846307B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明涉及一种在可控塌陷芯片连接(C4)凸块下、在管芯或晶片级，用一个或多个厚金属层制造互连结构的工艺流程。该互连结构可被用于微处理器的后端互连。该工艺流程可包括在具有大纵横比结构的表面上通过喷涂或层压来形成层间电介质。

Description

喷涂或层压处理厚ILD层的方法及装置 
要求优先权 
此申请是2003年9月9日提交的、标题为“改进功率传输和机械减震的厚金属层集成工艺流程”的美国专利申请No.10/659,044的部分继续申请并要求其优先权，通过引用将其内容全部结合在此。 
技术领域
本发明涉及一种使用C4晶片级厚金属集成流程的喷涂或层压处理厚ILD层的方法。 
背景技术
每一代可用于微处理器的互补金属氧化物半导体(CMOS)电路在低压和高频运行时需要更多的晶体管。由于每个新生代晶体管的阻抗可降低的不只是电压，同时晶体管可泄漏更多电流，因此CMOS电路需要更多的电流。从基底经过焊料凸块和可控塌陷芯片连接(C4)凸块至管芯需要更高的电流。由于电子移动的不足，每个C4凸块只能够处理有限量的电流。在半导体行业中，C4凸块作为能够在管芯和基底之间提供电流的连接而被认知。 
发明内容
按照本发明的第一方面，提供一种装置，包含：第一凸块和第二凸块；第一厚金属层，与集成电路管芯的顶部金属层耦合，所述第一厚金属层在被第一电介质层基本包围的空间内形成，所述第一电介质层具有基本平坦的上表面；在所述第一厚金属层上的第二厚金属层，所述第二厚金属层与所述第一、所述第二凸块、以及所述第一厚金属层耦合，所述第一厚金属层和所述第二厚金属层可起到将电流从所述第一凸块和所述第二凸块传递到所述集成电路管芯的所述顶部金属层的作用。 
按照本发明的第二方面，提供一种一种方法，包含：形成第一基层金属化上的第一厚金属层，所述第一基层金属化与集成电路管芯的顶部金属层相接触；形成所述第一厚金属层上的第一基本平坦电介质层；形成通过第一电介质层的通道；在第二基层金属化上形成第二厚金属层，所述第二厚金属层利用通过所述第一电介质层的通道耦合到所述第一厚金属层；以及在所述第二厚金属层上形成凸块；其中所述第二厚金属层与所述第一厚金属层耦合，从而起到将电流从所述凸块传递到所述集成电路管芯的所述顶部金属层的作用。 
按照本发明的第三方面，还是提供一种方法，包含：形成第一表面上的第一金属结构，所述第一金属结构具有高于所述第一表面超过40微米的高度，所述第一金属结构与所述第一表面下的集成电路管芯的顶部金属层相接触；形成所述第一金属结构周围和其上的基本平坦的第一电介质层；以及形成通过所述第一电介质层到所述第一金属结构的通道；在第二表面上形成第二金属结构，所述第二金属结构具有高于所述第二表面超过40微米的高度，所述第二金属结构与通过所述第一电介质层到所述第一金属结构的通道相接触；在所述第二金属结构周围和其上形成基本平坦的第二电介质层。 
按照本发明的第四方面，还是一种装置，包含：第一凸块和第二凸块；第一厚金属层，与所述第一凸块和所述第二凸块耦合，所述第一厚金属层在第一电介质层的沟槽内形成；第二厚金属层，与所述第一厚金属层耦合，所述第二厚金属层在第二电介质层的沟槽内形成，所述第二厚金属层与集成电路管芯的顶部金属层耦合，所述第一厚金属层和所述第二厚金属层适于将电流从所述第一凸块和所述第二凸块传递到所述集成电路管芯的所述顶部金属层。 
按照本发明的第五方面，还是一种方法，包含：形成第一基层金属化上的第一厚金属层，所述第一基层金属化与集成电路管芯的顶部金属层耦合；形成所述第一厚金属层上的第一电介质层；形成所述第一电介质层内的通道；形成所述第一电介质层的所述通道内的第二基 层金属化；形成第二基层金属化上的第二厚金属层；形成所述第二厚金属层上的第二电介质层；以及形成所述第二电介质层上的凸块，所述第二厚金属层与所述第一厚金属层耦合，从而适于将电流从所述凸块传递到所述集成电路管芯的所述顶部金属层。 
按照本发明的第六方面，还是一种方法，包含：形成在第一阻挡晶种层上的第一厚金属层，所述第一阻挡晶种层与集成电路管芯的顶部金属层相接触；形成所述第一厚金属层上的第一钝化层；形成所述第一钝化层上的第一聚酰亚胺层；形成所述第一聚酰亚胺层内的通道；形成所述通道内的第二阻挡晶种层；形成在第二阻挡晶种层上的第二厚金属层，所述第二阻挡晶种层与所述第一厚金属层相接触；形成所述第二厚金属层上的第二钝化层；形成所述第二钝化层上的第二聚酰亚胺层；形成所述第二聚酰亚胺层内的通道；形成所述通道内的第三阻挡晶种层；以及形成所述第三阻挡晶种层上的第一和第二凸块。 
附图说明
图1A说明了可作为微处理器或其他设备的一部分的一种结构。 
图1B说明了图1A中的传统互连结构和凸块。 
图1C说明了图1A中的一部分结构。 
图1D给出的是图8A所示厚金属互连结构的一种简化形式。 
图2-8B说明了制造互连结构的不同阶段，所述的制造过程可用于图1A的结构。 
图9A和9B给出了制造图2-8B的结构的两个示例过程。 
图10说明了互连结构的一个可选用的实施例，该结构与图8A的互连结构类似，但是带有附加的扩散阻挡层。 
图11A给出了制造图10的互连结构的工艺流程的例子。 
图11B给出了制造图10的互连结构的一个可选用的工艺流程。 
图12给出了制造图13F所示的互连结构的工艺流程。 
图13A-13F说明了按照图12的工艺流程的互连结构的制作阶段。 
图14是与图1B的标准互连结构的电流和电压值相比较的、图8A 的互连结构的模拟参数和模拟结果表。 
图15A说明了图1B和图8A结构的C4通道(via)阻抗和C4最大电流之间的关系。 
图15B说明了图1B和图8A结构的C4阻抗和电压降(毫伏)之间的关系。 
图16比较了图1B的标准互连结构和图8A的具有两个厚金属层的结构的应力减少。 
图17说明了使用″自旋式″涂敷在具有大纵横比的外形结构的表面涂上厚电介质层的工具。 
图18A说明了表面刻有图案的厚(大纵横比)金属层结构。 
图18B说明了在厚金属层结构周围和其上形成的厚电介质层。 
图19说明了在具有大纵横比外形结构的表面涂上厚ILD层的喷涂工具。 
图20说明了在具有大纵横比外形结构的表面覆盖厚ILD层的层压方法。 
具体实施方式
图1A说明了可作为微处理器或其他带有集成电路的设备的一部分的一种结构150。结构150可包括主板120、插脚122、插座连接器124、插座126、基底128、焊料凸块130、可控塌陷芯片连接(C4)凸块112、互连结构100、管芯133(也称作晶片)、热界面材料132和完整的热量扩展器134。主板120可通过插脚122向基底128提供电流(供电)。基底128可通过焊料凸块130和C4凸块112向管芯133提供电流。C4凸块112可与焊料凸块130耦合，焊料凸块130附着在基底128上。C4凸块112可由铜，锡，石墨-锡(铅-锡)化合物等制成。 
图1B说明了图1A中传统的互连结构100。互连结构100(图1B)可作为微处理器后端互连的一部分位于管芯133(图1A)上。图1A和1B中的互连结构100可包括顶部金属层104，钝化层106，聚酰亚 胺层108，球状受限的金属化(ball limited metallization)(BLM)层110和C4凸块112A-112B。“BLM”还可代表基层金属化。在顶部金属层104下可以有若干金属层，并且在金属层下可以有晶体管。 
图1A和1B中的C4凸块112A-112B可将电流从焊料凸块130(图1A)传输到顶部金属层104(图1B)。顶部金属层104可将电流传输到位于顶部金属层104下面的金属层，并将电流传输到下面的、位于芯管133上的晶体管。顶部金属层104、在下面的金属层和晶体管可形成微处理器堆栈。为了增加凸块的可靠性，最好是限制或减少从具体C4凸块(如C4凸块112B)到顶部金属层104的最大电流(Imax)。 
图1C说明了图1A结构的一部分。如图1C所示，如果管芯133(图1A-1B)中的电流驱动器(即晶体管)160需要高的电流。由于电流162不能被更多的凸块分流，所以电流162必须通过单个C4凸块112A。 
图1D表示了图8A(如下所述)的厚金属互连结构800的简化形式。在图1D中，电流250可以被更多的凸块分流。来自基底128的电流250可被分流到多个焊料凸块130A、130B，然后再到多个C4凸块112A、112B。电流250接着可通过一个或多个厚金属层218到达与需要高电流的驱动器160耦合的顶部金属层202。这样，电流250可通过多个凸块230A、230B而不是单个凸块112A(图1C)到达需要高电流的驱动器160。结果是，需要从单个凸块230得到的电流可被减小。 
与靠近驱动器160的凸块230相比，位于驱动器160上方并距离顶部金属层202越远的凸块230可贡献更小的电流。凸块230在驱动器160上方距离顶部金属层202越近，其贡献的电流就越大。 
下面描述的是制造可控塌陷芯片连接(C4)凸块和带有一个或多个管芯或晶片级集成厚金属层的互连结构的工艺流程。厚金属互连结构可用于微处理器的后端互连。一个或多个集成厚金属层可改进功率输送并提高热力学能力，比如，减少了低K ILD(层间电介质)以及 管芯/封装界面(图1A中的焊料凸块130和C4凸块112)上的机械应力。 
另外，高阻抗通道或高阻抗C4凸块可用于厚金属互连结构100以此提供更好的电流分流(比如改进均匀的功率分配)并减少最大凸块电流(Imax)。 
图2-8B说明了制造凸块230和互连结构800的不同阶段，该制作过程可用于图1A的结构150。图9A和9B给出了制造图2-8B的结构的两个示例过程。 
在图2中，顶部金属层202可由铜制成，并且在一个实施例中，其厚度可以是大约1微米。顶部金属层202可包括层间电介质(ILD)。ILD可以是传统的二氧化硅或低K(比如介电常数小于3)材料，如含碳氧化物或低K有机材料。具有低介电常数的材料可用于减少信号延迟时间。 
在900处(图9A)，钝化层204(比如氮化物)可在顶部金属层202上被沉积成。钝化层204大约为2,400埃厚。当聚酰亚胺的图案形成完成后，位于金属层202上的钝化层204部分可被除去以此形成通道209。 
聚酰亚胺层206可在钝化层204上被形成并且在902处(图9A)被图案化以及在904处形成通道209。聚酰亚胺层206可包含聚合体类型的材料并且其厚度约为3至5微米。代替聚酰亚胺，可用其他的比如环氧树脂或BCB(苯并环丁烷)材料形成层206. 
图3说明了带有在906处、于被图案化并被形成的聚酰亚胺层206上被沉积成的第一球状受限的金属化或基层金属化(BLM)层208的图2的结构。第一BLM层208可在/沿着通道209的侧壁被沉积成。第一BLM层208可包括薄(比如1000埃)钛(Ti)层，它可起到两个作用：充当随后的金属层212(比如铜)的扩散阻挡层以及为金属晶种(seed)层(比如铜)提供支持。第一BLM层208还可包括喷涂金属晶种层(比如2000-埃的铜晶种层)。在图4中，晶种层使随后的金属层212(比 如铜)被电镀。用于BLM层的材料可随金属层的选择而改变。 
在908处，图3中的光刻胶层210可被涂在第一BLM层208上并且在910处为了图4中的第一厚金属层212而被图案化。 
图4说明了带有在912处、于第一BLM层208上被电镀覆的第一厚金属层212的图3的结构。第一厚金属层212可以是铜(Cu)并且可具有预定的厚度，比如1到100微米(μm)，最好是10-50μm。第一厚金属层212可在第一BLM层208上通道209内被沉积。图3的光刻胶层210可在914处被除去。 
图5说明了带有在916处、被深腐蚀至聚酰亚胺206顶部的第一BLM层208的图4的结构。″灰烬″是去除光刻胶的等离子处理过程。在918A处，第一厚电介质层214可在第一厚金属层212上被沉积成。厚电介质层214可以是层间电介质(ILD)。厚电介质层的厚度可随厚金属层的厚度变化而变化。例如，假如第一金属层为40-50微米厚，那么第一厚电介质层214约为60微米厚。第一厚电介质层214可以是聚酰亚胺，环氧树脂，BCB(苯并环丁烷)或其他自旋式聚合体或自旋式玻璃乃至氧化硅。同样，第一电介质层214可以由用于图9A和11A的工艺流程的、一种自平面化，光可确定的聚合体制成。 
图6说明了带有在920和922处、通过光被图案化并形成通道222的第一电介质层214的图5的结构。在上述图9A中的操作906-922可以在924-940处被重复以此形成第二BLM层216、第二厚金属层218和带有被图案化的通道222的第二厚电介质层220。 
第二厚金属层218可以是铜的并且其厚度为10到50微米。如下面参考图8B所描述的，第二厚金属层218可以与第一厚金属层相互垂直。图6中的第一厚金属层212可以和第二厚金属层218电接触。例如，如果第二厚金属层为40-50微米厚，则第二厚电介质层220可以约为60微米厚。第二厚电介质层220可以为聚酰亚胺，环氧树脂，BCB(苯并环丁烷)或其他自旋式聚合体或自旋式玻璃甚至氧化硅。同样，第二厚电介质层220可以由用于图9A和11A的工艺过程的、 一种自平面化，光可确定的聚合体制成。 
图7说明了带有在942处、于第二电介质层220上及通道222内被沉积成的第三BLM层226的图6的结构。在944处，光刻胶层224可被涂在第三BLM层226上并且在946处为了随后形成的凸块230A、230B而被图案化。 
图8A说明了带有在948处、被镀覆在图7的通道222内以此形成凸块230A-230B的金属(如铜或石墨-锡(铅-锡)化合物)的图7的结构。镀覆层可以是电镀覆层。图7中的光刻胶层224可以在950处被除去。如图8A所示，第三BLM层226在952处可被深度蚀刻掉。 
如果凸块230A-230B由石墨-锡(Pb-Sn)化合物制成，第三BLM层226包含第一钛层(比如1,000埃)、铝层(比如10,000埃)、第二钛层(比如1,000埃)和镍层(比如4,000埃)。 
图8B给出的是图8A的互连结构800的俯视图。图8B中的第二厚金属层218可以与第一厚金属层212相互垂直。第二厚金属层218可以和至少两个凸块230B、230D电接触。 
图14(如下所述)列举了通过凸块230A-230D的最大电流值的例子。由于图8A和8B中的凸块230A、230B与厚金属层212、218耦合，因此通过图8A和8B中每一个凸块230A、230B的最大电流可以比通过图1B中每一个凸块112A、112B的最大电流要低。图1B中的凸块112A、112B未与厚金属层耦合。图1B中每一个凸块112必须将必需的满载电流(如680mA)输送到顶部金属层104。 
一个可选用的实施例可具有一个厚金属层而不是两个厚金属层212、218。单个厚金属层可以与一排C4凸块230耦合。在与图8A中的结构800相同的水平面上可以有多个厚金属层，每一个厚金属层可以与一排C4凸块230耦合。 
图9B说明了制造图8A的互连结构800的一个可选用的过程。图9B中的操作900-916与图9A中的操作900-916相似。在图9B的918B处，一种非光可确定的，自平面化的聚合体可作为第一电介质层(比 如，层间电介质(ILD))在图4中的第一厚金属层212上被沉积成。在图9B的954处，光刻胶层可被涂在电介质层上。在956处，在光刻胶内可把通道图案化。在958处，第一电介质层可被干刻。在960处，光刻胶层可被除去。 
图9B中的操作924-934可以与图9A中的操作924-934相似。在图9B中的962处，一种非光可确定的，自平面化的聚合体可作为第二电介质层(比如层间电介质(ILD))在第二厚金属层上被沉积成，这个第二厚金属层与图6的第二厚金属层216相似。在964处，光刻胶层可被涂在第二电介质层上。在966处，在光刻胶层内可把通道图案化。在968处，第二电介质层可被干刻。在970处，光刻胶层可被除去。图9B中的操作942-952可以与图9A中的操作942-952相似。图9B的过程可以如图9A的过程制造出基本相同的结构800(图8A)。 
图10说明了互连结构1000的一个可选用的实施例，该互连结构1000与图8A中的互连结构800相似，但是具有附加的扩散阻挡层1002、1004。扩散阻挡层1002、1004用于防止金属层212、218(比如铜)扩散进电介质层214、220。扩散阻挡层1002、1004可通过在金属层212、218上及两侧的无电镀(EL)钴镀覆而形成，这个过程在下面将参考图11A、11B和12来描述。 
图11A给出的是制造图10中的互连结构1000的工艺流程的一个例子。图11A中的操作900-952可以与图9A中的操作900-952相似。扩散阻挡层1002、1004(图10)可以在图11A中的1100和1102处被无电镀(EL)镀覆。 
图11B给出的是制造图10中的互连结构1000的一个可选用的工艺流程。图11B中的操作900-952可以与图9B中的操作900-952相似。 
扩散阻挡层1002、1004(图10)可以在图11B中的1100和1102处被无电镀(EL)镀覆。 
图12给出的是制造如图13F所示的互连结构1350的工艺流程。 
图13A-13F给出的是按照图12的工艺流程的互连结构1350的不同阶段。图13F中的互连结构1350可具有与图10的互连结构1000中的扩散阻挡层1002、1004类似的铜扩散阻挡层。 
图13A中的第一钝化层1300(比如氮化物)可在图12中的900处、于顶部金属层202上被沉积成。第一厚电介质层1302(比如ILD)可在图12中的1200处、于第一钝化层1300上被沉积成。第一厚电介质层的厚度取决于厚金属层的厚度。例如，第一厚电介质层1302大约为60微米厚。 
单个或双重波纹镶嵌工艺的应用取决于厚金属的厚度。图13B给出的是双重波纹镶嵌工艺。在1202处，第一光刻胶层可被涂在第一厚电介质层1302上。在1204处，在图13B的第一厚电介质层1302内可把通道1304图案化。接着，第一光刻胶层被除去。在1206处，第二光刻胶层被涂在第一厚电介质层1302上。在1208处，第二光刻胶层可使沟槽1306(图13B)图案化。然后，第二光刻胶层被除去。 
在1210处，图13C中的第一BLM层1308(即阻挡晶种层)可在通道1304和沟槽1306内被沉积成。在1212处，第一厚金属层1310(比如铜)可被镀覆在第一BLM层1308上、通道1304和沟槽1306内。 
在1214处，图13D中的第一厚金属层1310可以通过比如化学机械抛光(CMP)而被抛光。 
图12中的操作1216-1232可以与上述图12中的操作900-1214相似。操作1216-1232可以形成图13E中的第二钝化层1311(比如氮化物)、第二电介质层1312、第二BLM层1314和第二厚金属层1316。 
在1234处，图13F中的第三钝化层1318(比如氮化物)可以在第二厚金属层1316上形成。在1236处，聚酰亚胺层1320可被图案化并在第三钝化层1318上被形成。在1238处，第三BLM层1322可以在聚酰亚胺层1320上被沉积成。在1240处，另一层光刻胶可被涂在第三BLM层1322上。在1242和1244处，凸块1324可以被图案化并且在光刻胶余下的空间内被镀覆。 
在1246处，凸块1324周围的光刻胶层可被除去。接着，在1248处，第三BLM层1322可被蚀刻。 
图14是与图1B中的标准互连结构100的最大电流和电压降相比较的、图8A中的互连结构800(带有两个厚金属层212、218)的模拟参数和模拟结果表。图1中的不带厚金属层的标准互连结构100在图14中由行1310代表。图1B中的标准互连结构100可具有比如通过凸块112的680mA的最大电流(Imax)以及从凸块112至顶部金属层104的29mV的电压降(V＝IR)。 
图14中的模拟参数包括图8A和10中的两个厚金属层212、218的(a)厚度和(b)宽度、以及在凸块230和第二厚金属层218之间的通道222(图7-8A)的(c)阻抗。图14给出了1400-1406的四组参数和结果。因为驱动器(即顶部金属层202下的晶体管)所需要的电流可以从多个凸块230及两个厚金属层212、218(图8A)获得，所以1400-1406四组值中每个凸块可具有比标准互连结构100(图14中由行1410表示)更低的最大电流。因此，厚金属层212、218可减小最大电流并改进功率传输。 
第三组1404比第一组1400具有更高的通道阻抗(70欧姆)。第三组1404比第一组1400具有更低的最大电流(370mA)和更高的电压降(49mV)。 
通过多个相近凸块230的电流的更均匀分配可以将每个凸块上的最大电流(Imax)减少到原来的46％。借助于厚金属层集成流程，根据金属厚度，Imax可以改进约22到35％。越厚的金属可以提供更好的Imax。增加通道222(图8A)的阻抗可使Imax改进46％。 
为了增加通道阻抗，可将图8A中凸块230和第二厚金属层218之间的通道222作得更小。如果面积减小，则阻抗会增加。可选择地或另外地，可增加第二BLM层的厚度。同样地，通道222或凸块本身可以使用具有比铜(Cu)更高阻抗的材料(比如钨(W))被沉积成。 
图15A说明了图1B和图8A的结构中C4通道阻抗和C4最大电 流(Imax)之间的关系。当C4通道阻抗增加时，C4最大电流(Imax)减小。 
图15B说明了图1B和图8A的结构中C4阻抗和电压降(V＝IR，单位为毫伏)之间的关系。当C4阻抗增加时，通道的电压降(V＝IR)增大。 
如上所述，一层或更多的集成厚金属层(比如，图8A中的212、218)可以改进热力学能力，即减小低k ILD内以及管芯/封装界面处(比如，图1A中的焊料凸块130和C4凸块112)的机械应力。 
图16比较了(a)图1B中的标准互连结构100和(b)图8A中所建议的带有两个厚金属层212、218的结构800对低k(介电常数)ILD层的应力影响。比如，图8A中带有两个45-微米的厚金属层212、218的凸块结构800对低k层(比如含碳氧化物(CDO))的应力要比图1B中的标准互连结构100减小50％。 
自旋式层间电介质(ILD) 
目前，制造过程中的大部分层间电介质(ILD)涂敷工艺为″自旋式″工艺。图17说明了使用“自旋式”涂敷工艺在具有大纵横比外形结构1702的表面1700涂上厚ILD层的工具1704。当固定位置的工具1704在结构1702周围和其上涂ILD材料时，图17中的表面1700是旋转的或自旋的。 
在上面参考图2-11B所描述的晶片级、厚金属集成的工艺流程期间，可使用″自旋式″工具1704。比如，图5中的第一厚电介质层214可被自旋地喷涂在大纵横比外形表面(即第一厚金属层212上及周围)。作为另外一例，图6中的第二厚电介质层220可被自旋地喷涂在另一个大纵横比外形表面(即第二厚金属层218上及周围)。这里描述的″厚″金属层和″厚″电介质层指图5和6中的层的高度。 
图18A说明了在表面1800上被图案化的厚(大纵横比)金属层结构1802(比如45微米厚)。图18B说明了在厚金属层结构1802周围和其上形成的厚ILD层1804。 
在大纵横比外形表面，特别是带有行结构的大纵横比外形表面(比如图6中的第二厚金属层218)自旋地喷涂上厚(比如45-微米)ILD层之后，要形成一个平面的或基本平坦的上表面是困难的。 
喷涂ILD 
喷涂已被用于比如建筑或机械应用中的油或润滑剂，并且还用作抗腐蚀涂层的金属喷涂。在半导体行业中，喷涂被用来处理抗蚀剂以此提供均匀的涂层。 
喷涂可被用于永久的厚层间电介质(ILD)涂层。在晶片级厚金属集成的工艺流程(如上所述)期间，喷涂可用来在大纵横比外形表面(比如，图6中的厚金属层212、218周围和其上)形成一层厚ILD层。 
图19说明了在带有大纵横比外形结构1904的表面1902(比如，图6中第二厚金属层218)喷涂厚ILD层的喷涂工具1900。当喷涂工具1900将电介质材料喷涂到结构1904周围和其上的表面1902时，工具1900可以在各个方向(如箭头所示)上移动。喷涂工具1900可以从亚利桑那州菲尼克斯市的EV集团(EVG)公司获得。由EV集团公司制造的喷涂工具可被修改或更改以此制造上述的电介质层。微处理器可以控制喷涂工具的移动。 
喷涂可提供优质的平面，即图18B中给出的基本平坦或平面的上表面。 
层压 
层压已被用于装配区(比如，粘合层)内的装配过程，并且还被用于干式抗蚀剂涂层以此涂上厚抗蚀剂。 
层压还可提供优质的平面化结构。层压可被用于永久的厚ILD涂敷。在晶片级厚金属集成的工艺流程(如上所述)期间，层压可被用于在大纵横比外形表面(比如，厚金属层212、218周围和其上)形成厚ILD层。 
图20说明了在具有大纵横比外形结构2004的表面2002(比如，图6中的第二厚金属层218)喷涂厚ILD层的层压方法。层压材料2006 可以从日本东京LINTEC公司获得。层压材料2006可以在具有大纵横比外形结构2004的表面2002被展开和按压。 
喷涂和层压可以使厚ILD涂层能够在大纵横比的金属外形表面具有想要的平面。 
许多实施例已经被描述过。然而，应当理解：在没有脱离此申请的精神与范围内，可以做各种的修改。因此，其他的实施例属于后面权利要求的范围内。 

Claims (51)

1.一种集成电路装置，包含：
第一凸块和第二凸块；
第一后端互连金属层，与集成电路管芯的顶部金属层耦合，所述第一后端互连金属层在被第一电介质层包围的空间内形成，所述第一电介质层具有基本平坦的上表面；
在所述第一后端互连金属层上的第二后端互连金属层，所述第二后端互连金属层与所述第一凸块、所述第二凸块、以及所述第一后端互连金属层耦合，所述第一后端互连金属层和所述第二后端互连金属层可起到将电流从所述第一凸块和所述第二凸块传递到所述集成电路管芯的所述顶部金属层的作用。
2.如权利要求1所述的装置，其中所述第一电介质层包含自平面化、光可确定的聚合体。
3.如权利要求1所述的装置，其中所述第一电介质层包含自平面化、非光可确定的聚合体。
4.如权利要求1所述的装置，其中所述第一电介质层是被喷涂上的。
5.如权利要求1所述的装置，其中所述第一电介质层是被层压上的。
6.如权利要求1所述的装置，其中所述第一后端互连金属层为10到50微米厚。
7.如权利要求1所述的装置，其中所述第一后端互连金属层包含电镀铜。
8.如权利要求1所述的装置，其中所述第一后端互连金属层沉积在第一基层金属化上的通道内，所述第一基层金属化沉积在所述集成电路管芯的所述顶部金属层上。
9.如权利要求1所述的装置，其中所述第二后端互连金属层与所述第一后端互连金属层相互垂直。
10.如权利要求1所述的装置，其中：所述第一后端互连金属层为1至100微米厚；以及所述第二后端互连金属层为10至50微米厚。
11.一种形成集成电路的方法，包含：
形成第一基层金属化上的第一后端互连金属层，所述第一基层金属化与集成电路管芯的顶部金属层相接触；
形成所述第一后端互连金属层上的第一基本平坦电介质层；
形成通过第一电介质层的通道；
在所述第一电介质层的通道中形成第二基层金属化；
在第二基层金属化上形成第二后端互连金属层，所述第二后端互连金属层利用通过所述第一电介质层的通道耦合到所述第一后端互连金属层；以及
在所述第二后端互连金属层上形成凸块；
其中所述第二后端互连金属层与所述第一后端互连金属层耦合，从而起到将电流从所述凸块传递到所述集成电路管芯的所述顶部金属层的作用。
12.如权利要求11所述的方法，其中形成第一基本平坦电介质层包含喷涂电介质材料。
13.如权利要求11所述的方法，其中形成第一基本平坦电介质层包含滚动和按压层压材料。
14.如权利要求11所述的方法，其中形成所述第一后端互连金属层包含形成厚度为10到50微米的后端互连金属层。
15.如权利要求11所述的方法，其中形成所述第一基层金属化上的所述第一后端互连金属层包含将铜电镀到所述第一基层金属化上。
16.如权利要求11所述的方法，其中所述形成第一电介质层使用了自平面化、光可确定的聚合体。
17.如权利要求11所述的方法，其中所述形成第一电介质层使用了自平面化、非光可确定的聚合体。
18.如权利要求11所述的方法，其中所述第二后端互连金属层与所述第一后端互连金属层相互垂直。
19.如权利要求11所述的方法，其中：形成所述第一后端互连金属层包含形成1至100微米厚的金属层；以及形成所述第二后端互连金属层包含形成10至50微米厚的金属层。
20.一种形成集成电路的方法，包含：
形成第一表面上的第一金属结构，所述第一金属结构具有高于所述第一表面超过40微米的高度，所述第一金属结构与所述第一表面下的集成电路管芯的顶部金属层相接触；
形成所述第一金属结构周围和其上的基本平坦的第一电介质层；
形成通过所述第一电介质层到所述第一金属结构的通道；
在第二表面上形成第二金属结构，所述第二金属结构具有高于所述第二表面超过40微米的高度，所述第二金属结构与通过所述第一电介质层到所述第一金属结构的通道相接触；
在所述第二金属结构周围和其上形成基本平坦的第二电介质层。
21.如权利要求20所述的方法，其中形成所述基本平坦的第一电介质层包含在所述第一金属结构周围和其上喷涂电介质材料。
22.如权利要求20所述的方法，其中形成所述基本平坦的第一电介质层包含移动喷涂器以便在所述第一金属结构周围和其上喷涂电介质材料。
23.如权利要求20所述的方法，其中形成所述基本平坦的第一电介质层包含滚动和按压在所述第一金属结构周围和其上的叠片材料。
24.如权利要求20所述的方法，其中：形成第一后端互连金属层包含形成1至100微米厚的金属层；以及形成第二后端互连金属层包含形成10至50微米厚的金属层。
25.一种集成电路装置，包含：
第一凸块和第二凸块；
第一后端互连金属层，与所述第一凸块和所述第二凸块耦合，所述第一后端互连金属层在第一电介质层的沟槽内形成；
第二后端互连金属层，与所述第一后端互连金属层耦合，所述第二后端互连金属层在第二电介质层的沟槽内形成，所述第二后端互连金属层与集成电路管芯的顶部金属层耦合，所述第一后端互连金属层和所述第二后端互连金属层适于将电流从所述第一凸块和所述第二凸块传递到所述集成电路管芯的所述顶部金属层。
26.如权利要求25所述的装置，其中所述第一和第二凸块是可控塌陷芯片连接凸块。
27.如权利要求25所述的装置，其中所述第一和第二凸块与基底的第一和第二焊料凸块耦合。
28.如权利要求25所述的装置，其中所述第一后端互连金属层为10到50微米厚。
29.如权利要求25所述的装置，其中所述第一后端互连金属层包含电镀铜。
30.如权利要求25所述的装置，其中所述第一后端互连金属层沉积在第一基层金属化上的通道内，所述第一基层金属化沉积在所述集成电路管芯的所述顶部金属层上。
31.如权利要求25所述的装置，其中所述第一电介质层包围所述第一后端互连金属层。
32.如权利要求31所述的装置，其中所述第一电介质层包含自平面化、光可确定的聚合体。
33.如权利要求31所述的装置，其中所述第一电介质层包含自平面化、非光可确定的聚合体。
34.如权利要求25所述的装置，还包含在所述第一后端互连金属层上和两侧的扩散阻挡层。
35.如权利要求25所述的装置，其中：所述第一后端互连金属层为1至100微米厚；以及所述第二后端互连金属层为10至50微米厚。
36.一种形成集成电路的方法，包含：
形成第一基层金属化上的第一后端互连金属层，所述第一基层金属化与集成电路管芯的顶部金属层相接触；
形成所述第一后端互连金属层上的第一电介质层；
形成所述第一电介质层内的通道；
形成所述第一电介质层的所述通道内的第二基层金属化；
形成第二基层金属化上的第二后端互连金属层；
形成所述第二后端互连金属层上的第二电介质层；以及
形成所述第二电介质层上的凸块，所述第二后端互连金属层与所述第一后端互连金属层耦合，从而适于将电流从所述凸块传递到所述集成电路管芯的所述顶部金属层。
37.如权利要求36所述的方法，其中所述第一和第二凸块是可控塌陷芯片连接凸块。
38.如权利要求36所述的方法，其中所述第一后端互连金属层为10到50微米厚。
39.如权利要求36所述的方法，其中形成所述第一基层金属化上的所述第一后端互连金属层包含将铜电镀到所述第一基层金属化。
40.如权利要求36所述的方法，还包含所述凸块与基底的焊料凸块相连。
41.如权利要求36所述的方法，还包含在聚酰亚胺层的通道内形成所述第一基层金属化。
42.如权利要求36所述的方法，还包含在苯并环丁烯层的通道内形成所述第一基层金属化。
43.如权利要求36所述的方法，还包含在环氧树脂层的通道内形成所述第一基层金属化。
44.如权利要求36所述的方法，其中所述形成第一电介质层使用了自平面化、光可确定的聚合体。
45.如权利要求36所述的方法，其中所述形成第一电介质层使用了自平面化、非光可确定的聚合体。
46.如权利要求36所述的方法，其中所述第二后端互连金属层与所述第一后端互连金属层相互垂直。
47.如权利要求36所述的方法，还包含在所述第一后端互连金属层上及两侧形成扩散阻挡层。
48.如权利要求36所述的方法，其中：形成所述第一后端互连金属层包含形成1至100微米厚的金属层；以及形成所述第二后端互连金属层包含形成10至50微厚的金属层。
49.一种形成集成电路的方法，包含：
形成在第一阻挡晶种层上的第一后端互连金属层，所述第一阻挡晶种层与集成电路管芯的顶部金属层相接触；
形成所述第一后端互连金属层上的第一钝化层；
形成所述第一钝化层上的第一聚酰亚胺层；
形成所述第一聚酰亚胺层内的通道；
形成所述通道内的第二阻挡晶种层；
形成在第二阻挡晶种层上的第二后端互连金属层，所述第二阻挡晶种层与所述第一后端互连金属层相接触；
形成所述第二后端互连金属层上的第二钝化层；
形成所述第二钝化层上的第二聚酰亚胺层；
形成所述第二聚酰亚胺层内的通道；
形成所述通道内的第三阻挡晶种层；以及
形成所述第三阻挡晶种层上的第一和第二凸块。
50.如权利要求49所述的方法，其中所述第一后端互连金属层为10-50微米厚。
51.如权利要求49所述的方法，其中：形成所述第一后端互连金属层包含形成1至100微米厚的金属层；以及形成所述第二后端互连金属层包含形成10至50微厚的金属层。
CN200480025653XA 2003-09-09 2004-09-03 喷涂或层压处理厚ild层的方法及装置 Expired - Fee Related CN1846307B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US10/659,044 2003-09-09
US10/659,044 US6977435B2 (en) 2003-09-09 2003-09-09 Thick metal layer integrated process flow to improve power delivery and mechanical buffering
US10/745,059 2003-12-22
US10/745,059 US6943440B2 (en) 2003-09-09 2003-12-22 Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow
PCT/US2004/028949 WO2005024912A2 (en) 2003-09-09 2004-09-03 Methods of processing thick ild layers using spray coating or lamination for c4 wafer level thick metal integrated flow

Publications (2)

Publication Number Publication Date
CN1846307A CN1846307A (zh) 2006-10-11
CN1846307B true CN1846307B (zh) 2011-05-18

Family

ID=34226907

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200480025653XA Expired - Fee Related CN1846307B (zh) 2003-09-09 2004-09-03 喷涂或层压处理厚ild层的方法及装置

Country Status (4)

Country Link
US (3) US6977435B2 (zh)
CN (1) CN1846307B (zh)
DE (1) DE112004001654T5 (zh)
TW (1) TWI299510B (zh)

Families Citing this family (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6551857B2 (en) 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
US6642136B1 (en) 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US8021976B2 (en) 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US7405149B1 (en) 1998-12-21 2008-07-29 Megica Corporation Post passivation method for semiconductor chip or wafer
US7381642B2 (en) * 2004-09-23 2008-06-03 Megica Corporation Top layers of metal for integrated circuits
US6936531B2 (en) 1998-12-21 2005-08-30 Megic Corporation Process of fabricating a chip structure
US6965165B2 (en) * 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US6495442B1 (en) * 2000-10-18 2002-12-17 Magic Corporation Post passivation interconnection schemes on top of the IC chips
US7247932B1 (en) 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
US7271489B2 (en) 2003-10-15 2007-09-18 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US6815324B2 (en) 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
TWI313507B (en) 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US6818545B2 (en) 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US7902679B2 (en) 2001-03-05 2011-03-08 Megica Corporation Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
US7099293B2 (en) 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
US6613606B1 (en) 2001-09-17 2003-09-02 Magic Corporation Structure of high performance combo chip and processing method
US7932603B2 (en) 2001-12-13 2011-04-26 Megica Corporation Chip structure and process for forming the same
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
TW503496B (en) 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
TW544882B (en) * 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
US6673698B1 (en) 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
WO2004015764A2 (en) * 2002-08-08 2004-02-19 Leedy Glenn J Vertical system integration
WO2005024912A2 (en) * 2003-09-09 2005-03-17 Intel Corporation Methods of processing thick ild layers using spray coating or lamination for c4 wafer level thick metal integrated flow
US6977435B2 (en) * 2003-09-09 2005-12-20 Intel Corporation Thick metal layer integrated process flow to improve power delivery and mechanical buffering
US7459790B2 (en) 2003-10-15 2008-12-02 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US7394161B2 (en) * 2003-12-08 2008-07-01 Megica Corporation Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
US8022544B2 (en) 2004-07-09 2011-09-20 Megica Corporation Chip structure
US7465654B2 (en) * 2004-07-09 2008-12-16 Megica Corporation Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
US7452803B2 (en) 2004-08-12 2008-11-18 Megica Corporation Method for fabricating chip structure
US8008775B2 (en) * 2004-09-09 2011-08-30 Megica Corporation Post passivation interconnection structures
US7355282B2 (en) * 2004-09-09 2008-04-08 Megica Corporation Post passivation interconnection process and structures
US7521805B2 (en) * 2004-10-12 2009-04-21 Megica Corp. Post passivation interconnection schemes on top of the IC chips
US7547969B2 (en) 2004-10-29 2009-06-16 Megica Corporation Semiconductor chip with passivation layer comprising metal interconnect and contact pads
US20060102957A1 (en) * 2004-11-12 2006-05-18 Jhon-Jhy Liaw SER immune cell structure
KR100661220B1 (ko) * 2004-12-29 2006-12-22 동부일렉트로닉스 주식회사 듀얼 절연막을 이용한 금속 배선 형성 방법
US8294279B2 (en) 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
US7470927B2 (en) * 2005-05-18 2008-12-30 Megica Corporation Semiconductor chip with coil element over passivation layer
JP4449824B2 (ja) * 2005-06-01 2010-04-14 カシオ計算機株式会社 半導体装置およびその実装構造
US7582556B2 (en) * 2005-06-24 2009-09-01 Megica Corporation Circuitry component and method for forming the same
CN1901163B (zh) 2005-07-22 2011-04-13 米辑电子股份有限公司 连续电镀制作线路组件的方法及线路组件结构
US7335536B2 (en) 2005-09-01 2008-02-26 Texas Instruments Incorporated Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices
US7473999B2 (en) * 2005-09-23 2009-01-06 Megica Corporation Semiconductor chip and process for forming the same
US7397121B2 (en) 2005-10-28 2008-07-08 Megica Corporation Semiconductor chip with post-passivation scheme formed over passivation layer
US7410884B2 (en) * 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
TWI339419B (en) * 2005-12-05 2011-03-21 Megica Corp Semiconductor chip
US8836146B2 (en) * 2006-03-02 2014-09-16 Qualcomm Incorporated Chip package and method for fabricating the same
US20070241665A1 (en) * 2006-04-12 2007-10-18 Matsushita Electric Industrial Co., Ltd. Organic electroluminescent element, and manufacturing method thereof, as well as display device and exposure apparatus using the same
US20070259523A1 (en) * 2006-05-04 2007-11-08 Yechuri Sitaramarao S Method of fabricating high speed integrated circuits
US8420520B2 (en) * 2006-05-18 2013-04-16 Megica Corporation Non-cyanide gold electroplating for fine-line gold traces and gold pads
US8022552B2 (en) 2006-06-27 2011-09-20 Megica Corporation Integrated circuit and method for fabricating the same
US8421227B2 (en) * 2006-06-28 2013-04-16 Megica Corporation Semiconductor chip structure
US20080002365A1 (en) * 2006-06-29 2008-01-03 Ashish Gupta Socket enabled cooling of in-substrate voltage regulator
CN100459081C (zh) * 2006-07-10 2009-02-04 中芯国际集成电路制造(上海)有限公司 焊料凸块的制造方法
TWI336913B (en) * 2006-07-18 2011-02-01 Via Tech Inc A chip and manufacturing method and application thereof
US7498252B2 (en) * 2006-09-29 2009-03-03 Intel Corporation Dual layer dielectric stack for microelectronics having thick metal lines
TWI370515B (en) * 2006-09-29 2012-08-11 Megica Corp Circuit component
US8143173B2 (en) * 2006-11-22 2012-03-27 Seiko Epson Corporation Method for manufacturing semiconductor device
JP4731456B2 (ja) * 2006-12-19 2011-07-27 富士通セミコンダクター株式会社 半導体装置
US20080160752A1 (en) * 2007-01-03 2008-07-03 International Business Machines Corporation Method for chip to package interconnect
US7485564B2 (en) * 2007-02-12 2009-02-03 International Business Machines Corporation Undercut-free BLM process for Pb-free and Pb-reduced C4
US8193636B2 (en) 2007-03-13 2012-06-05 Megica Corporation Chip assembly with interconnection by metal bump
TWI368286B (en) 2007-08-27 2012-07-11 Megica Corp Chip assembly
US7964965B2 (en) * 2008-03-31 2011-06-21 Intel Corporation Forming thick metal interconnect structures for integrated circuits
US7833899B2 (en) * 2008-06-20 2010-11-16 Intel Corporation Multi-layer thick metallization structure for a microelectronic device, intergrated circuit containing same, and method of manufacturing an integrated circuit containing same
US8293634B2 (en) * 2008-08-07 2012-10-23 International Business Machines Corporation Structures and methods for improving solder bump connections in semiconductor devices
JP5284194B2 (ja) * 2008-08-07 2013-09-11 キヤノン株式会社 プリント配線板およびプリント回路板
US7705447B2 (en) * 2008-09-29 2010-04-27 Intel Corporation Input/output package architectures, and methods of using same
US8309396B2 (en) * 2009-01-26 2012-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for 3D integrated circuit stacking
US8299611B2 (en) * 2009-04-08 2012-10-30 International Business Machines Corporation Ball-limiting-metallurgy layers in solder ball structures
DE102009035437B4 (de) * 2009-07-31 2012-09-27 Globalfoundries Dresden Module One Llc & Co. Kg Halbleiterbauelement mit einem Verspannungspuffermaterial, das über einem Metallisierungssystem mit kleinem ε gebildet ist
US20120009409A1 (en) * 2010-07-08 2012-01-12 Jones William F Method for applying a layer of material to the surface of a non-metallic substrate
KR101649055B1 (ko) 2011-09-30 2016-08-17 인텔 코포레이션 실리콘 관통 비아 프로세싱 동안 장치 웨이퍼를 처리하기 위한 구조체 및 방법, 및 3ｄ 패키징 구조체
US8933715B2 (en) 2012-04-08 2015-01-13 Elm Technology Corporation Configurable vertical integration
EP3178162A4 (en) 2014-08-07 2018-04-04 Intel Corporation Method and apparatus for forming backside die planar devices and saw filter
US10043740B2 (en) * 2016-07-12 2018-08-07 Intel Coporation Package with passivated interconnects
EP3898070A1 (en) * 2018-12-17 2021-10-27 Heraeus Precious Metals North America Conshohocken LLC Process for forming an electric heater
US11063146B2 (en) 2019-01-10 2021-07-13 Texas Instruments Incorporated Back-to-back power field-effect transistors with associated current sensors
CN111117443A (zh) * 2019-11-12 2020-05-08 新疆烯金石墨烯科技有限公司 用于铝电解电容器的石墨烯散热涂料、石墨烯散热材料及其制备方法
GB2591755A (en) * 2020-02-05 2021-08-11 Dar Yun Energy Science Tech Co Ltd Power-supplying battery of electric vehicle
US20210375816A1 (en) * 2020-06-02 2021-12-02 Texas Instruments Incorporated Ic device with chip to package interconnects from a copper metal interconnect level

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5300461A (en) * 1993-01-25 1994-04-05 Intel Corporation Process for fabricating sealed semiconductor chip using silicon nitride passivation film
US5892273A (en) * 1994-10-03 1999-04-06 Kabushiki Kaisha Toshiba Semiconductor package integral with semiconductor chip
AU6376796A (en) * 1995-03-20 1996-10-16 Mcnc Solder bump fabrication methods and structure including a ti tanium barrier layer
US5950102A (en) * 1997-02-03 1999-09-07 Industrial Technology Research Institute Method for fabricating air-insulated multilevel metal interconnections for integrated circuits
JPH10228110A (ja) 1997-02-17 1998-08-25 Hitachi Chem Co Ltd ポジ型感光性樹脂組成物、これを用いたレリーフパターンの製造法及びポリイミドパターンの製造法
US6330967B1 (en) * 1997-03-13 2001-12-18 International Business Machines Corporation Process to produce a high temperature interconnection
US6316288B1 (en) * 1997-03-21 2001-11-13 Seiko Epson Corporation Semiconductor device and methods of manufacturing film camera tape
US6117299A (en) * 1997-05-09 2000-09-12 Mcnc Methods of electroplating solder bumps of uniform height on integrated circuit substrates
JPH1174413A (ja) * 1997-07-01 1999-03-16 Sony Corp リードフレームとリードフレームの製造方法と半導体装置と半導体装置の組立方法と電子機器
US6255675B1 (en) * 1998-07-10 2001-07-03 Xilinx, Inc. Programmable capacitor for an integrated circuit
JP2000114370A (ja) * 1998-10-06 2000-04-21 Oki Electric Ind Co Ltd 半導体装置
US7405149B1 (en) * 1998-12-21 2008-07-29 Megica Corporation Post passivation method for semiconductor chip or wafer
SG93278A1 (en) 1998-12-21 2002-12-17 Mou Shiung Lin Top layers of metal for high performance ics
US6140155A (en) * 1998-12-24 2000-10-31 Casio Computer Co., Ltd. Method of manufacturing semiconductor device using dry photoresist film
JP2000216184A (ja) * 1999-01-25 2000-08-04 Sanyo Electric Co Ltd 半導体装置およびその製造方法
US20020000665A1 (en) * 1999-04-05 2002-01-03 Alexander L. Barr Semiconductor device conductive bump and interconnect barrier
US6341418B1 (en) * 1999-04-29 2002-01-29 International Business Machines Corporation Method for direct chip attach by solder bumps and an underfill layer
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6559388B1 (en) * 1999-06-08 2003-05-06 International Business Machines Corporation Strain relief for substrates having a low coefficient of thermal expansion
US6230400B1 (en) * 1999-09-17 2001-05-15 George Tzanavaras Method for forming interconnects
JP2001144204A (ja) * 1999-11-16 2001-05-25 Nec Corp 半導体装置及びその製造方法
US6406994B1 (en) * 1999-12-03 2002-06-18 Chartered Semiconductor Manufacturing Ltd. Triple-layered low dielectric constant dielectric dual damascene approach
US6426545B1 (en) * 2000-02-10 2002-07-30 Epic Technologies, Inc. Integrated circuit structures and methods employing a low modulus high elongation photodielectric
JP3578964B2 (ja) 2000-03-21 2004-10-20 富士通株式会社 半導体装置及びその製造方法
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6518675B2 (en) * 2000-12-29 2003-02-11 Samsung Electronics Co., Ltd. Wafer level package and method for manufacturing the same
FR2824954A1 (fr) * 2001-05-18 2002-11-22 St Microelectronics Sa Plot de connexion d'un circuit integre
TW536795B (en) * 2001-05-30 2003-06-11 Apack Comm Inc Flip chip package of monolithic microwave integrated circuit
US6798073B2 (en) * 2001-12-13 2004-09-28 Megic Corporation Chip structure and process for forming the same
US6673698B1 (en) * 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
TW503496B (en) * 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
US6908845B2 (en) * 2002-03-28 2005-06-21 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US20030218246A1 (en) * 2002-05-22 2003-11-27 Hirofumi Abe Semiconductor device passing large electric current
JP3574450B1 (ja) * 2003-05-16 2004-10-06 沖電気工業株式会社 半導体装置、及び半導体装置の製造方法
US6977435B2 (en) * 2003-09-09 2005-12-20 Intel Corporation Thick metal layer integrated process flow to improve power delivery and mechanical buffering
WO2005024912A2 (en) * 2003-09-09 2005-03-17 Intel Corporation Methods of processing thick ild layers using spray coating or lamination for c4 wafer level thick metal integrated flow
US6900541B1 (en) * 2004-02-10 2005-05-31 United Microelectronics Corp. Semiconductor chip capable of implementing wire bonding over active circuits

Also Published As

Publication number Publication date
DE112004001654T5 (de) 2013-10-10
US20050051904A1 (en) 2005-03-10
TWI299510B (en) 2008-08-01
TW200523986A (en) 2005-07-16
US6943440B2 (en) 2005-09-13
US20060076678A1 (en) 2006-04-13
CN1846307A (zh) 2006-10-11
US20050051894A1 (en) 2005-03-10
US6977435B2 (en) 2005-12-20

Similar Documents

Publication Publication Date Title
CN1846307B (zh) 喷涂或层压处理厚ild层的方法及装置
US20070190776A1 (en) Methods of Processing Thick ILD Layers Using Spray Coating or Lamination for C4 Wafer Level Thick Metal Integrated Flow
US11315896B2 (en) Conical-shaped or tier-shaped pillar connections
US8344514B2 (en) Semiconductor device structures and electronic devices including same hybrid conductive vias
JP4017173B2 (ja) ボンディング・パッドと高性能銅インダクタの集積化
TWI595535B (zh) 積體電路結構與其形成方法
US7452803B2 (en) Method for fabricating chip structure
US7985653B2 (en) Semiconductor chip with coil element over passivation layer
US6551856B1 (en) Method for forming copper pad redistribution and device formed
KR101570272B1 (ko) 상호접속 구조물 및 이의 제조 방법
US20060234423A1 (en) System for providing a redistribution metal layer in an integrated circuit
CN102832188B (zh) 具有厚聚合物层的焊球保护结构
US9059026B2 (en) 3-D inductor and transformer
US11545450B2 (en) Interlocked redistribution layer interface for flip-chip integrated circuits
CN117393523B (zh) 一种用于贴装的多层布线转接板及其制备方法
US20230260881A1 (en) Semiconductor device and method for making the same
US20230411318A1 (en) Semiconductor Device and Method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110518

Termination date: 20180903

CF01 Termination of patent right due to non-payment of annual fee