CN1881535A - 具有穿透电极的半导体器件及其制造方法 - Google Patents
具有穿透电极的半导体器件及其制造方法 Download PDFInfo
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- CN1881535A CN1881535A CNA200610086505XA CN200610086505A CN1881535A CN 1881535 A CN1881535 A CN 1881535A CN A200610086505X A CNA200610086505X A CN A200610086505XA CN 200610086505 A CN200610086505 A CN 200610086505A CN 1881535 A CN1881535 A CN 1881535A
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- dielectric film
- electrode
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- substrate
- semiconductor substrate
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Abstract
本发明公开一种具有穿透电极的半导体器件的制造方法,该方法包括如下步骤:在基板31中形成穿透孔36,从所述基板的一个表面侧形成第一金属层39,并且在所述基板的一个表面上粘贴保护膜40;在使用所述第一金属层作为供电层的同时,借助于从所述基板的另一表面实施第二金属42的电镀,用所述第二金属填充所述穿透孔以形成穿透电极;除去保护膜40,以及除去位于除所述穿透电极周围部分之外的区域中的第一金属层39。
Description
技术领域
本发明涉及一种具有穿透电极的半导体器件和一种具有该穿透电极的半导体器件的制造方法。举例来说,本发明可以用作三维封装方法,即,在诸如用于接收由聚光透镜所会聚的光线的CCD(电荷耦合器件)、CMOS器件、存储器件等器件、以及诸如摄像模块、多级存储模块等模块部件中,本发明适用于在硅基板中形成穿透电极。
背景技术
随着信息通信技术的迅速进步和发展,近年来可以实现数据通信速度的提高和数据通信量的增大。在诸如蜂窝电话、笔记本式个人计算机等移动电子设备中,其中结合有摄像装置的移动电子设备目前正在普及,该摄像装置具有摄像元件,如CCD图像传感器、CMOS图像传感器等。除了字符数据之外,这些设备还可以实时传输由成像装置拍摄的图像数据。
在图5中示出了现有技术中的摄像模块(成像装置)的截面结构。图5中的上部视图示出了以下类型的模块,即摄像元件和基板通过引线接合相连接。在其一端的开口部分中具有聚光透镜11的外壳12用胶粘剂13设置在印刷电路板14上。在外壳12的内部,其中光线接收部分15形成于硅基板16上表面上的摄像元件1(CCD或CMOS图像传感器)用胶粘剂17安装在印刷电路板14上。在硅基板16上表面上的光线接收部分15的周围区域中形成电极片18。电极片18和印刷电路板14上的端子片20分别经由接合引线19电连接。这里,21表示用焊料在外壳12的外部固定于印刷电路板14上的无源元件,例如片形电容器等。
由于光线通过设置在外壳12一端的聚光透镜11会聚,然后通过摄像元件1的光线接收部分15接收,因此可以实现诸如摄像机等光学器件的摄像功能。在以下类型的装置中,即如图5中的上部视图所示,设置在硅基板16上表面的周围区域中的电极片18与印刷电路板14上的端子片20经由接合引线19连接,存在这样的问题,即增大了装置的尺寸。
在图5中的下部视图中,采用了在硅基板16中形成穿透电极22的结构,以代替在摄像元件1的硅基板16上表面的周围布置电极片的结构,这样可以减小装置的尺寸。更具体地说,在硅基板16的周围区域中形成竖直穿透该硅基板的穿透电极22,然后将穿透电极22的上端与光线接收部分15电连接,并且将穿透电极22的下端经由凸点23与端子片20电连接。以这种方式,其上表面上形成有光线接收部分15的摄像元件1通过倒装式接合法安装在印刷电路板14上,使得光线接收部分15与印刷电路板14彼此电连接。这样,可以省略容纳接合引线19的空间部分。因此,可以减小外壳12的尺寸,并且还可以在总体尺寸上将摄像模块从图5中的上部视图所示的尺寸减小到图5中的下部视图所示的尺寸,这如虚线25所示。
图6是图5中的下部视图的局部详细视图,其中形成有穿透电极22。这里,24是印刷电路板14的布线部分,125是红外截止滤光片部分,26是透明绝缘层。
在未审查日本专利公开No.2003-169235(在下文中称为专利文献1)中,作为使用CCD的摄像模块的常规实例,其出于这样的目的而提出了该摄像装置:即,减少模块部件的零件数量、实现尺寸和重量上的减小以及降低生产成本。在该摄像装置中,安装有电路板并且该电路板和外壳在它们边界处互相接合,圆柱形外壳、聚光透镜和传感器件安装在该电路板上,其中,该聚光透镜安装于外壳的开口部分的一侧,以会聚从开口部分入射的光线,传感器件安装于外壳的开口部分的另一侧,以接收由聚光透镜所会聚的光线。然而,在专利文献1所公开的成像装置中,传感器件和电路板通过使用接合引线连接,这样由于需要其中容纳接合引线的空间部分,所以限制了装置尺寸的减小。
此外,在未审查日本专利公开No.2004-22990(在下文中称为专利文献2)中,作为穿透电极形成于基板中的常规实例,提出了这样的穿透孔充填法:即,首先在硅基板中形成穿透孔,然后使用电镀通过充填在穿透孔中填充金属。根据该充填法,为了通过消除充填金属中产生的微小空隙以提高充填金属的密度和附着性,通过电镀在硅基板中的穿透孔中填充金属,接着使硅基板的两个表面平面化,然后对硅基板实施高压退火处理。
如上所述,在以下类型的装置中,即如图5中的上部视图和专利文献1所示,摄像元件与电路板通过引线接合相连接,由于需要其中容纳接合引线的空间部分,所以限制了装置尺寸的减小。
发明内容
下面的公开内容公开了一种具有穿透电极的半导体器件和一种具有该穿透电极的该半导体器件的制造方法,当制造诸如CCD(电荷耦合器件)、CMOS器件、存储器件等器件、以及诸如摄像模块、多级存储模块等模块部件时,该方法通过改进并简化在硅基板中形成穿透电极的方法,能够实现低成本化、小型化、高密度化和高速化。
下面说明本发明的示例实施方案。根据本发明,提供一种具有穿透电极的半导体器件的制造方法,包括以下步骤:在基板中形成穿透孔;在所述基板的一个表面上形成第一金属层,并且在所述第一金属层上设置绝缘保护膜;在使用所述第一金属层作为供电层的同时,借助于从所述基板的另一表面实施第二金属的电镀,用所述第二金属填充所述穿透孔以形成穿透电极;除去所述绝缘保护膜;以及除去位于除所述穿透电极的周围部分之外的区域中的所述第一金属层。
所述基板为半导体基板,器件层和电极片形成于所述半导体基板的所述一个表面上,并且所述穿透孔形成为穿透所述电极片、设置在所述电极片下方的第一绝缘膜和所述基板。
在所述半导体基板中形成所述穿透孔之前,通过蚀刻在所述电极片中形成露出所述第一绝缘膜的第一开口部分,并且对从所述第一开口部分中露出的所述第一绝缘膜实施蚀刻,形成从其露出所述半导体基板的第二开口部分,所述第二开口部分的面积小于所述第一开口部分,然后对从所述第二开口部分露出的所述半导体基板的一部分实施蚀刻,以形成其截面积小于所述第二开口部分的所述穿透孔。
在所述基板中形成所述穿透孔之后,但是在所述基板的一个表面上形成所述第一金属层之前,在包括所述穿透孔的内壁的所述基板的整个表面上形成第二绝缘膜。
在所述基板的一个表面上除所述穿透孔周围部分之外的区域上形成抗蚀层,然后在包括所述穿透孔的内壁的所述基板的整个表面上形成所述第二绝缘膜,然后除去所述抗蚀层和所述抗蚀层上的所述第二绝缘膜,然后形成所述第一金属层。或者,在包括所述穿透孔的内壁的所述基板的整个表面上形成所述第二绝缘膜,然后在所述基板的一个表面上的所述穿透孔的周围部分形成抗蚀层,接着通过蚀刻除去未用所述抗蚀层覆盖的所述第二绝缘膜,接着除去所述抗蚀层,然后形成所述第一金属层。
通过溅射铬和铜形成所述第一金属层,并且通过镀铜形成所述第二金属。
此外,根据本发明,提供一种具有穿透电极的半导体器件的制造方法,该方法包括以下步骤:在半导体基板的一个表面上形成器件层,并且在所述器件层周围形成与所述器件层电连接的电极片;形成穿透所述电极片、设置在所述电极片下方的第一绝缘膜和所述半导体基板的穿透孔;用第二绝缘膜覆盖下述整个表面,所述整个表面包括所述穿透孔的内壁表面、所述第一绝缘膜和所述电极片的开口部分;从所述电极片的上表面的至少一部分区域中除去所述第二绝缘膜;从所述半导体基板的一个表面侧形成第一金属层,以便至少覆盖所述穿透孔的开口部分的周围,这样使得所述第一金属层的一部分与所述电极片电连接;在所述第一金属层上粘贴绝缘带;在使用所述第一金属层作为供电层的同时,借助于从所述半导体基板的另一表面实施第二金属的电镀,用所述第二金属填充所述穿透孔以形成穿透电极;除去所述绝缘带;以及除去位于除所述穿透电极的周围部分之外的区域中的所述第一金属层。
所述器件层和所述电极片均形成于所述半导体基板上的所述第一绝缘膜上。或者,所述器件层直接形成于所述半导体基板上,并且所述电极片形成于所述半导体基板上的所述第一绝缘膜上。
附图说明
图1(a)至图1(d)是剖面图,按步骤顺序示出了根据本发明实施例的具有穿透电极的半导体器件的制造方法。
图2(a)至图2(d)是剖面图,接着图1按步骤顺序示出了根据本发明实施例的具有穿透电极的半导体器件的制造方法。
图3(a)至图3(d)是剖面图,接着图2按步骤顺序示出了根据本发明实施例的具有穿透电极的半导体器件的制造方法。
图4是剖面图,示出了使用按照本发明制造的布线基板的半导体器件。
图5是示出在现有技术中制造的具有穿透电极的摄像模块的视图。
图6是图5中的下部视图的局部详细视图。
具体实施方式
下面将参照图1至图4详细说明本发明的实施例。图1(a)至图1(d)、图2(a)至图2(d)和图3(a)至图3(d)按步骤顺序示出了本发明的具有穿透电极的半导体器件的制造方法。
图1(a)示出了半导体晶片(布线基板)。在这种半导体晶片中,氧化膜(SiO2膜)32形成为覆盖硅(Si)基板(半导体基板)31的上表面的绝缘膜。然后,在氧化膜32上形成器件层33,例如CCD或CMOS图像传感器、存储器等。然后,在氧化膜32上的器件层33周围形成电极片(铝片)34,这样该铝片的一部分与器件层33重叠。然后,在整个表面上形成绝缘膜(钝化膜)35。然后,分别只从比铝片34区域稍窄的区域上除去位于电极片34上方的钝化膜35,以露出铝片34。在这种情况下,除硅基板之外,砷化镓半导体等也可以用作基板31。
这里,举例来说,优选的是,硅(Si)基板31的厚度t设定为例如50至500μm,电极片34形成为单边长度a为例如约100μm的正方形,并且比该正方形稍窄的正方形区域从钝化膜35中露出。
图1(b)示出了通过蚀刻除去从钝化膜35中露出的电极片34的状态。例如,作为这种情况下的蚀刻处理,将抗蚀剂(抗蚀层)(未示出)涂覆在整个表面上,然后通过曝光/显影对该抗蚀剂进行制作图案。然后,通过使用对于氧化膜32没有任何影响的干式(氯基气体)或湿式(磷酸+醋酸+盐酸)蚀刻剂或Stanford蚀刻剂对半导体晶片的上表面实施蚀刻。然后,在完成蚀刻之后除去抗蚀剂。通过这种蚀刻方法除去的电极片部分中的开口部分34a的单边长度b为例如约80μm的正方形,这样使得下方的氧化膜32从开口部分34a中露出。
图1(c)示出了通过蚀刻除去从电极片34的开口部分34a露出的氧化膜32的状态。例如,作为这种情况下的蚀刻处理,将抗蚀剂(未示出)涂覆在整个表面上,然后通过曝光/显影对该抗蚀剂进行制作图案。然后,通过使用对于硅基板31没有任何影响的干式(CHF3或CF4)或湿式(盐酸)蚀刻剂对半导体晶片的上表面实施蚀刻。然后,在完成蚀刻之后除去抗蚀剂。通过这种蚀刻方法除去的氧化膜32的形状为单边长度c为例如约60μm的正方形,这样使得硅基板31的上表面从氧化膜32的作为正方形除去的开口部分32a中露出。
图1(d)示出了通过使用蚀刻的开孔处理在从氧化膜32的正方形开口部分32a中露出的硅基板31的一部分中形成穿透孔36的状态。例如,作为这种情况下的蚀刻处理,将抗蚀剂(未示出)涂覆在整个表面上,然后通过曝光/显影对该抗蚀剂进行制作图案。然后,通过使用干式(SF6气体)蚀刻剂实施蚀刻。然后,在完成蚀刻之后除去抗蚀剂(未示出)。
在通过蚀刻对硅基板31实施开孔处理时,这种处理可以从其上形成电极片34的半导体晶片的上表面侧实施。但是,这种处理也可以从硅基板31的背面实施。在这种情况下,将抗蚀剂(未示出)涂覆在硅基板31的背面侧,然后通过曝光/显影对该抗蚀剂进行制作图案,然后从硅基板31的背面侧施加蚀刻剂。照这样,从器件层33几乎不会受等离子蚀刻影响的观点来看,从硅基板31的背面侧实施的蚀刻是有利的。
根据这种蚀刻,在与氧化膜32的开口部分32a对应的位置处形成从上表面到下表面穿透硅基板31的穿透孔36。穿透孔36具有例如大约40μm的内径d。
根据上述结构,由于开口部分的不同长度b、c、d,所以穿透孔36的内壁具有阶梯状截面。凭借穿透孔36的这种阶梯状内壁,可以延长电极片34的开口部分34a的侧壁与硅基板31的开口部分的侧壁之间的距离。因此,可以保证电极片34与硅基板31之间的充分绝缘。此外,与穿透孔的内壁不是阶梯形状,即开口部分的长度相同的情况相比,内壁在竖直方向上的笔直部分变得较短。因此,在通过溅射或CVD(化学气相沉积)形成后面提到的绝缘膜38和金属层39的情况下,可以顺序形成具有足够厚度的这些膜和层。因此,可以保证充分的电连接以及充分的绝缘。
图2(a)示出了通过在绝缘膜(钝化膜)35和电极片34上涂覆抗蚀剂,然后对该抗蚀剂进行制作图案而形成抗蚀图案37的状态。更具体地说,在包括绝缘膜(钝化膜)35和电极片34的半导体晶片整个表面上涂覆抗蚀剂,然后通过曝光/显影形成图案,这样从穿透孔的下述周围部分除去该抗蚀剂,所述周围部分包括穿透孔36和穿透孔36周围的硅基板31的上表面的区域、氧化膜32的露出表面以及电极片34的内侧部分。这样,形成用于覆盖钝化膜35的整个表面以及与钝化膜35邻近的电极片34的一部分的抗蚀图案37。
图2(b)示出了在包括硅基板31下表面和穿透孔36内壁表面的半导体晶片整个表面上形成薄绝缘膜38的状态。可以通过在例如250℃或更低温度下从半导体晶片的上表面和下表面实施低温化学气相沉积(CVD)而形成这种绝缘膜38。但是,可以通过以下方式在半导体晶片的整个表面上形成绝缘膜38,即在从该半导体晶片的上表面实施CVD之后,上下翻转该半导体晶片,然后从下表面实施CVD。可以采用SiOx、SiNx、SiNOx等作为CVD中所使用的绝缘膜38的材料。绝缘膜38的厚度设定为例如大约0.2至0.5μm。因此,在包括穿透孔36内壁的半导体晶片整个表面上形成绝缘膜38。
图2(c)示出了除去图2(a)所示步骤中形成的抗蚀图案37的状态。为了除去抗蚀图案37,使用所谓的举离法(lift-off)比较有利。根据举离法,除去抗蚀图案37,并且同时还除去抗蚀图案37上表面上的绝缘膜38。因此,使得电极片34局部露出,并且使得用于覆盖器件层33的钝化膜35也露出。穿透孔36的内表面侧和半导体晶片的背面侧仍然覆盖有绝缘膜38。
在这种情况下,可以采用例如下列步骤代替图2(a)至图2(c)中的步骤。也就是说,在图2(a)中,首先在钝化膜35和电极片34上面形成抗蚀图案37。在这种情况下,在形成抗蚀图案37之前,在包括穿透孔36的内壁表面的半导体晶片的整个上表面和下表面上形成图2(b)所示步骤中的绝缘膜38。然后,在绝缘膜38上面涂覆抗蚀剂(未示出)并进行制作图案。然后,通过使用形成图案的抗蚀剂作为掩模蚀刻绝缘膜38,从而除去除穿透孔36侧的端部之外的钝化膜35上的绝缘膜38和电极片34上的绝缘膜。然后,除去所使用的抗蚀剂。根据这些步骤,可以通过不同于举离法的方法形成与图2(c)中所示类似的半导体晶片。
图2(d)示出了通过溅射从半导体晶片的上侧形成金属膜39的状态。形成例如50nm厚的铬(Cr)膜并在其上面形成500nm厚的铜(Cu)膜作为金属膜39。由于通过溅射从半导体晶片的上侧形成金属膜39,所以半导体晶片的整个上表面覆盖有导电的金属膜39。相比之下,金属膜39只附着在半导体晶片上部的穿透孔36的内壁上,但是金属膜39不会附着在穿透孔36的大部分内壁区域和该晶片的下表面上。
图3(a)示出了保护膜40粘贴在晶片上表面上的状态。通过热压,在适当的温度(例如,150℃)下对绝缘树脂构成的材料(例如UV剥离带等材料)施加适当的压力(例如,1MPa),从而将这种保护膜40粘贴到晶片上表面的整个区域上。
图3(b)示出了通过以下方法形成穿透电极42的状态,即在从如箭头41所示的、形成于晶片上表面的整个区域上的金属膜39的端部供给电镀用的电力,同时从该晶片的背面实施电解镀铜。以这种方式,由于金属膜39形成于晶片上表面的整个区域上,所以可以通过使用穿透孔36上方的金属膜39作为一个电极实施电镀铜(Cu)。这样,穿透孔36的内部完全填满铜从而可以形成穿透电极42。相比之下,由于晶片的上表面用保护膜40保护,因此铜不会通过电镀而附着在晶片的上表面上,例如附着在钝化膜35等上方存在的金属膜39上。
图3(c)示出了通过紫外线辐射除去粘贴到晶片上表面上的保护膜40的状态。这是由于在电镀中用作供电层的金属膜39必须通过随后的步骤部分地除去的缘故。
图3(d)示出了从除穿透孔36的周围部分之外的区域上除去金属膜39的状态。实施铜(Cu)和铬(Cr)的蚀刻,以这种方式部分地除去金属膜39。众所周知,作为这种蚀刻方法,将抗蚀剂(未示出)涂覆在晶片的上表面的整个区域上,然后通过曝光/显影对该抗蚀剂进行制作图案。然后,在使用Stanford蚀刻剂的干式或湿式蚀刻剂的同时,实施蚀刻。接着,在完成蚀刻之后除去抗蚀剂。因此,切断晶片上表面上经由金属膜39进行的整体传导(导通),并且只有穿透孔36中的穿透电极42和穿透电极上表面和下表面上的端子部分仍然保持为传导部分。在这种情况下,可以通过蚀刻金属膜以形成布线图案,从而在钝化膜35上形成布线。
此后,通过对半导体晶片的预定部分实施切割获得单独的半导体器件。
如上所述,本发明的具有穿透电极的半导体器件(布线基板)可以通过图1(a)至图1(d)、图2(a)至图2(d)和图3(a)至图3(d)中的各个步骤进行制造。
图4示出了这样的情况:即,通过使用按照上述步骤制造的半导体器件(布线基板),形成在其背面上具有重新布线的半导体器件的情况。这种半导体器件可以按照例如下列步骤制造。
通过对图3(d)所示状态下的半导体晶片的背面进行抛光,使从穿透孔36的底部伸出的穿透电极42平面化。然后,通过溅射在晶片的背面上形成铜(Cu)/铬(Cr)膜。然后,通过涂覆抗蚀剂(未示出),并经由曝光/显影使该抗蚀剂形成图案从而形成重新布线部分50。然后,涂覆抗蚀剂(抗蚀层)51,并对这种抗蚀剂51进行制作图案,以便只露出其中形成外部连接端子的部分。然后,对重新布线部分50上的外部连接端子形成部分实施镀镍(Ni)/金(Au)53,接着在其上形成用作外部连接端子的焊料凸点52。接下来,对半导体晶片的预定部分实施切割。以这种方式,可以获得如图4所示的在背面具有重新布线的半导体器件。
通过以上说明,参照附图说明了本发明的实施例。但是本发明不限于上述实施例,并且可以在本发明的要旨和保护范围内进行变化、修改等而成为各种形式。在这种情况下,在制造半导体器件的实际步骤中,在半导体晶片中形成穿透电极,然后通过将晶片切割成片来制造单独的半导体器件。
此外,在上述实施例中,说明了器件层33和电极(铝)片34均形成于硅基板31上的第一绝缘膜(氧化膜32)上的情况。然而,在某些情况下,器件层33可以直接形成于硅基板31上,这取决于器件,如晶体管等。在这种情况下,第一绝缘膜(氧化膜32)形成于电极片34的下方。
如上所述,根据本发明,在诸如CCD(电荷耦合器件)、CMOS器件、存储器件等器件、以及诸如摄像模块、多级存储模块等模块部件中,可以通过简单的方法在硅基板中形成穿透电极,并且可以实现低成本化、小型化、高密度化和高速化。
Claims (12)
1.一种具有穿透电极的半导体器件的制造方法,包括以下步骤:
在基板中形成穿透孔;
在所述基板的一个表面上形成第一金属层,并且在所述第一金属层上设置绝缘保护膜;
在使用所述第一金属层作为供电层的同时,借助于从所述基板的另一表面实施第二金属的电镀,用所述第二金属填充所述穿透孔以形成穿透电极;
除去所述绝缘保护膜;以及
除去位于除所述穿透电极的周围部分之外的区域中的所述第一金属层。
2.根据权利要求1所述的具有穿透电极的半导体器件的制造方法,还包括以下步骤:
在所述基板的所述一个表面上形成器件层和第一绝缘膜,并且在所述基板的所述一个表面上的所述第一绝缘膜的上方形成电极片,
其中,所述基板为半导体基板,并且所述穿透孔形成为穿透所述电极片、设置在所述电极片下方的所述第一绝缘膜和所述基板。
3.根据权利要求2所述的具有穿透电极的半导体器件的制造方法,还包括以下步骤:
在所述半导体基板中形成所述穿透孔之前,通过蚀刻在所述电极片中形成露出所述第一绝缘膜的第一开口部分,并且对从所述第一开口部分中露出的所述第一绝缘膜实施蚀刻,形成从其露出所述半导体基板的第二开口部分,所述第二开口部分的面积小于所述第一开口部分,
其中,对从所述第二开口部分露出的所述半导体基板的一部分实施蚀刻,形成其截面积小于所述第二开口部分的所述穿透孔。
4.根据权利要求1所述的具有穿透电极的半导体器件的制造方法,还包括以下步骤:
在所述基板中形成所述穿透孔之后,但是在所述基板的所述一个表面上形成所述第一金属层之前,在包括所述穿透孔的内壁的所述基板的整个表面上形成第二绝缘膜。
5.根据权利要求4所述的具有穿透电极的半导体器件的制造方法,还包括以下步骤:
在形成所述第二绝缘膜之前,在所述基板的所述一个表面上除所述穿透孔的周围部分之外的区域上形成抗蚀层;以及
除去所述抗蚀层和所述抗蚀层上的所述第二绝缘膜,
其中,在除去所述抗蚀层和所述第二绝缘膜之后形成所述第一金属层。
6.根据权利要求4所述的具有穿透电极的半导体器件的制造方法,还包括以下步骤:
在形成所述第二绝缘膜之后,在所述基板的所述一个表面上的所述穿透孔的周围部分形成抗蚀层;以及
通过蚀刻,除去未用所述抗蚀层覆盖的所述第二绝缘膜,然后除去所述抗蚀层,
其中,在除去所述抗蚀层之后形成所述第一金属层。
7.根据权利要求1所述的具有穿透电极的半导体器件的制造方法,其中,
通过溅射铬和铜形成所述第一金属层,并且通过镀铜形成所述第二金属。
8.一种具有穿透电极的半导体器件的制造方法,包括以下步骤:
在半导体基板的一个表面上形成器件层,并且在所述器件层周围形成与所述器件层电连接的电极片;
形成穿透所述电极片、设置在所述电极片下方的第一绝缘膜和所述半导体基板的穿透孔;
用第二绝缘膜覆盖下述整个表面,所述整个表面包括所述穿透孔的内壁表面、所述第一绝缘膜和所述电极片的开口部分;
从所述电极片的上表面的至少一部分区域中除去所述第二绝缘膜;
从所述半导体基板的一个表面侧形成第一金属层,以便至少覆盖所述穿透孔的开口部分的周围,这样使得所述第一金属层的一部分与所述电极片电连接;
在所述第一金属层上粘贴绝缘带;
在使用所述第一金属层作为供电层的同时,借助于从所述半导体基板的另一表面实施第二金属的电镀,用所述第二金属填充所述穿透孔以形成穿透电极;
除去所述绝缘带;以及
除去位于除所述穿透电极的周围部分之外的区域中的所述第一金属层。
9.根据权利要求8所述的具有穿透电极的半导体器件的制造方法,其中,
所述器件层和所述电极片均形成于所述半导体基板上的所述第一绝缘膜上。
10.根据权利要求8所述的具有穿透电极的半导体器件的制造方法,其中,
所述器件层直接形成于所述半导体基板上,并且所述电极片形成于所述半导体基板上的所述第一绝缘膜上。
11.一种半导体器件,包括:
半导体基板;
器件层,其形成于所述半导体基板的一个表面上;
电极片,其形成于所述半导体基板的所述一个表面上,并且与所述器件层电连接;
第一绝缘膜,其位于所述半导体基板的所述一个表面上的所述电极片下方;
穿透孔,其穿透所述电极片、所述第一绝缘膜和所述半导体基板,并且具有截面为阶梯状的内壁;
第二绝缘膜,其形成于所述半导体基板的另一表面、所述穿透孔的内壁和所述半导体基板的所述一个表面上的所述穿透孔的周围部分上;
穿透电极,其形成于由所述第二绝缘膜覆盖的所述穿透孔中;以及
金属层,其形成于所述半导体基板的所述一个表面上的所述穿透孔的周围部分,并且使所述电极片与所述穿透电极电连接。
12.根据权利要求11所述的具有穿透电极的半导体器件,其中,
所述穿透孔在穿过所述第一绝缘膜的部分具有比穿过所述电极片的部分更小的直径,并且在穿过所述半导体基板的部分具有比穿过所述第一绝缘膜的部分更小的直径。
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CNA200610086505XA Pending CN1881535A (zh) | 2005-06-17 | 2006-06-16 | 具有穿透电极的半导体器件及其制造方法 |
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US (1) | US7524753B2 (zh) |
EP (1) | EP1734576A1 (zh) |
JP (1) | JP4698296B2 (zh) |
KR (1) | KR20060132490A (zh) |
CN (1) | CN1881535A (zh) |
TW (1) | TW200707643A (zh) |
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Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4017382B2 (ja) | 2001-11-30 | 2007-12-05 | 新光電気工業株式会社 | 撮像装置 |
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JP2004327910A (ja) * | 2003-04-28 | 2004-11-18 | Sharp Corp | 半導体装置およびその製造方法 |
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-
2005
- 2005-06-17 JP JP2005178534A patent/JP4698296B2/ja active Active
-
2006
- 2006-06-15 US US11/424,385 patent/US7524753B2/en active Active
- 2006-06-16 CN CNA200610086505XA patent/CN1881535A/zh active Pending
- 2006-06-16 KR KR1020060054365A patent/KR20060132490A/ko not_active Application Discontinuation
- 2006-06-16 TW TW095121568A patent/TW200707643A/zh unknown
- 2006-06-19 EP EP06012546A patent/EP1734576A1/en not_active Withdrawn
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CN101783329A (zh) * | 2009-01-13 | 2010-07-21 | 台湾积体电路制造股份有限公司 | 半导体元件及其制法 |
US8399354B2 (en) | 2009-01-13 | 2013-03-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via with low-K dielectric liner |
US9064940B2 (en) | 2009-01-13 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via with low-K dielectric liner |
US10707149B2 (en) | 2009-01-13 | 2020-07-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via with low-K dielectric liner |
US11600551B2 (en) | 2009-01-13 | 2023-03-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via with low-K dielectric liner |
CN106206498A (zh) * | 2014-09-18 | 2016-12-07 | 爱思开海力士有限公司 | 半导体器件以及包括该半导体器件的半导体封装 |
CN106206498B (zh) * | 2014-09-18 | 2019-09-03 | 爱思开海力士有限公司 | 半导体器件以及包括该半导体器件的半导体封装 |
Also Published As
Publication number | Publication date |
---|---|
TW200707643A (en) | 2007-02-16 |
JP4698296B2 (ja) | 2011-06-08 |
KR20060132490A (ko) | 2006-12-21 |
JP2006351968A (ja) | 2006-12-28 |
US7524753B2 (en) | 2009-04-28 |
EP1734576A1 (en) | 2006-12-20 |
US20060286789A1 (en) | 2006-12-21 |
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