CN1883054A - 超薄硅上的nrom闪速存储器 - Google Patents

超薄硅上的nrom闪速存储器 Download PDF

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CN1883054A
CN1883054A CNA2004800338366A CN200480033836A CN1883054A CN 1883054 A CN1883054 A CN 1883054A CN A2004800338366 A CNA2004800338366 A CN A2004800338366A CN 200480033836 A CN200480033836 A CN 200480033836A CN 1883054 A CN1883054 A CN 1883054A
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oxide
source
drain regions
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gate insulator
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L·福布斯
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Micron Technology Inc
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Abstract

以超薄绝缘体上硅结构实现NROM闪存单元。在平面器件中，位于源极/漏极(220，221)区之间的沟道(200)是通常完全耗尽的。氧化物层(210，211)提供了源极/漏极区和上层栅极绝缘体层(207)之间的绝缘。控制栅极(230)形成在栅极绝缘体层上。在垂直器件中，氧化物柱(310)从衬底延伸，在柱的两侧有源极/漏极区(330，331)。外延再生长被用来沿着氧化物柱侧壁形成超薄硅体区(300，301)。在此结构上形成第二源极/漏极区(320，321)。栅极绝缘体(307)和控制栅极(330)形成在上。

Description

超薄硅上的NROM闪速存储器
                            技术领域
本发明一般涉及存储器，本发明尤其涉及氮化物只读存储器闪速存储器。
                            背景技术
计算机以及其他电子器件的速度和容量的发展需要组成器件的集成电路具有更好的性能。一种使集成电路更快的方法是减小组成器件的晶体管的尺寸。然而，当晶体管做得越来越小和越来越快时，相对于晶体管的速度而言，在晶体管之间的连接中的延时变得更大。
另外一种提高集成电路速度的方法是使用替代的半导体。例如，绝缘体上硅结构(SOI)技术在同样的CMOS技术下可提高性能25-35％。SOI指将薄硅层放置在诸如氧化硅或玻璃的绝缘体上。晶体管接着被构造在该SOI薄层上。该SOI层减小了晶体管的电容，因此晶体管运行更快。
图1示出了一个典型的现有技术的SOI半导体。晶体管形成在位于绝缘体102上的硅层101中。绝缘体形成在衬底103上。在硅层101内，形成漏极/源极区105和106。栅极107形成在部分耗尽沟道109上。浮体110位于耗尽区112内，且由部分耗尽产生。
然而，SOI技术对技术要求非常高。用于SOI晶体管的硅膜必须是完全晶体硅。然而，绝缘体层不是晶体。因为绝缘体层的晶体性质与纯硅完全不同，所以很难用绝缘体制作完全晶体的氧化物上硅结构(silicon-on-oxide)或硅。如果不能得到完全的晶体硅，SOI膜上就会有缺陷。这就劣化了晶体管的性能。
此外，使用SOI技术的部分耗尽CMOS器件中的浮体效应在许多逻辑和存储器应用中是不受欢迎的。浮体导致阈值电压和开关速度成为某一逻辑门的开关历史的可变复函数。在动态逻辑和DRAM存储器中，浮体导致过度的电荷泄漏和短保持时间，将导致数据丢失。在传统的闪速存储器和NROM器件中，浮体导致减少的擦除场(erase field)和更慢的擦除时间。
因为上述原因，以及本领域技术人员通过阅读和理解本说明书之后可以清楚看出的下面所述的其他原因，本领域需要一种方法来消除结合SOI技术的CMOS器件中的浮体效应。
                            发明内容
上述关于消除浮体效应的问题以及其他问题由本发明来解决，通过阅读和学习下面的说明书可以得到理解。
本发明包括一种具有超薄绝缘体上硅结构衬底的NROM晶体管。硅具有由通常完全耗尽体区隔开的两个掺杂的源极/漏极区。掺杂区与衬底的电导率不同。
在源极/漏极区的每一个上形成氧化物层。在体区和氧化物层上形成栅极绝缘体。栅极绝缘体能够储存大量电荷。在栅极绝缘体上形成控制栅极。
本发明的进一步的实施例包括变化范围的方法和装置。
                            附图说明
图1是现有技术下典型SOI半导体的截面图。
图2是使用超薄SOI的平面或非NROM单元的一个实施例的截面图。
图3是使用超薄SOI的本发明的两个垂直或非NROM单元的实施例的截面图。
图4是使用超薄SOI的本发明的两个垂直或非NROM单元的另一个实施例的截面图。
图5是本发明的或非NROM闪存阵列的等效电路。
图6是使用超薄SOI的本发明的垂直或非NROM存储器阵列的另一个可选实施例的截面图。
图7是根据图6的实施例的本发明的或非NROM闪存阵列的等效电路。
图8是使用超薄SOI的本发明的平面与非NROM单元的实施例的截面图。
图9是使用超薄SOI的本发明的两个垂直与非NROM单元的实施例的截面图。
图10是根据图9的实施例的本发明的与非NROM闪存阵列的等效电路。
图11是本发明的电子系统的实施例的框图。
                           具体实施方式
在接下来对本发明的描述中，参考作为此处组成部分的附图，附图以举例的方法示出了本发明得以实施的具体实施例。在图中，相同的数字在几张图中表示相同的组件。这些实施例充分详述，以便本领域的技术人员可以实施本发明。也可以利用其他实施例，并且在不背离本发明范围下，可以在结构上、逻辑上和电气上作出改变。因此，接下来的详细描述不应受限制，本发明的范围仅由附加的权利要求和它的等效物所定义。
图2示出了使用超薄绝缘体上硅结构(SOI)技术的平面NROM单元的一个实施例的截面图。图2的NROM闪存单元是具有虚拟地位线的或非(NOR)阵列单元。
NROM闪存单元由绝缘体202上的硅层201组成。在超薄SOI单元中硅201小于100nm(1000)。层201由充当位线220和221的两个源极/漏极区220和221组成。在一个实施例中，这些区220和221是n-型材料。可选实施例中如果衬底是n-型材料，则这些区就用p-型材料。
在位线220和221之间的体区200在超薄SOI中通常是完全耗尽的。体区200由离子化受主杂质203和离子化施主杂质205组成。两个氧化物区210和211淀积在硅201上。
在一个实施例中，栅极绝缘体207是形成在控制栅极230和硅层201之间的氧化物-氮化物-氧化物(ONO)复合结构。在一个实施例中，控制栅极230是多晶硅材料，并且在或非闪存单元实施例中沿“x”方向延伸。氮化物层225有两个电荷存储区231和232。
本发明的可选实施例使用除了所示的ONO复合结构以外的其他栅极绝缘体。这些结构可包括氧化物-氮化物-氧化铝复合层、氧化物-氧化铝-氧化物复合层、氧化物、碳氧化硅-氧化物复合层以及其他复合层。
在又一可选实施例中，除了诸如Si、N、Al、Ti、Ta、Hf、Zr以及La之类的两种或多种常用绝缘体材料的其他非化学计量单层栅极绝缘体以外，栅极绝缘体可包括比由湿氧化且不退火形成的一般氧化硅更厚的、包含毫微硅粒子的富硅氧化物、非复合层的氮氧化硅层、非复合层的富硅氧化铝绝缘体、非复合层的碳氧化硅绝缘体、包含碳化硅毫微粒子的氧化硅绝缘体。
图3示出了使用超薄SOI的本发明的两个垂直或非NROM单元350和351的一个实施例的截面图。垂直实施例提供了更高密度的存储器阵列。
图3中的单元350和351每个都有源极/漏极区330和331，作为位线，并由n+掺杂硅组成。其他实施例如果衬底由n-型材料组成，则这些区使用p-型材料。每一个晶体管的额外的源极/漏极区320和321形成在垂直氧化物柱310上。左边的晶体管350使用源极/漏极区320和331而右边的晶体管使用源极/漏极区321和330。上部的源极/漏极区320和321由晶界分隔但电气耦合。垂直氧化物柱310是两个晶体管350和351之间的绝缘体。
垂直外延再生长被用来提供沿着垂直氧化物柱310的侧壁的超薄硅非晶层300和301层。这些层就是超薄硅(即＜100nm)体区300和301而且通常完全耗尽。硅体区300和301的厚度方向在每个区中示出。左边超薄硅体区是左晶体管350的一部分，而右边体区300是右晶体管351的一部分。
在一个实施例中，栅极绝缘体层307是复合ONO结构。该层307的可选实施例在上文中已经揭示。控制栅极330形成在该绝缘体层307之上且为晶体管350和351共有，因此它用作存储器阵列的字线。在一个实施例中，控制栅极330是多晶硅材料。
图4示出了使用超薄SOI的本发明的两个垂直或非NROM单元的另一个实施例的截面图。这个实施例具有和图3的实施例基本相似的结构，其中超薄硅体区400和401通过沿着氧化物柱410的侧壁外延再生张而形成。上源极/漏极区420和421形成在氧化物柱410上，且公共聚控制栅极405形成在栅极绝缘体420上，通过字线将晶体管450和451耦合。
然而，在图4的实施例中，栅极绝缘体420的底部氧化物层402和404在沟槽(trench)中比前一个实施例中厚。此外，图3中的两个源极/漏极区被在更厚的氧化物层的部分之间隔离的单个n+源极/漏极区430所代替。
图5示出了本发明的或非NROM闪存阵列的等效电路。该电路可表示本发明的平面实施例以及图3的垂直实施例。
控制栅极501与阵列中的所有器件510-512交叉。n+源极/漏极区503和504用作虚拟地数据或位线。如本领域众所周知，该阵列的位线耦合于读出放大器以便从单元510-512中读取数据。控制栅极501是用于选择单元510-512的字线。
图6示出了使用超薄SOI的本发明的垂直或非NROM存储器阵列的另一个可选实施例的截面图。这张图示出了四个垂直晶体管650-653。为了清楚起见，只描述围绕第一氧化物柱632形成的晶体管。余下的晶体管在结构和运行上实质相同。
如前述实施例中那样，两个超薄硅体区608和609通过沿氧化物柱632的侧壁外延再生长而形成。栅极绝缘体层601和602沿硅体区608和609并排形成。每一个晶体管650和651的n+多晶硅栅极结构630和631形成在绝缘体层601和602上。
氮化物层603和604为每一个晶体管650-653提供两个电荷存储区610和611。在沟槽区中，下层氧化物层605相比栅极绝缘体层的其余部分有更厚的组成。根据每一个晶体管偏压方向，上面的单元650-653形成在衬底上充当公共源极/漏极区的下层n+区620上。
上层的n+区660和661是每一个晶体管650和651的第二个公共源极/漏极区。每一个晶体管的上层n+区660和611通过接线640或者其他导电器件与阵列中的其他晶体管耦合。
图7示出了根据图6的实施例的本发明的或非NROM闪存阵列的等效电路。该图示出了如上面图6所描述的各单元650-653。
控制栅极701-704耦合到阵列中的其他单元，并作为字线。这些控制栅极701-704中的两个在图6中示出为630和631。上公共源极/漏极区660和661被示为虚拟地或数据位线709，而公共源极/漏极区620被示为虚拟地或数据位线708。
图8示出了使用超薄SOI的本发明的平面与非(NAND)NROM单元的一个实施例的截面图。该实施例包含了两个具有在超薄SOI中的完全耗尽体区801的源极/漏极区803和804。两个氧化物区807和808形成在n+区上，并且栅极绝缘体805形成在该结构上。在一个实施例中，栅极绝缘体805是复合ONO层，但是可以是包括前面阐述的那些材料在内的任何其他类型材料。
控制栅极806形成在栅极绝缘体805上。在与非实施例中，栅极806在“z”方向延伸而不是在或非实施例中那样在“x”方向延伸。
图9示出了使用超薄SOI的本发明的两个垂直与非NROM单元910和911的一个实施例的截面图。每个晶体管910和911由形成于p-型衬底材料中的源极/漏极区905和906所组成。第二源极/漏极区920和921形成在氧化物柱930上，并由晶界分隔，但仍然电气耦合。源极/漏极区905、906、920和921用作虚拟地位线/数据线。
外延再生长用于在氧化物柱930的侧壁上生长超薄硅体区901和902。如在前面的实施例中那样，这些区901和902每一个都小于100nm厚。
栅极绝缘体950形成在晶体管910和911上。在一个实施例中，栅极绝缘体950是ONO复合层。该复合层的可选实施例前面已经示出。
每一个晶体管910和911的控制栅极907和908分别在栅极绝缘体950的每一侧上从多晶硅材料形成。控制栅极907和908耦合于其他晶体管以充当字线。
图10示出了根据图9的实施例的本发明的与非NROM闪存阵列的等效电路。示出了图9的两个晶体管910和911。
图10的n+源极/漏极连接1005对应图9的两个源极/漏极区920和921。图10的字线1001和1002分别对应图9的控制栅极907和908。图9的衬底上形成的源极/漏极区905和906对应图10的源极/漏极连接1009和1007。
上述实施例是作为n-沟道型晶体管示出的。然而，本领域的普通技术人员会理解，通过改变掺杂类型可以使电导率类型相反，使得本发明同样可以应用于包括具有超薄硅、p-沟道型晶体管的NROM结构。
用于形成本发明的超薄硅NROM闪存单元的掩模和蚀刻步骤不作详细讨论。形成上述结构所需的各步骤已被本领域技术人员所知。
图11示出了可使用本发明的超薄SOI闪存单元的存储器1100的功能框图。存储器1100耦合于处理器1110。处理器1110可以是微处理器或者某种其他类型的控制电路。存储器1100和处理器1110构成电子系统1120的一部分。存储器1100被简化以聚焦于存储器的特征上，以便对理解本发明有帮助。
存储器包括闪存单元阵列1130。在一个实施例中，这些存储单元是NROM闪存单元，而且该存储器阵列1130按行和列的存储体排列。每一行存储单元的控制栅极与字线耦合，而存储单元的漏极和源极连接耦合于位线。如本领域众所周知，单元到位线的连接取决于阵列是与非结构还是或非结构。
提供地址缓存电路1140用于锁存由地址输入连接A0-Ax 1142上提供的地址信号。地址信号被行解码器1144和列解码器1146接收并解码，以访问存储器阵列1130。本领域技术人员将会理解，得益于此处的描述，地址输入连接的数量取决于存储器阵列1130的密度和结构。即，地址数量是随着存储单元数和存储体和块数的增长而增长的。
存储器1100通过使用检测/缓存电路1150检测存储器阵列的列中的电压或电流的变化来读取存储器阵列1130中的数据。在一个实施例中，该检测/缓存电路被耦合来读取和锁存来自存储器阵列1130的行的数据。数据输入和输出缓存电路1160被包含在内用于通过多个与控制器1110的数据连接进行双向数据通讯。写电路1155被提供用来向存储器阵列写入数据。
控制电路1170对从处理器1110通过控制连接1172提供的信号进行解码。这些信号用于控制存储器阵列1130的运行，包括数据读取、数据写入以及擦除操作。控制电路1170可以是状态机、序列发生器、或者某种其他类型的控制器。
因为本发明的NROM存储单元采用了CMOS兼容工艺，图11中的存储器1100可以是具有CMOS处理器的嵌入式器件。
图11中示出的闪存存储器已经被简化以方便对存储器特征的基本理解。对闪存内部电路和功能的更详细的理解对本领域的技术人员来说是已知的。
总之，本发明的NROM闪存单元利用超薄SOI来提供完全耗尽的体区。这消除了部分耗尽的CMOS器件所遭受的不合需要的浮体效应。
虽然在这里示出并阐述了具体的实施例，本领域普通技术人员会明白，能达到同样目的而作出的任何配置可以代替所示的具体实施例。本发明的许多改变对本领域的普通技术人员来说都将是明显的。因此，本申请意图覆盖本发明的任何改变和变型。很明显，本发明由下面的权利要求和其等价物所限制。

Claims (32)

1、一种NROM晶体管，包含：
具有由通常完全耗尽的体区分隔的两个源极/漏极区的超薄绝缘体上硅结构层；
形成在源极/漏极区的每一个上的氧化物层；
形成在体区和氧化物层上的栅极绝缘体，栅极绝缘体能存储大量电荷；以及
形成在栅极绝缘体上的控制栅极。
2、如权利要求1所述的晶体管，其特征在于，栅极绝缘体是氧化物—氮化物—氧化物复合结构。
3、如权利要求1所述的晶体管，其特征在于，栅极绝缘体层是由氧化物—氮化物—氧化铝复合层、氧化物—氧化铝—氧化物复合层、或者氧化物—碳氧化硅—氧化物复合层中之一组成的复合层。
4、如权利要求1所述的晶体管，其特征在于，栅极绝缘体层是由湿氧化且不退火形成的氧化硅、包含毫微硅粒子的富硅氧化物、氮氧化硅层、富硅氧化铝绝缘体、碳氧化硅绝缘体、包含碳化硅毫微粒子的氧化硅绝缘体之一组成的非复合层。
5、如权利要求1所述的晶体管，其特征在于，栅极绝缘体由硅、氮、铝、钛、钽、铪、镧或锆中的两种或多种的非化学计量单层组成。
6、如权利要求1所述的晶体管，其特征在于，晶体管有平面结构。
7、如权利要求1所述的晶体管，其特征在于，晶体管有与非构造。
8、如权利要求1所述的晶体管，其特征在于，晶体管有或非构造。
9、一种NROM闪存单元，包含：
包含绝缘体层和厚度小于100nm的绝缘体上硅结构层的衬底，绝缘体上硅结构层包含由通常完全耗尽的体区分隔的两个源极/漏极区；
形成在源极/漏极区的每一个上的氧化物层；
形成在体区和氧化物层上的复合栅极绝缘体，该栅极绝缘体具有氮化物层，当单元以第一方向工作时可存储第一电荷，而当单元以第二方向工作时可存储第二电荷；以及
形成在复合栅极绝缘体上的控制栅极。
10、如权利要求9所述单元，其特征在于，控制栅极由多晶硅材料组成。
11、如权利要求9所述单元，其特征在于，当单元以第一方向工作时，第一源极/漏极区作为漏极区运行，而当单元以第二方向工作时，第一源极/漏极区作为源极区运行。
12、一种垂直NROM闪存阵列，包含：
具有第一组多个源极/漏极区的衬底；
从衬底向外沿伸的氧化物柱；
多个的超薄硅体区，每一个包含沿着氧化物柱的相对侧壁的硅的外延再生长，每个体区从不同的源极/漏极区垂直延伸；
形成在氧化物柱上的第二组多个源极/漏极区，每个源极/漏极区耦合于不同的体区；
形成在第一组多个源极/漏极区、多个体区、以及第二组多个源极/漏极区上的绝缘体层；以及
形成在绝缘体层上的控制栅极。
13、如权利要求12所述阵列，其特征在于，存储器阵列的第一晶体管由来自第一组多个源极/漏极区的第一源极/漏极区、第一超薄硅体区、来自第二组多个源极/漏极区的第一源极/漏极区、第一硅体区上的绝缘体层的一部分、以及该部分绝缘体层上的控制栅极的一部分组成。
14、如权利要求12所述阵列，其特征在于，绝缘体层由复合氧化物-氮化物-氧化物结构组成。
15、如权利要求14所述阵列，其特征在于，下层氧化物层在氧化物柱任一侧沟槽中比围绕氧化物柱排列的其余部分厚度更大。
16、如权利要求15所述阵列，其特征在于，第一组多个源极/漏极区在每条沟槽之间是隔离的。
17、一种垂直NROM闪存阵列，包含：
具有下层源极/漏极区的衬底；
在下层源极/漏极区上从衬底向外延伸的氧化物柱；
多个超薄硅体区，每个包含沿着氧化物柱的相对的侧壁的硅的外延再生长，每个体区从下层源极/漏极区的每一侧垂直延伸；
形成在氧化物柱上的上层源极/漏极区，上层源极/漏极区的每一侧耦合于不同的体区；形成在下层源极/漏极区、多个体区、上层源极/漏极区任一侧周围的绝缘体层，在下层源极/漏极区每一侧的绝缘体层部分比其余的绝缘体层部分更厚，使得下层漏极/源极区在较厚的绝缘体层部分之间隔离；以及
形成在绝缘体层上的控制栅极。
18、如权利要求17所述存储器阵列，其特征在于，较厚的绝缘体层部分是下层氧化物层。
19、一种垂直NROM闪存阵列，包含：
衬底，衬底具有与沿着衬底延伸的、具有与衬底电导率类型不同的电导率的掺杂区，掺杂区作为第一源极/漏极区；
从第一源极/漏极区延伸的多个氧化物柱；
分别沿着氧化物柱的相对侧壁形成的多个超薄硅体区，每个超薄硅体区是完全耗尽的；
形成在每个氧化物柱和每个体区上的多晶硅材料，该多晶硅材料作为第二源极/漏极区，并具有和第一源极/漏极区相同类型的电导率类型；
形成在衬底、体区、第二源极/漏极区上的氧化物层，使得该氧化物层沿着衬底比在其他区域中厚度大；
形成在氧化物层上仅位于氧化物柱相对侧上的氮化物-氧化物层；以及
形成在氮化物-氧化物层上的多晶硅控制栅极。
20、如权利要求19所述存储器阵列，其特征在于，还包括耦合每个氧化物柱上的第二源极/漏极区的导线。
21、如权利要求19所述存储器阵列，其特征在于，第一和第二源极/漏极区是n+型电导率材料。
22、如权利要求19所述存储器阵列，其特征在于，该阵列是或非类型结构。
23、一种电子系统，包含：
产生系统的控制信号的处理器；以及
耦合于处理器并具有多个存储单元的存储器阵列，该存储器阵列包含：
具有由通常完全耗尽的体区分隔的两个源极/漏极区的超薄绝缘体上硅结构层；
形成在每一个源极/漏极区上的氧化物层；
形成在体区和氧化物区上的栅极绝缘体，该栅极绝缘体能存储大量电荷；以及
形成在栅极绝缘体上的控制栅极。
24、一种形成NROM闪存单元阵列的方法，该方法包括：
在超薄绝缘体上硅结构上形成多个掺杂区，该绝缘体上硅结构具有完全耗尽的体区；
在多个掺杂区的每一个上形成氧化物层；
在掺杂区和完全耗尽的体区上形成栅极绝缘体层；以及
在栅极绝缘体层上形成多晶硅控制栅极。
25、如权利要求24所述方法，其特征在于，形成栅极绝缘体包括形成氧化物—氮化物—氧化物层。
26、如权利要求24所述方法，其特征在于，形成多晶硅控制栅极使得该阵列为或非闪存阵列。
27、如权利要求24所述方法，其特征在于，形成多晶硅控制栅极使得该阵列为与非闪存阵列。
28、一种形成包含多个垂直NROM存储单元的存储阵列的方法，该方法包括：
在衬底中形成第一组多个掺杂，使得每个掺杂区之间存在间隙，掺杂区和衬底电导率类型不同；
在掺杂区之间的间隙上形成氧化物柱；
通过从每个掺杂区沿着氧化物柱的相对侧壁延伸的外延再生长，形成超薄硅体区；
在氧化物柱上和体区上形成多晶硅材料的第二组多个掺杂区，以使柱上的掺杂区电气耦合并具有与第一组多个掺杂区相同的电导率类型；
在第一组多个掺杂区、体区、和第二组多个掺杂区上形成栅极绝缘体层；以及
在临近每个体区的栅极绝缘体上形成多晶硅控制栅极区。
29、如权利要求28所述方法，其特征在于，形成多晶硅控制栅极区包括形成控制栅极作为栅极绝缘体上的连续层。
30、一种形成包含多个垂直NROM存储单元的存储阵列的方法，该方法包括：
在衬底中形成第一组多个掺杂区，掺杂区与衬底有不同的电导率类型；
在每个掺杂区上形成氧化物柱，使每个掺杂区的每一端部延伸超出氧化物柱的相邻侧壁之外；
通过从掺杂区端部并沿着氧化物柱相对侧壁延伸的外延再生长，形成超薄硅体区；
在氧化物柱和体区上形成多晶硅材料的第二组多个掺杂区，使柱上的掺杂区电气耦合并具有与第一组多个掺杂区同样的电导率；
在第一组多个掺杂区、体区、和第二组多个掺杂区上形成栅极绝缘体层，栅极绝缘体层具有与第一组多个掺杂区的某一掺杂区的每个端部相邻的下层，具有比其余下层部分更厚的厚度；以及
在与每一个体区相邻的栅极绝缘体上形成多晶硅控制栅极区。
31、如权利要求30所述的方法，其特征在于，栅极绝缘体层是复合氧化物—氮化物—氧化物层，而所述下层是氧化物层。
32、如权利要求30所述的方法，其特征在于，所述下层是氧化物层。
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US7358562B2 (en) 2008-04-15
US7768058B2 (en) 2010-08-03
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US7915669B2 (en) 2011-03-29
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US20080203467A1 (en) 2008-08-28
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US7244987B2 (en) 2007-07-17
US20050280089A1 (en) 2005-12-22
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