CN1902749A - 具有金属和硅化物栅电极的cmos器件及其制作方法 - Google Patents

具有金属和硅化物栅电极的cmos器件及其制作方法 Download PDF

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CN1902749A
CN1902749A CN200480039412.0A CN200480039412A CN1902749A CN 1902749 A CN1902749 A CN 1902749A CN 200480039412 A CN200480039412 A CN 200480039412A CN 1902749 A CN1902749 A CN 1902749A
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silicide
dielectric layer
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J·K·布拉斯克
M·L·多茨
J·卡瓦利罗斯
M·V·梅茨
C·E·巴恩斯
U·夏
S·达塔
C·D·托马斯
R·S·仇
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Abstract

描述了一种半导体器件以及形成它的方法。该半导体器件包括形成在衬底的第一部分上的金属NMOS栅电极和形成在衬底的第二部分上的硅化物PMOS栅电极。

Description

具有金属和硅化物栅电极的CMOS器件及其制作方法
技术领域
本发明涉及半导体器件，具体地说，涉及具有金属和硅化物栅电极的CMOS器件。
背景技术
具有由二氧化硅制成的很薄的栅极电介质的CMOS器件可能会经历不可接受的栅极漏电流。用某些高k介电材料代替二氧化硅形成栅极电介质可以降低栅极泄漏。然而，由于这种电介质不能与多晶硅兼容，因此已经提出在包括高k栅极电介质的器件中以金属栅电极代替基于多晶硅的栅电极。
尽管金属栅电极可用于形成NMOS和PMOS晶体管，但是如果使用相同材料来制作两种类型的晶体管的金属栅电极，则不可能产生具有最佳功函数的栅电极。有可能通过用第一材料形成NMOS晶体管的金属栅电极并且用第二材料形成PMOS晶体管的金属栅电极来解决这个问题。第一材料可以保证NMOS栅电极的可接受的功函数，而第二材料可保证PMOS栅电极的可接受的功函数。然而，用于形成这种双金属栅极器件的工艺可能是复杂且昂贵的。
具有硅化物栅电极的PMOS晶体管可以显现出可接受的驱动电流和迁移率特性，即使当它的栅极电介质是用很薄的二氧化硅层制作的也是如此。然而，具有硅化物栅电极和很薄的二氧化硅栅极电介质的NMOS晶体管可能不会具有类似的特性。
因此，需要包括NMOS和PMOS晶体管两者的半导体器件，其中PMOS晶体管包括形成在很薄的栅极介电层上的硅化物PMOS电极。需要用于制作这种对两种类型的晶体管都显示出可接受的晶体管性能的CMOS器件的相对廉价且不复杂的工艺。本发明提供这种半导体器件及其制作方法。
附图说明
图1a-1g示出可以在执行用于制作本发明的半导体器件的方法的实施例时形成的结构的截面。
这些图中所示的部件并没有打算按比例绘制。
具体实施方式
描述了半导体器件及其制作方法。该半导体器件包括形成在衬底的第一部分上的金属NMOS栅电极，和形成在衬底的第二部分上的硅化物PMOS栅电极。用于制作该半导体器件的方法的实施例包括在第一栅极介电层上形成的被侧壁隔离物对夹住的第一多晶硅层，以及在第二栅极介电层上形成p型多晶硅层。在除去第一多晶硅层以形成位于侧壁隔离物对之间的沟槽之后，在该沟槽内形成n型金属层，并且基本全部的p型多晶硅层转变成硅化物。
在下面的描述中，阐述了多个细节以提供对本发明的全面理解。然而，对本领域的技术人员来说显然，本发明可以用除了这里明确描述的那些之外的多种方式来实施。由此本发明并不限于下面公开的具体细节。
图1a-1g示出可以在执行用于制作本发明的半导体器件的方法的实施例时形成的结构。图1a示出可以在制作互补型金属氧化物半导体(“CMOS”)时形成的中间结构。该结构包括衬底100的第一部分101和第二部分102。隔离区103使第一部分101与第二部分102分开。第一多晶硅层104形成在第一栅极介电层105上，并且p型多晶硅层106形成在第二栅极介电层107上。第一多晶硅层104被侧壁隔离物对108、109夹住，以及p型多晶硅层106被侧壁隔离物对110、111夹住。电介质112与侧壁隔离物邻近。
衬底100可以包括体硅或绝缘体上硅子结构。或者，衬底100可以包括可以或不可以与硅结合的其它材料，例如锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓、或锑化镓。尽管这里描述了可用以形成衬底100的材料的多个实例，但是可用作形成半导体器件的基础的任何材料都落入本发明的精神和范围之内。
隔离区103可以包括二氧化硅、或其它可以使晶体管的有源区分开的材料。第一栅极介电层105和第二栅极介电层107都可以包括二氧化硅、或其它可以使衬底与栅电极绝缘的材料。介电层105、107优选包括高质量、致密热生长的二氧化硅层，该二氧化硅层厚度小于约20埃，更优选厚度在约5和约10埃之间。第一多晶硅层104和p型多晶硅层106优选厚度均在约100和约2000埃之间，更优选厚度在约500和约1600埃之间。
第一多晶硅层104可以是不掺杂的或掺杂砷、磷或另一种n型材料，而p型多晶硅层106优选掺杂硼。当掺杂硼时，p型多晶硅层106应当包括足够浓度的该元素，以保证随后用于除去第一多晶硅层104的湿法腐蚀工艺将不会除去显著量的p型多晶硅层106。隔离物108、109、110、111优选包括氮化硅，而电介质112可以包括二氧化硅、或低K材料。电介质112可以掺杂磷、硼、或其它元素，并且可以使用高密度等离子体淀积工艺形成。
可以使用常规的工艺步骤、材料、和设备来产生图1a结构，这对本领域的技术人员来说是明显的。如所示，电介质112可以例如通过常规化学机械抛光(“CMP”)操作来背面抛光以暴露第一多晶硅层104和p型多晶硅层106。尽管未示出，但是图1a结构可以包括多个其它部件(例如氮化硅腐蚀停层、源区和漏区、以及一个或多个缓冲层)，它们可以使用常规工艺形成。
当使用常规离子注入和退火工艺形成源区和漏区时，希望在多晶硅层104、106上形成硬掩模并且在该硬掩模上形成腐蚀停层，以便当源区和漏区被硅化物覆盖时保护层104、106。硬掩模可以包括氮化硅，并且腐蚀停层可以包括当应用适当的刻蚀工艺时与氮化硅相比将以显著更低的速率被除去的材料。这种腐蚀停层可以例如由硅、氧化物(例如二氧化硅或二氧化铪)、或碳化物(例如碳化硅)制成。
这种硬掩模和腐蚀停组合可以采用下述方式形成在层104、106上。在构图多晶硅层之前，可以在它上面淀积氮化硅层，其后在该氮化硅层上淀积腐蚀停层。氮化硅层优选厚度在约100和约500埃之间，更优选厚度在约200和约250埃之间。腐蚀停层优选厚度在约200和约1200埃之间，更优选厚度在约400和约600埃之间。在多晶硅层上淀积那些层之后，可以应用常规光刻和刻蚀工艺来构图腐蚀停层和氮化硅层，其将在那些工艺构图层104、106时用作硬掩模。
当介电层112被抛光时，腐蚀停层和氮化硅硬掩模可以从层104、106的表面被抛光，因为这些层在工艺的该阶段之前已经实现了它们的目的。图1a示出在前形成在层104、106上的任何硬掩模或腐蚀停层都已经从那些层的表面除去的结构。如果使用外延生长技术来形成源区和漏区，其没有伴随着硅化物形成，则在构图多晶硅层之前在该多晶硅层上形成这种硬掩模和腐蚀停层可能不是有利的。当使用离子注入工艺来形成源区和漏区时，层104、106可以在注入源区和漏区的同时被掺杂。在这种工艺中，第一多晶硅层104可以特征化为n型多晶硅层。
在形成图1a结构之后，可以除去第一多晶硅层104以产生位于侧壁隔离物108、109之间的沟槽113，形成图1b所示的结构。在除去第一多晶硅层104之后，暴露第一栅极介电层105。在优选实施例中，通过应用对p型多晶硅层106上方的第一多晶硅层104有选择性的湿法腐蚀工艺来除去第一多晶硅层104，以便在不除去显著部分的p型多晶硅层106的情况下除去第一多晶硅层104。
这种湿法腐蚀工艺可以包括在充足的温度下将第一多晶硅层104在包括氢氧化物源的水溶液中暴露充足的时间以基本除去全部层104。该氢氧化物源可以在去离子水中按体积包括在约2％和约30％之间的氢氧化铵或氢氧化四烷基铵，例如氢氧化四甲基铵(“TMAH”)。第一多晶硅层104可以通过将它暴露在溶液中而选择性地除去，其保持在约15℃和约90℃之间(以及优选低于约40℃)的温度，该溶液在去离子水中按体积包括在约2％和约30％之间的氢氧化铵。在该暴露步骤中，优选暴露持续至少一分钟，所希望的是施加在约10KHz和约2000KHz之间的频率下的声能，同时消耗在约1和约10瓦/cm2之间。
在特别优选实施例中，具有约1350埃厚度的第一多晶硅层104可以通过将它在约25℃下在溶液中暴露约30分钟同时施加在约1000KHz的声能(消耗在约5瓦/cm2)来选择性地除去，该溶液在去离子水中按体积包括约15％的氢氧化铵。这种腐蚀工艺应当基本除去了全部n型多晶硅层104，而没有除去有意义的量的p型多晶硅层106。
作为替换，第一多晶硅层104可以通过将它在溶液中暴露至少一分钟同时施加声能来选择性地除去，其保持在约60℃和约90℃之间的温度，该溶液在去离子水中按体积包括在约20％和约30％之间的TMAH。通过将具有约1350埃厚度的第一多晶硅层104在约80℃下在溶液中暴露约2分钟同时施加在约1000KHz的声能(消耗在约5瓦/cm2)来除去该第一多晶硅层104，可以基本上除去全部第一多晶硅层104而不除去显著量的p型多晶硅层106，所述溶液在去离子水中按体积包括约25％的TMAH。
在除去第一多晶硅层104之后，可以保留第一栅极介电层105，其可以包括二氧化硅，其后在层105上形成n型金属层。或者，可以除去第一栅极介电层105，形成图1c结构。当第一栅极介电层105包括二氧化硅时，可以使用对二氧化硅有选择性的刻蚀工艺来除去它。这种刻蚀工艺包括：将层105暴露在溶液中，该溶液在去离子水中包括约1％的HF，或者应用干法刻蚀工艺，该干法刻蚀工艺采用基于碳氟化合物的等离子体。层105的暴露时间应当受到限制，因为用于除去层105的刻蚀工艺也可以除去部分介电层112。考虑到上述原因，如果使用基于1％的HF的溶液来除去层105，则器件优选应当在该溶液中暴露少于约60秒，更优选约30秒或更少。
当除去第一栅极介电层105时，在沟槽113内形成n型金属层之前必须代替它。优选地，在已经除去第一栅极介电层105之后，在沟槽113底部的衬底100上形成高k栅极介电层114，产生图1d所示的结构。可用于制作高k栅极电介质114的一些材料包括：氧化铪、铪硅氧化物、氧化镧、氧化锆、锆硅氧化物、氧化钽、钡锶钛氧化物、钡钛氧化物、锶钛氧化物、氧化钇、氧化铝、铅钪钽氧化物、和铅锌铌酸盐。特别优选的是氧化铪、氧化锆、和氧化铝。尽管这里描述了可用于形成高k栅极介电层114的材料的多个实例，但是该层可以用其它材料来制作。
高k栅极介电层114可以使用诸如常规化学汽相淀积(“CVD”)、低压CVD、或物理汽相淀积(“PVD”)工艺之类的常规淀积方法形成在衬底100上。优选地，使用常规原子层CVD工艺。在这种工艺中，金属氧化物前驱(例如金属氯化物)和蒸汽可以以所选的流速馈送到CVD反应器中，其接着在所选的温度和压力下运行以在衬底100和高k栅极介电层114之间产生原子平滑的界面。CVD反应器应当运行足够长时间以形成具有所需厚度的层。在大多数应用中，高k栅极介电层114厚度应当小于约60埃，更优选厚度在约5埃和约40埃之间。
尽管未在图1d中示出，但是如果使用原子层CVD工艺来形成高k栅极介电层114，则该层除了形成在沟槽113的底部上之外还可以形成在该沟槽的侧上。如果高k栅极介电层114包括氧化物，则它可以根据用于制作它的工艺显现出在随机表面位置的氧空位和不可接受的杂质水平。所希望的是在淀积层114之后，从层114除去某些杂质，并且氧化它以产生具有接近理想化的金属∶氧化学计量法的层。
在高k栅极介电层114形成在衬底100上之后，在该实施例中，n型金属层115形成在沟槽113内和高k栅极介电层114上，形成图1e结构。N型金属层115可以包括任何n型导电材料，由该导电材料可以得到金属NMOS栅电极。N型金属层115优选具有热稳定特性，该特性使得它适于制作半导体器件的金属NMOS栅电极。
可用于形成n型金属层115的材料包括：铪、锆、钛、钽、铝，以及它们的合金，例如包括这些元素的金属碳化物，即碳化铪、碳化锆、碳化钛、碳化钽、和碳化铝。N型金属层115可以使用诸如常规溅射或原子层CVD工艺之类的公知PVD或CVD工艺形成在高k介电层114上。如所示，n型金属层115除了它填充沟槽113的地方都被除去。层115可以通过湿法或干法刻蚀工艺或适当的CMP操作从器件的其它部分除去。当将层115从其表面除去时，电介质112可以用作腐蚀或抛光停。
N型金属层115优选用作金属NMOS栅电极，其具有在约3.9eV和约4.2eV之间的功函数，并且其厚度在约100埃和约2000埃之间，更优选厚度在约500埃和约1600埃。尽管图1e示出n型金属层115填充全部沟槽113的结构，但是在替换实施例中，n型金属层115可以仅填充部分沟槽113，并且沟槽的剩余部分用可以易于抛光的材料例如钨或铝来填充。在这种替换实施例中，用作功函数金属的n型金属层115厚度可以在约50和约1000埃之间，更优选厚度是至少约100埃。在沟槽113包括功函数金属和沟槽填充金属两者的实施例中，所得到的金属NMOS栅电极可以被认为包括功函数金属和沟槽填充金属两者的结合。
在所示实施例中，在沟槽113内形成n型金属层115之后，基本全部的p型多晶硅层106(优选是该层全部)转变成硅化物116，如图1f所示。硅化物116可以包括硅化镍、硅化钴、硅化钛、那些材料的组合、或可以形成高性能硅化物PMOS栅电极的任何其它类型的硅化物。P型多晶硅层106可以通过如下操作转变成硅化物116：在整个结构上方淀积适当的金属，然后施加足够时间的足够温度的热以从p型多晶硅层106产生金属硅化物(例如NiSi)。
在优选实施例中，硅化物116通过首先在包括层106的暴露表面的整个结构上方溅射适当的金属(例如镍)形成。为了使硅化物116完全延伸通过p型多晶硅层106，有必要在溅射操作后进行高温退火，例如在至少约450℃的温度下进行的快速热退火。当形成硅化镍时，退火优选在约500℃和约550℃之间的温度下进行。当形成硅化钴时，退火优选在至少约600℃的温度下进行。
在形成硅化物116之后，可以应用常规湿法腐蚀或干法刻蚀工艺、或常规CMP步骤来从该结构除去多余金属，电介质112用作腐蚀或抛光停。硅化物116可以用作具有在约4.3eV和约4.8eV之间的中间隙(midgap)功函数的硅化物PMOS栅电极，并且其厚度在约100埃和约2000埃之间，更优选厚度在约500埃和约1600埃之间。
尽管这里描述了可用于形成n型金属层115和硅化物116的材料的多个实例，但是该金属层和该硅化物可用多种其它材料制作，这对本领域的技术人员来说是明显的。在形成硅化物116之后，覆盖介电层117可以淀积在介电层112、金属NMOS栅电极118、和硅化物PMOS栅电极119上，形成图1g结构。覆盖介电层117可以使用任何常规淀积工艺来淀积。淀积覆盖介电层117之后完成器件的工艺步骤，例如形成器件的触点、金属互连、和钝化层是本领域的技术人员公知的，并且这里将不再描述。
尽管所示实施例用高k栅极介电层114代替了第一栅极介电层105，但是在替换实施例中，可以保留第一栅极介电层105，其可以包括二氧化硅，并且n型金属层115可以直接形成在层105上。上述方法能够形成包括金属NMOS栅电极和硅化物PMOS栅电极的CMOS器件，而不必执行相对复杂且成本高的工艺步骤。尽管上述实施例提供了用于形成这类器件的工艺的实例，但是本发明并不限于这些具体实施例。
图1g的半导体器件包括形成在衬底100的第一部分101上的金属NMOS栅电极118、和形成在衬底100的第二部分102上的硅化物PMOS栅电极119。如上所示，金属NMOS栅电极118可以完全由一种或多种上述n型金属构成，或者，可以包括被沟槽填充金属覆盖的n型功函数金属。如上所述，衬底100的第一部分101可以包括高k栅极介电层114，而衬底100的第二部分102包括第二栅极介电层107。金属NMOS栅电极118优选厚度在约100和约2000埃之间，具有在约3.9eV和约4.2eV之间的功函数，并包括一种或多种上述n型材料。硅化物PMOS栅电极119优选厚度在约100和约2000埃之间，具有在约4.3eV和约4.8eV之间的中间隙功函数，并包括上述硅化物中的一种。
高k栅极介电层114可以包括一种或多种上述材料，而第二栅极介电层107可以包括二氧化硅。或者，当在除去第一多晶硅层104之后不用高k栅极介电层114代替第一栅极介电层105时，衬底100的第一部分101可以替代地包括第一栅极介电层105，并且第一栅极介电层105和第二栅极介电层107每一个都包括二氧化硅。
尽管本发明的半导体器件可以使用以上详细阐述的工艺来制作，但是它可以替换地使用其它类型的工艺形成。为此，该半导体器件并没有打算受限于可以使用上述工艺制作的器件。尽管前面的描述已经指定了可用在本发明中的特定步骤和材料，但是本领域的技术人员应当理解，可以进行多种修改和替换。因此，目的是这些修改、变型、替换和添加应当被认为落入由所附权利要求限定的本发明的精神和范围之内。

Claims (20)

1.一种用于制作半导体器件的方法，包括：
在衬底的第一部分上形成金属NMOS栅电极；以及
在衬底的第二部分上形成硅化物PMOS栅电极。
2.权利要求1的方法，其中衬底的第一部分包括第一栅极介电层，以及衬底的第二部分包括第二栅极介电层。
3.权利要求2的方法，其中第一栅极介电层和第二栅极介电层均包括二氧化硅。
4.权利要求2的方法，其中第一栅极介电层包括高k栅极介电层，以及第二栅极介电层包括二氧化硅。
5.权利要求4的方法，其中高k栅极介电层通过原子层化学汽相淀积形成，并包括从包括下述材料组中选择的材料：氧化铪、铪硅氧化物、氧化镧、氧化锆、锆硅氧化物、氧化钽、钡锶钛氧化物、钡钛氧化物、锶钛氧化物、氧化钇、氧化铝、铅钪钽氧化物、和铅锌铌酸盐。
6.权利要求1的方法，其中金属NMOS栅电极包括从包括铪、锆、钛、钽、铝、和金属碳化物的组中选择的材料。
7.权利要求1的方法，其中硅化物PMOS栅电极包括从包括硅化镍、硅化钴、和硅化钛的组中选择的材料。
8.权利要求1的方法，其中金属NMOS栅电极具有在约3.9eV和约4.2eV之间的功函数，以及硅化物PMOS栅电极具有在约4.3eV和约4.8eV之间的中间隙功函数。
9.一种制作半导体器件的方法，包括：
在第一栅极介电层上形成被侧壁隔离物对夹住的第一多晶硅层，以及在第二栅极介电层上形成p型多晶硅层；
除去第一多晶硅层以形成位于侧壁隔离物对之间的沟槽；
在沟槽内形成n型金属层；以及
将基本全部的p型多晶硅层转变成硅化物。
10.权利要求9的方法，其中第一栅极介电层和第二栅极介电层每一个包括二氧化硅，并且其中第一多晶硅层和p型多晶硅层每一个厚度在约100和约2000埃之间。
11.权利要求9的方法，其中应用对p型多晶硅层上方的第一多晶硅层有选择性的湿法腐蚀工艺来除去第一多晶硅层。
12.权利要求9的方法，其中n型金属层包括从包括铪、锆、钛、钽、铝、和金属碳化物的组中选择的材料，以及其中全部p型多晶硅层转变成硅化物。
13.一种制作半导体器件的方法，包括：
在第一栅极介电层上形成被侧壁隔离物对夹住的n型多晶硅层，以及在第二栅极介电层上形成p型多晶硅层；
应用对p型多晶硅层上方的n型多晶硅层有选择性的湿法腐蚀工艺来除去n型多晶硅层而没有除去显著部分的p型多晶硅层，产生位于侧壁隔离物对之间的沟槽，以及暴露第一栅极介电层；
除去暴露的第一栅极介电层；
在沟槽底部的衬底上形成高k栅极介电层；
在高k栅极介电层上形成n型金属层以产生金属NMOS栅电极；以及
将p型多晶硅层转变成硅化物以产生硅化物PMOS栅电极。
14.权利要求13的方法，其中：
高k栅极介电层通过原子层化学汽相淀积形成，并包括从包括下述材料组中选择的材料：氧化铪、铪硅氧化物、氧化镧、氧化锆、锆硅氧化物、氧化钽、钡锶钛氧化物、钡钛氧化物、锶钛氧化物、氧化钇、氧化铝、铅钪钽氧化物、和铅锌铌酸盐；
n型金属层包括从包括铪、锆、钛、钽、铝、和金属碳化物的组中选择的材料；以及
硅化物包括从包括硅化镍、硅化钴、和硅化钛的组中选择的材料。
15.权利要求13的方法，其中湿法腐蚀工艺包括将n型多晶硅层暴露在水溶液中，该水溶液按体积包括在约2％和约30％之间的氢氧化物源。
16.权利要求15的方法，其中氢氧化物源包括从包括氢氧化铵和氢氧化四甲基铵的组中选择的化合物。
17.一种半导体器件，包括：
形成在衬底的第一部分上的金属NMOS栅电极；和
形成在衬底的第二部分上的硅化物PMOS栅电极。
18.权利要求17的半导体器件，其中：
衬底的第一部分包括第一栅极介电层，以及衬底的第二部分包括第二栅极介电层；
金属NMOS栅电极厚度在约100和约2000埃之间，具有在约3.9eV和约4.2eV之间的功函数，并包括从包括铪、锆、钛、钽、铝、和金属碳化物的组中选择的材料；以及
硅化物PMOS栅电极厚度在约100和约2000埃之间，具有在约4.3eV和约4.8eV之间的中间隙功函数，并包括从包括硅化镍、硅化钴、和硅化钛的组中选择的材料。
19.权利要求18的方法，其中第一栅极介电层和第二栅极介电层每一个包括二氧化硅。
20.权利要求18的方法，其中第二栅极介电层包括二氧化硅，以及第一栅极介电层是高k栅极介电层，该高k栅极介电层包括从包括下述材料组中选择的材料：氧化铪、铪硅氧化物、氧化镧、氧化锆、锆硅氧化物、氧化钽、钡锶钛氧化物、钡钛氧化物、锶钛氧化物、氧化钇、氧化铝、铅钪钽氧化物、和铅锌铌酸盐。
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