CN1930669A - 改善低k电介质粘附性的等离子体处理方法 - Google Patents
改善低k电介质粘附性的等离子体处理方法 Download PDFInfo
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- CN1930669A CN1930669A CNA2005800080664A CN200580008066A CN1930669A CN 1930669 A CN1930669 A CN 1930669A CN A2005800080664 A CNA2005800080664 A CN A2005800080664A CN 200580008066 A CN200580008066 A CN 200580008066A CN 1930669 A CN1930669 A CN 1930669A
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- oxidizing gas
- silicon compound
- silicon
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Classifications
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/02—Pretreatment of the material to be coated
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31633—Deposition of carbon doped silicon oxide, e.g. SiOC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/32—Carbides
- C23C16/325—Silicon carbide
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/401—Oxides containing silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32174—Circuits specially adapted for controlling the RF discharge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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Abstract
本发明提供了在两个低k电介质层之间沉积具有低介电常数的粘附层而对衬底进行处理的方法。在一个方面,本发明提供了处理衬底的方法,该方法包括:以有机硅化合物与氧化气体的第一比率将有机硅化合物和氧化气体引入处理室;生成氧化气体与有机硅化合物的等离子,以在包含至少硅和碳的阻挡层上形成初始层;以大于有机硅化合物与氧化气体的第一比率的第二比率将有机硅化合物和氧化气体引入处理室;沉积相邻于电介质初始层的第一电介质层。
Description
技术领域
本发明涉及集成电路的制造,还涉及在衬底上沉积电介质层的工艺以及由该电介质层形成的结构。
背景技术
制造现代半导体器件的主要步骤之一是通过气体化学反应在衬底上形成金属层和电介质层。这样的沉积工艺被称为化学气相沉积或CVD。传统的热CVD工艺将反应性气体供给至发生热致化学反应的衬底表面,从而形成期望的层。
自从半导体器件数十年前问世以来,其几何尺寸显著减小。因此,集成电路通常遵循两年/尺寸减半的规律(通常称为摩尔定律),即芯片上装有的器件数量每两年翻一倍。现今的制造工厂一般生产特征尺寸为0.35μm甚至0.18μm的器件,而今后的工厂很快将生产几何尺寸更小的器件。
为了进一步减小集成电路上器件的尺寸,使用具有低电阻率的导电材料已成为必须,而且还使用具有低介电常数(介电常数<4.0)的绝缘体来降低相邻金属线之间的电容耦合。一种这样的低k电介质材料是旋涂玻璃,例如未掺杂的硅玻璃(USG)或掺杂氟的硅玻璃(FSG),其可在半导体制造工艺中作为填隙层被沉积。另一种低k电介质材料是可在镶嵌特征的制造中用作电介质层的硅的碳氧化物。
一种可接受的导电材料是铜及其合金,其已成为次四分之一微米级互连技术所选择的材料,原因在于铜与铝相比具有更低的电阻率(1.7μΩ-com,而铝为3.1μΩ-com)、更高的电流和更高的载流量。这些特性对于实现高集成度下的较高电流密度以及提高器件速度来说是重要的。此外,铜具有良好的导热性并且可以以十分纯的状态获得。
在半导体器件中使用铜的一个困难是难以对铜进行蚀刻来得到精确的图案。采用传统的形成互连的沉积/蚀刻工艺来蚀刻铜,已经不能令人满意。因此,正在开发制造具有含铜材料和低k电介质材料的互连的新方法。
一种形成垂直和水平互连的方法是通过镶嵌或双镶嵌方法。在镶嵌方法中,一种或多种电介质材料(例如低k电介质材料)被沉积与图案化蚀刻以形成垂直互连(即,过孔)和水平互连(即,线)。然后将导电材料(例如含铜材料)和其他材料(例如用于防止含铜材料扩散进入周围的低k电介质的阻挡层材料)镶嵌在已蚀刻的图案中。然后,去除已蚀刻图案外部(例如衬底表面上)的过量含铜材料和过量阻挡层材料。
然而,当硅氧碳化物层和硅碳化物层被用作镶嵌形成中的低k材料时,在处理过程中发现层间粘附性无法满足要求。某些处理衬底的技术可能施加可增加涂层缺陷(例如层离)的力。例如,在化学机械抛光工艺中,可通过衬底与抛光垫之间的机械研磨来去除过量的含铜材料,并且衬底与抛光垫之间的力可在沉积的低k电介质材料中产生应力,从而导致层离。在另一个实施例中,沉积材料的退火可使低k电介质材料中产生也可造成层离的高热应力。
因此,需要一种改善低k电介质层之间的层间粘附性的工艺。
发明内容
本发明一般性地提供在两个低k电介质层之间沉积具有低介电常数的粘附层的方法。在一个方面,本发明提供处理衬底的方法,该方法包括:将衬底置于处理室中,其中衬底具有包含至少硅和碳的阻挡层;以有机硅化合物与氧化气体的第一比率将有机硅化合物和氧化气体引入处理室;生成氧化气体与有机硅化合物的等离子以在阻挡层上形成初始层;以大于第一比率的有机硅化合物与氧化气体的第二比率将有机硅化合物和氧化气体引入处理室;沉积相邻于电介质初始层的第一电介质层,其中电介质层包含硅、氧和碳并且具有约3或更小的介电常数。
本发明的另一方面提供了处理衬底的方法,该方法包括:将衬底置于处理室中,其中衬底具有包含至少硅和碳的阻挡层;将惰性气体引入处理室中;由单频RF功率源生成第一等离子体以对阻挡层的表面进行改性;以约1∶1的比率将有机硅化合物与氧化气体引入处理室;由双频RF功率源生成第二等离子体以在阻挡层上形成初始层;以大于约10∶1的比率将有机硅化合物与氧化气体引入处理室;沉积相邻于电介质初始层的第一电介质层,其中电介质层包含硅、氧和碳并且具有约3或更小的介电常数。
本发明的另一方面提供了处理衬底的方法,该方法包括:将衬底置于处理室中,其中衬底具有包含至少硅和碳的阻挡层;将氧化气体引入处理室;生成氧化气体的等离子体并且处理阻挡层表面;以第一流率引入有机硅化合物;由氧化气体和有机硅化合物在阻挡层上沉积初始层;以大于第一流率的第二流率引入有机硅化合物;由氧化气体和有机硅化合物沉积相邻于电介质初始层的第一电介质层,其中电介质层包含硅、氧和碳并且具有约3或更小的介电常数。
本发明的另一方面提供了处理衬底的方法,该方法包括:将衬底置于处理室中,其中衬底具有包含至少硅和碳的阻挡层;将氧化气体引入处理室;生成氧化气体的等离子体并且在阻挡层上形成初始层;将有机硅化合物引入处理室;使有机硅化合物与氧化气体反应;沉积相邻于电介质初始层的第一电介质层相邻于电介质初始层,其中电介质层包含硅、氧和碳并且具有约3或更小的介电常数。
附图说明
为了实现上述本发明的各个方面以及详细理解本发明,以下通过参考附图所示的实施方式对本发明进行更具体的描述。
然而应当注意到,附图仅说明了本发明的典型实施方式,因而不应看作是对其范围的限制,本发明可容许其他等同有效的实施方式。
图1为包括本文所述的硅碳化物和硅氧碳化物层的双镶嵌结构的剖面图;
图2A-2H为本发明的双镶嵌沉积工序的一种实施方式的剖面图。
为了更好地理解本发明的方面,参考应保证详细的说明。
具体实施方式
本文所述的本发明的方面是指沉积粘附性电介质材料和/或处理电介质层之间的表面以改善电介质层的粘附性的方法与装置。提高层间粘附性可包括在沉积后续电介质层之前形成电介质初始层。该初始层可包含硅、碳并且可选地包含氧。提高电介质层之间的粘附性的处理包括在后续沉积之前对已沉积的层的表面进行改性,例如,采用惰性气体、氧化气体或二者的等离子体处理。对含硅、碳以及可选地含氧的材料的表面进行处理被认为在沉积材料表面上形成更类似氧化物的表面,从而提高层间粘附性。
双镶嵌结构的沉积
图1示出了采用本文所述的在硅碳化物层上布置硅氧碳化物层的沉积工艺所形成的镶嵌结构。图1和图2A-2H所示的以下结构形成工艺是示例性的,不应被理解或解释为对本发明范围的限制。尽管下述层间粘附工艺是在硅碳化物阻挡层112与电介质层110之间以及低k蚀刻终止层114与层间电介质层118之间使用,但是本发明还可在镶嵌结构或电介质叠层中的任何合适的电介质层之间使用层间粘附工艺。
具有在衬底表面材料105中形成的金属特征107的衬底100被供给至处理室。通常,在衬底表面上沉积第一硅碳化物阻挡层112,以消除衬底与后续沉积材料之间的层间扩散。第一硅碳化物阻挡层112可掺杂氮和/或氧。阻挡层材料的介电常数可达约9,例如4或更小,优选在约2.5与小于约4之间。硅碳化物阻挡层的介电常数可为约5或更小,优选小于约4。通过最小化或排除氮源气体,可在第一硅碳化物阻挡层112上原位沉积无氮硅碳化物覆层(未示出)。可在第一硅碳化物阻挡层112上沉积初始层113,而且在沉积初始层113之前,可使用本文所述的预处理工艺。
氧化有机硅化合物的第一电介质层110被沉积在初始层113上。然后,可用等离子体或电子束工艺对第一电介质层110进行后处理。或者,通过提高本文所述的硅氧碳化物沉积工艺中的氧浓度,可在第一电介质层110上原位沉积硅氧化物覆层(未示出),从而去除沉积材料中的碳。
然后在第一电介质层110上沉积硅碳化物的蚀刻终止层(或第二阻挡层)114(其可掺杂氮或氧)。可在蚀刻终止层114上沉积无氮硅碳化物覆层。然后,对蚀刻终止层114进行图案化蚀刻以定义接触/过孔116的开口。在后续处理(例如蚀刻或附加的电介质蚀刻)之前,可在层114上形成本文所述的层间粘附层或初始层115,以改善随后沉积的电介质材料的层间粘附。改善的粘附层可包括本文所述的预处理工艺和初始层。可通过本文所述的技术来形成层间粘附表面。然后,在图案化的蚀刻终止层上沉积氧化有机硅烷或有机硅氧烷的第二电介质层118。然后,可对第二电介质层118进行等离子体或电子束处理和/或具有用本文所述的工艺布置于其上的硅氧化物覆盖材料。
然后,通过本领域已知的传统方法来沉积和图案化本领域通常已知的抗蚀剂层122(例如光阻材料UV-5,可从Massachusetts,Marlborough的Shipley Company Inc.购得),从而定义互连线120。然后进行单个蚀刻工艺来定义下至蚀刻终止层的互连,并且蚀刻由图案化的蚀刻终止层暴露的未保护的电介质以定义接触/过孔。
如图2E所示,根据本发明制造的优选的双镶嵌结构包括等离子体处理或电子束处理暴露的硅氧碳化物层,制造该结构的方法依次示于图2A-2H,这些图是用本发明的工艺步骤进行处理的衬底的剖面图。
如图2A所示,第一硅碳化物阻挡层112被沉积在衬底表面上。第一硅碳化物阻挡层112的硅碳化物材料可掺杂氮和/或氧。尽管并未示出,但可在阻挡层112上沉积无氮硅碳化物或硅氧化物的覆层。通过调节处理气体的组成,可在原位沉积无氮硅碳化物或硅氧化物。
通过等离子体处理第一硅碳化物阻挡层112,随后沉积实际的初始层材料,可以沉积初始层113;以上两个工艺可在原位顺序进行。氦(He)、氩(Ar)、氖(Ne)及其组合可被用于等离子体处理。
惰性气体预处理工艺的实例包括:以约1500sccm的流率向处理室提供氦;保持室压力为约5Torr;保持衬底温度为约350℃;在距衬底表面约450密耳处设置气体分布器;通过在约13.56MHz的高频下施加15秒的约300W的RF功率水平来生成等离子体。
沉积初始层113的实例包括:以500sccm的流率将氧引入处理室;以约500毫克/分钟(mgm)(相当于约39sccm的OMCTS)的流率引入八甲基环四硅氧烷;以约4800sccm的流率引入氦;保持室处于约350℃的衬底温度下;保持室压力为约5Torr;在距衬底表面约350密耳处设置气体分布器;在13.56MHz下施加约500W、在356KHz下施加约150W的RF功率。
通过本文所述的工艺,在初始层113上沉积来自氧化有机硅烷或有机硅氧烷(例如三甲基硅烷和/或八甲基环四硅氧烷)的硅氧碳化物的初始第一电介质层110,依赖于制造的结构尺寸,沉积厚度为约5000至约15000。第一电介质层还可包含其他低k电介质材料,例如低聚物材料(包括paralyne)或低k旋涂玻璃,如未掺杂的硅玻璃(USG)或氟掺杂的硅玻璃(FSG)。然后,可用本文所述的等离子体工艺来处理第一电介质层。
如图2B所示,然后在第一电介质层上沉积可为氮和/或氧掺杂的硅碳化物的低k蚀刻终止层114,沉积厚度约100至约1000。然后,在低k蚀刻终止层114上形成或沉积由本文所述的工艺之一所形成的层间电介质粘附层或表面115(例如电介质初始层)。通过本文所述的用于硅碳化物材料或硅氧碳化物材料的方法,对低k蚀刻终止层114和/或层间电介质粘附层或表面115进行等离子体处理。可如沉积初始层113所述来沉积层115。
然后,如图2C所示,图案化蚀刻低k蚀刻终止层114以定义接触/过孔开口116,并且在要形成接触/过孔的区域暴露第一电介质层110。优选地,通过使用氟、碳和氧离子的常规光刻和蚀刻工艺来对低k蚀刻终止层114进行图案化蚀刻。尽管并未示出,但是在沉积其他材料之前,可在低k蚀刻终止层114和/或层间电介质粘附层或表面115上沉积约100至约500的无氮硅碳化物或硅氧化物覆层。
如图2D所示,在蚀刻低k蚀刻终止层114以图案化接触/过孔以及去除抗蚀剂材料之后,通过本文所述的工艺来沉积来自氧化有机硅烷或有机硅氧烷(例如三甲基硅烷)的硅氧碳化物的第二电介质层118,沉积厚度为约5000至约15000。然后,可通过如处理第一电介质层110所述的等离子体工艺来处理第二电介质层118。
然后,如图2E所示,优选使用传统的光刻工艺在第二电介质层118(或覆层)上沉积抗蚀剂材料122并图案化以定义互连线120。抗蚀剂材料122包括现有技术公知的材料,优选为高活化能的抗蚀剂材料,例如UV-5(可从Massachusetts,Marlborough的Shipley Company Inc.购得)。然后,如图2F所示,用反应性离子蚀刻或其他各向异性蚀刻技术来蚀刻互连和接触/过孔,从而定义金属化结构(即,互连和接触/过孔)。使用氧剥离或其他合适的工艺来去除所有的用于图案化蚀刻终止层114或第二电介质层118的抗蚀剂材料或其他材料。
因此,形成了具有导电材料的金属化结构,导电材料例如是铝、铜、钨或其组合。由于铜的电阻率低(1.7mΩ-cm,而铝为3.1mΩ-cm),目前的趋势是使用铜来形成更小的特征。优选地,如图2G所示,合适的金属阻挡层124(例如钽氮化物)首先被保形沉积在金属化图案中,以防止铜迁移进入周围的硅和/或电介质材料中。此后,使用化学气相沉积、物理气相沉积、电镀中的任何一种或其组合来沉积铜126以形成导电结构。如图2H所示,一旦此结构被铜或其他导电金属填充,则使用化学机械抛光对其表面进行平坦化。
初始层沉积
在一个方面,可通过在沉积硅氧碳化物层之前沉积初始层来改善层间粘附。可选地,在沉积初始层之前,可以对其下方的电介质层(例如硅碳化物或掺杂的硅碳化物)进行预处理工艺。在气体在预处理步骤和/或沉积步骤之间的转换时,可以不停止施加生成等离子体的RF功率。
以下描述的沉积工艺采用300mm ProducerTM双沉积台处理室,应当作相应的解释,例如,流率是指总流率,而当描述室内的每个沉积站的流率时,应当将流率除以2。此外,应当注意,为了在不同的室中以及对于不同的衬底尺寸(例如200mm)进行等离子体工艺,可以对各个参数进行调整。
本文所述的沉积工艺可以作为一个连续的等离子体工艺来进行,或者包括两个或多个生成的等离子体,例如,每个层沉积步骤均有一个生成的等离子体。本文所述的预处理和沉积工艺可以作为一个连续的等离子体工艺来进行,或者包括两个或更多个生成的等离子体,例如,一个生成的等离子体用于预处理工艺,一个和多个生成的等离子体用于层沉积步骤;或者一个等离子体用于预处理工艺和初始层沉积步骤,第二生成的等离子体用于电介质沉积步骤。
预处理工艺包括用惰性气体、氧化气体或二者对下方的电介质进行等离子体处理。等离子体处理可形成更类似于后续沉积材料的下方电介质材料的表面。例如,氧等离子体可产生更类似氧化物的表面。等离子体处理可在与用于沉积硅氧碳化物材料相同的室中进行。
等离子体处理的一种实施方式包括:以约500sccm至约3000sccm的流率向处理室提供惰性气体,其包括氦、氩、氖、氙、氪或其组合;保持室压力为约3Torr至约12Torr;保持衬底温度为约300℃至约450℃;设置气体分布器或“喷淋头”,其可位于距衬底表面约200密耳至约1000密耳(例如300密耳至500密耳)的位置;通过在高频(例如约13MHz至约14MHz,如13.56MHZ)下施加约0.03W/cm2至约3.2W/cm2的功率密度(对于200mm的衬底,相当于约10W至约1000W的RF功率水平)来生成等离子体。等离子体处理可进行约3秒至约120秒,例如,优选使用约5秒至约40秒。
可通过双频RF功率源来生成等离子体。或者,所有的等离子体生成可远程进行,而将生成的基引入处理室,用于已沉积的材料的等离子体处理或材料层的沉积。
惰性气体预处理工艺的实例包括:已约1500sccm的流率向处理室提供氦;保持室压力为约5Torr;保持衬底温度为约350℃;在距衬底表面约450密耳处设置气体分布器;通过在约13.56MHz的高频下施加15秒的约300W的RF功率水平来生成等离子体。
等离子体预处理工艺可使用氧化气体(例如氧),可以使用或不使用上述惰性气体。氧化预处理工艺可包括:以约100sccm至约3000sccm的流率向处理室提供氧化气体(例如本文所述的氧或其它氧化气体);保持室压力为约2Torr至约12Torr;保持衬底温度为约250℃至约450℃;设置气体分布器或“喷淋头”,其可位于距衬底表面约200密耳至约1000密耳(例如300密耳至500密耳)的位置;通过在高频(例如约13MHz至约14MHz,如13.56MHZ)下施加约0.03W/cm2至约3.2W/cm2的功率密度(对于200mm的衬底,相当于约10W至约1000W的RF功率水平)来生成等离子体。等离子体处理可进行约3秒至约120秒,优选使用约5秒至约40秒的等离子体处理。
氧化气体预处理工艺的实例包括:以约750sccm(对于双台ProducerTM等离子体室,为约1500sccm)的流率向处理室提供氧;保持室压力为约5Torr;保持衬底温度为约350℃;在距衬底表面约450密耳处设置气体分布器;通过在约13.56MHz的高频下施加15秒的约300W的RF功率水平来生成等离子体。
可在下方材料(例如可包括氮或氧掺杂的硅碳化物)上沉积初始层以便于沉积后续的电介质层(例如硅氧碳化物层)。
初始层可包括硅氧碳化物层,并可由氧化气体和有机硅材料沉积,其中有机硅化合物如这里所述的化合物。引入处理室的有机硅化合物(mgm)与氧化气体(sccm)的比率可为约1∶2至约10∶1,例如约1∶2至约2∶1,如约1∶2至约1∶1。可在与后续的电介质材料沉积(例如硅氧碳化物沉积)相近或相同的处理条件下沉积初始层。
通过调整处理气体的组成,可在原位顺序沉积初始层和硅氧碳化物层。例如,可通过以约10∶1或更大(例如约10∶1至约20∶1,如约18∶1)的有机硅化合物(mgm)与氧化气体(sccm)的比率将有机硅化合物与氧化气体引入处理室;以及通过在初始层沉积与硅氧碳化物层沉积之间改变有机硅化合物与氧化气体的比率,可使处理在原位发生。氧化气体可包括选自氧、臭氧、一氧化碳、二氧化碳、氧化亚氮及其组合的氧化化合物,其中氧是优选的。
预处理工艺也可在初始层沉积和/或硅氧碳化物层沉积原位进行。除非另有说明,用于沉积工艺的有机硅化合物与氧化气体的所有的流量比率均以mgm/sccm的单位描述。
一种沉积电介质初始层的实施方式如下所述。该沉积可通过以下方法进行:以约10sccm至约2000sccm的流率将氧化化合物引入处理室;以约100毫克/分钟(mgm)至约5000mgm(对于八甲基环四硅氧烷(OMCTS),相当于约7sccm至约400sccm)的流率引入有机硅前体,并且可选地,以约1sccm至约10000sccm的流率供给惰性气体;保持室处于约0℃至约500℃的衬底温度;保持室压力为约100mTorr至约100Torr;在距衬底表面约200密耳至约700密耳处设置气体分布器;施加约0.03W/cm2至约1500W/cm2的RF功率,例如约0.03W/cm2至约6.4W/cm2,对于200mm的衬底,施加约10W至约2000W的RF功率水平。
可由双频RF功率源施加第一RF功率和至少第二RF功率,其中,第一RF功率的频率范围为约10MHz至约30MHz,功率范围为约200W至约1000W;第二PF功率的频率范围为约100KHz至约500KHz,功率范围为约1W至约200W。沉积初始层的时间可为约1秒至约60秒,例如约1秒至约5秒,如2秒。
沉积初始层的实例包括:以约500sccm的流率将氧引入处理室;以约500毫克/分钟(mgm)(对于OMCTS,相当于约39sccm)的流率引入八甲基环四硅氧烷;以约4800sccm的流率引入氦;保持室处于约350℃的衬底温度;保持室压力为约5Torr;在距衬底表面约350密耳处设置气体分布器;在13.56MHz下施加约500W、在356KHz下施加约150W的RF功率。此工艺进行约1秒至约5秒,优选约2秒。
在形成初始层的另一种实施方式中,氧等离子体预处理工艺可开始并进行第一时间长度,然后引入有机硅材料,用于沉积初始层。在后续电介质材料沉积(也可原位进行)之前,这允许不间断的氧化等离子体对沉积材料的预处理和后续的初始层沉积。
在一种实施方式中,电介质材料可包括通过以下方法沉积的硅氧碳化物:以约10sccm至约2000sccm的流率将氧化化合物(诸如氧气)引入处理室;以约100毫克/分钟(mgm)至约5000mgm(对于OMCTS,相当于约7sccm至约400sccm)的流率引入有机硅前体,并且可选地,以约1sccm至约10000sccm的流率供给惰性气体;保持室处于约0℃至约500℃的衬底温度;保持室压力为约100mTorr至约100Torr;在距衬底表面约200密耳至约700密耳处设置气体分布器;施加约0.03W/cm2至约1500W/cm2的RF功率(例如约0.03W/cm2至约6.4W/cm2,对于200mm的衬底来说约10W至约2000W的RF功率水平)。可由双频RF功率源施加第一RF功率和至少第二RF功率,其中,第一RF功率的频率范围为约10MHz至约30MHz,功率范围为约200W至约1000W;第二PF功率的频率范围为约100KHz至约500KHz,功率范围为约1W至约200W。
沉积电介质层的实例包括:以160sccm的流率将氧引入处理室;以约2900毫克/分钟(mgm)(对于OMCTS,相当于约226sccm)的流率引入八甲基环四硅氧烷;以约1000sccm的流率引入氦;保持室处于约350℃的衬底温度;保持室压力为约5Torr;在距衬底表面约450密耳处设置气体分布器;在13.56MHz下施加约500W、在356KHz下施加约150W的RF功率。通过调节前体流率和其它处理参数,初始层沉积工艺以及电介质层的沉积可以在原位且连续进行。
实施例
下面的实施例说明了本发明的粘附工艺的各种实施方式,与标准的层积相比,本发明可改善层间粘附。这些实施例在ProducerTm 300mm处理室中进行,该装置包括具有双片石英工艺套件的固态双频RF匹配单元,均由California,Santa Clara的Applied Materials,Inc制造并出售。
测试样品如下制备。按如下方法在硅衬底上沉积电介质叠层。所述衬底包括硅衬底,硅衬底上布置有约1000的氧化物,氧化物上布置有约250的钽,钽上布置有约4500的铜,铜层上布置有约2000的硅碳氮化物,在硅碳氮化物层上沉积约2000的硅氧碳化物。硅碳氮化物沉积和硅氧碳化物沉积可以采用单一连续的等离子体或包括两个或多个生成的等离子体。
通过以下方法来沉积硅氧碳化物层:以160sccm的流率将氧引入处理室;以约2900毫克/分钟(mgm)(对于OMCTS,相当于约226sccm)的流率引入八甲基环四硅氧烷;以约1000sccm的流率引入氦;保持室处于约350℃的衬底温度;保持室压力为约5Torr;在距衬底表面约450密耳处设置气体分布器;在13.56MHz下施加约500W、在356KHz下施加约150W的RF功率。
按如下方法对测试样品进行粘附性测试。在测试样品上沉积约120μm至约150μm的具有已知的层离特性的环氧材料。在环氧材料层上沉积硅层。然后将测试样品在约190℃下烘焙或固化一小时,之后切成1cm见方的样品并用液氮冷却至-170℃。然后观察该样品以确定层离,在给定温度下,层离发生在最薄弱的层间界面处。给定温度下的环氧材料的收缩与造成剥离所需的力有关。根据此观察,可定量计算粘附力。粘附力(GC)基于式
计算,其中h为环氧层厚度,σ为残余应力。测得的上述未处理或未改性的叠层的粘附力GC在约3.01的介电常数下为约3J·m2,层离发生在硅碳氮化物与硅氧碳化物的界面。
对于样品1,在沉积硅氧碳化物层之前,通过以下方法对硅碳氮化物层进行氦等离子体处理:以约1500sccm的流率向处理室提供氦;保持室压力为约5Torr;保持衬底温度为约350℃;在距衬底表面约450密耳处设置气体分布器;通过在约13.56MHz的高频下施加15秒的约300W的RF功率水平来生成等离子体。测得的样品1的氦处理叠层的粘附力GC在约3.03的介电常数下为约3.8J·m2,硅碳氮化物与硅氧碳化物的界面处未发生层离。
对于样品2,在沉积硅氧碳化物层之前,对硅碳氮化物层进行氦等离子体处理和初始层沉积,其中氦等离子体处理方法与样品1相同,初始层沉积方法如下:以500sccm的流率将氧引入处理室;以约500毫克/分钟(mgm)(相当于约39sccm)的流率引入八甲基环四硅氧烷;以约4800sccm的流率引入氦;保持室处于约350℃的衬底温度下;保持室压力为约5Torr;在距衬底表面约350密耳处设置气体分布器;在13.56MHz下施加约500W、在356KHz下施加约150W的RF功率。测得的样品2的氦处理叠层的粘附力GC在约3.06的介电常数下为约5.5J·m2,硅碳氮化物与硅氧碳化物的界面处未发生层离。
层沉积:
硅氧碳化物层
硅氧碳化物层通常包含硅、碳以及约15原子%或更高的氧。本文所述的掺杂氧的硅碳化物包含小于约15原子%的氧。优选的硅氧碳化物层包含对低介电常数和阻挡性质有贡献的硅-氧键和硅-碳键。沉积层的碳含量为约5-30原子%(不包括氢原子),优选约10-20原子%(不包括氢原子)。整个沉积层可含有C-H或C-F键,从而为硅氧碳化物层提供疏水性。硅氧碳化物层还可含有氢、氮或其组合。
通过氧化有机硅化合物来沉积硅氧碳化物层,有机硅化合物包括本文所述的含氧有机硅化合物和含氮有机硅化合物。在本发明的一个优选方面,通过使含三个或更多烷基的有机硅化合物与含臭氧的氧化气体反应来沉积硅氧碳化物层。如果有机硅化合物包含氧,则可在无氧化剂的条件下沉积硅氧碳化物层。优选的有机硅化合物包括例如:
三甲基硅烷 (CH3)3-SiH
四甲基硅烷 (CH3)4-Si
1,1,3,3-四甲基二硅氧烷 (CH3)2-SiH-O-SiH-(CH3)2
六甲基二硅氧烷 (CH3)3-Si-O-Si-(CH3)3
2,2-双(1-甲基二硅氧烷基)丙烷 (CH3-SiH2-O-SiH2-)2-C(CH3)2
1,3,5,7-四甲基环四硅氧烷 -(-SiHCH3-O-)4-(环状)
八甲基环四硅氧烷 -(-Si(CH3)2-O-)4-(环状)
1,3,5,7,9-五甲基环五硅氧烷 -(-SiHCH3-O-)5-(环状)
及其氟化衍生物
在沉积硅氧碳化物层过程中,有机硅化合物优选通过与氧(O2)、臭氧(O3)、氧化亚氮(N2O)、一氧化碳(CO)、二氧化碳(CO2)、水(H2O)或其组合(其中优选氧)反应而被氧化。当臭氧用作氧化气体时,臭氧生成器通常将气体源中的约15wt%的氧转化为臭氧,余下的通常为氧。然而,依赖于所需的臭氧量和所用臭氧生成设备的类型,臭氧浓度可以提高或降低。含有氧的有机硅化合物可被分解以提供氧。在沉积硅氧碳化物层过程中,衬底被保持在约-20℃至约500℃,优选被保持在约170℃至约180℃。
对于硅氧碳化物层的等离子体增强沉积,沉积有机硅材料所用的功率密度为约0.003W/cm2至约6.4W/cm2,即对于200mm的衬底,施加约1W至约2000W的RF功率水平。优选地,RF功率水平为约300W至约1700W。以约0.01MHz至约300MHz的频率提供RF功率。可以连续地或以短周期提供RF功率,其中,功率在所述水平开启,开启周期小于约200Hz,并且开启周期总共占总工作周期的约10%至约50%。在以下更详细描述的衬底处理系统中进行低介电常数层的沉积工艺。硅氧碳化物层的沉积可以连续进行,或者可以有中断,例如更换处理室或提供冷却时间以提高孔隙率。
或者,可以采用双频系统来沉积硅氧碳化物材料。混合双频RF功率源可提供约10MHz至约30MHz范围的高频率(例如约13.56MHz)以及约100KHz至约500KHz范围的低频率(例如约350KHz)。混频RF功率施加的例子可包括第一RF功率和至少第二RF功率,其中,第一RF功率的频率范围为约10MHz至约30MHz,功率范围为约200W至约1000W;第二PF功率的频率范围为约100KHz至约500KHz,功率范围为约1W至约200W。第二RF功率与总混频功率的比率优选小于约0.2至1.0。
在一个方面,环状有机硅化合物和脂族有机硅化合物与足够量的氧化气体反应,以在半导体衬底上沉积低介电常数层,其中环状有机硅化合物包含至少一个硅-碳键。脂族有机硅化合物含有硅-氢键和硅-氧键,优选含有硅-氢键。例如,环状有机硅化合物可以是1,3,5,7-四甲基环四硅氧烷或八甲基环四硅氧烷,脂族有机硅化合物可以是三甲基硅烷或1,1,3,3-四甲基二硅氧烷。
在另一个方面,环状有机硅化合物与脂族有机硅化合物均含有硅-氢键。例如,在施加RF功率的同时,将1,3,5,7-四甲基环四硅氧烷与三甲基硅烷或1,1,3,3-四甲基二硅氧烷混合并氧化。
在等离子体增强沉积的一种实施方式中,氧或含氧化合物被分解,以提高沉积层的反应性并且使沉积层获得所需的氧化。RF功率被耦合至沉积室以促进化合物的分解。在化合物进入沉积室之前,也可在微波室内将其分解。
尽管沉积优选发生在单个沉积室中,但是硅氧碳化物层的沉积也可在例如两个或多个沉积室中顺序进行,从而在沉积过程中对层进行冷却,上述沉积室可例如是DxZTM处理室或ProducerTm处理室,二者均可从California,Santa Clara的Applied Materials,Inc购得。此外,通过使用选择性前体以及控制处理参数和处理气体的组成,可以在相同的室内原位沉积且顺序沉积硅氧碳化物层和硅碳化物层。例如,通过在硅碳化物的沉积中使用三甲基硅烷及氨以形成掺杂氮的硅碳化物,随后在硅氧碳化物材料的沉积过程中使用臭氧,可以沉积硅碳化物层和硅氧碳化物层。
硅碳化物层
通过使有机硅化合物反应来沉积硅碳化物层,从而形成含碳-硅键且介电常数小于约4的电介质层。硅碳化物层优选为无定型氢化的硅碳化物。可以在惰性气体、氢气和二者的等离子体中沉积硅碳化物层。硅碳化物电介质层可以是掺杂的硅碳化物层。硅碳化物层可以作为阻挡层沉积在与导电材料或电介质层相邻的位置,或者硅碳化物电介质层可以是沉积在一个或多个电介质层之间的蚀刻终止层。
用于沉积硅碳化物的合适的有机硅化合物的例子优选包括以下结构:
其中,R包括有机官能团,包括烷基、烯基、环己烯基、芳基及其官能衍生物。有机前体可具有多于一个的与硅原子连接的R基,本发明可使用具有或不具有Si-H键的有机硅前体。
有机硅化合物包括脂族有机硅化合物、环状有机硅化合物或其组合,其具有至少一个硅-碳键并且结构中可选地包含氧。环状有机硅化合物通常具有包含三个或更多个硅原子的环。脂族有机硅化合物具有包含一个或多个硅原子和一个或多个碳原子的直链或支链结构。可购得的脂族有机硅化合物包括在硅原子之间不含氧的有机硅烷,而对于掺杂氧的硅碳化物层,则包括在两个或更多个硅原子之间含有氧的有机硅氧烷。在本发明中,有机硅化合物的氟化衍生物也可用于沉积硅碳化物和硅氧碳化物层。
合适的脂族和环状有机硅化合物的例子包括例如一种或多种下列化合物:
甲基硅烷 CH3-SiH3
二甲基硅烷 (CH3)2-SiH2
三甲基硅烷(TMS) (CH3)3-SiH
乙基硅烷 CH3-CH2-SiH3
二硅烷基甲烷 SiH3-CH2-SiH3
双(甲基硅烷基)甲烷 CH3-SiH2-CH2-SiH2-CH3
1,2-二硅烷基乙烷 SiH3-CH2-CH2-SiH3
1,2-双(甲基硅烷基)乙烷 CH3-SiH2-CH2-CH2-SiH2-CH3
2,2-二硅烷基丙烷 SiH3-C(CH3)2-SiH3
1,3,5-三硅烷基-2,4,6-三亚甲基 -(-SiH2CH2-)3-(环状)
以上所列仅为示例性,而不应当理解或解释为限制本发明的范围。
含有机硅化合物的苯基也可用于沉积硅碳化物材料,其通常包括以下结构:
其中,R为苯基。例如,合适的含苯基的有机硅化合物通常包括式SiHa(CH3)b(C6H5)c,其中a为0-3,b为0-3,c为1-4,且a+b+c=4。从此式得出的合适前体的例子包括二苯基硅烷、二甲基苯基硅烷、二苯基甲基硅烷、苯基甲基硅烷及其组合。优选使用的是b为1-3且c为1-3的含苯基的有机硅化合物。最优选的作为阻挡层沉积的有机硅化合物包括具有式SiHa(CH3)b(C6H5)c的有机硅化合物,其中a为1或2、b为1或2且c为1或2的有机硅化合物。优选的前体的例子包括二甲基苯基硅烷和二苯基甲基硅烷。
通常,在包含较具惰性的气体(例如氮(N2))和稀有气体(例如氦和氩)的等离子体中使有机硅化合物反应。沉积的硅碳化物层的介电常数为约5或更小,掺杂的硅碳化物层的介电常数为约3或更小。
在一种实施方式中,通过以约10毫克/分钟(mgm)至约5000毫克/分钟(mgm)的流率将三甲基硅烷供给至等离子体处理室来沉积优选的硅碳化物层。对于不同的有机硅化合物,由于从毫克/分钟到标准立方分米/分钟(sccm)的转换可能存在差异,因此优选使用毫克/分钟。惰性气体(例如氦、氩或其组合)也被以约50sccm至约5000sccm的流率供给至处理室中。室压力被保持在约100mTorr至约15Torr。在沉积过程中,衬底表面温度被保持在约100℃至约450℃。沉积硅碳化物层的工艺的一个例子被2003年3月25日授权的美国专利No.6537733所公开,通过引用将其与本发明的权利要求和说明书一致的部分包含于此。
硅碳化物层也可以是含氧、氮、硼、磷或其组合的掺杂的硅碳化物层。掺杂的硅碳化物通常包含少于约15原子百分比(原子%)或更少的一种或多种掺杂物。掺杂物可用在处理气体中,掺杂物与有机硅化合物的比率为约1∶5或更小,例如约1∶5至约1∶100。
在反应过程中可用氧源或氮源来形成掺杂氧和/或掺杂氮的硅碳化物层。氧源的例子包括氧化气体(例如氧、臭氧、一氧化碳、二氧化碳、氧化亚氮)和含氧的有机硅前体或其组合,例如一氧化碳与含氧的有机硅前体。掺杂氧的硅碳化物通常包含少于约15原子%的氧,优选约10原子%或更少的氧。
含氧有机硅化合物包括例如:
二甲基二甲氧基硅烷 (CH3)2-Si-(OCH3)2
1,3-二甲基二硅氧烷 CH3-SiH2-O-SiH2-CH3
1,1,3,3-四甲基二硅氧烷(TMDSO) (CH3)2-SiH-O-SiH-(CH3)2
六甲基二硅氧烷(HMDS) (CH3)3-Si-O-Si-(CH3)3
1,3-双(硅烷基亚甲基)二硅氧烷 (SiH3-CH2-SiH2-)2-O
双(1-甲基二硅氧烷基)甲烷 (CH3-SiH2-O-SiH2-)2-CH2
2,2-双(1-甲基二硅氧烷基)丙烷 (CH3-SiH2-O-SiH2-)2-C(CH3)2
2,4,6,8-四甲基环四硅氧烷(TMCTS) -(-SiHCH3-O-)4-(环状)
八甲基环四硅氧烷(OMCTS) -(-Si(CH3)2-O-)4-(环状)
2,4,6,8,10-五甲基环五硅氧烷 -(-SiHCH3-O-)5-(环状)
1,3,5,7-四硅烷基-2,6-二氧-4,8-二亚甲基 -(-SiH2-CH2-SiH2-O-)2-(环状)
六甲基环三硅氧烷 -(-Si(CH3)2-O-)3-(环状)
1,3-二甲基二硅氧烷 CH3-SiH2-O-SiH2-CH3
六甲氧基二硅氧烷(HMDOS) (CH3O)3-Si-O-Si-(OCH3)3
及其氟化衍生物
掺杂氮的硅碳化物可包含高达20原子%的氮,并可通过添加含氮化合物来沉积,含氮化合物包括例如氨、氮气、氮气和氢气的混合物以及具有Si-N-Si键合基团的化合物,例如硅氮烷。合适的硅氮烷前体包括脂族化合物(例如六甲基二硅氮烷和二乙烯基四甲基二硅氮烷)和环状化合物(例如六甲基环三硅氮烷)。
例如,通过以约50sccm至约10000sccm的流率将氧源和/或氮源或气体掺杂物引入处理室,可以沉积掺杂的硅碳化物层。例如,通过在沉积硅碳化物层时引入氮源(例如氨、氮、氮和氢的混合物,或其组合),可以沉积含氮的或掺杂氮的硅碳化物层。
通过在沉积过程中将膦(PH3)或硼烷(BH3)或其硼烷衍生物(例如二硼烷(B2H6))引入处理室,可以进行低k硅碳化物层的磷和/或硼掺杂。掺杂物可降低沉积的硅碳化物材料的介电常数。可以以约50sccm至约10000sccm的流率将磷和/或硼掺杂物引入处理室。
处理气体中也可使用有机化合物(例如脂族烃化合物)来提高沉积的硅碳化物材料的碳含量。合适的脂族烃化合物包括具有1至约20个相邻的碳原子的化合物。烃化合物可包含通过单键、双键和三键的任意组合而结合的相邻的碳原子。
沉积含氮硅碳化物层的工艺的例子被2004年7月20日授权的美国专利No.6764958和2003年3月25日授权的美国专利No.6537733所公开,通过引用将其与本发明的权利要求和说明书一致的部分包含于此。沉积含氧硅碳化物层的工艺的例子被2002年7月15日授权的美国专利No.10/196498所公开,通过引用将其与本发明的权利要求和说明书一致的部分包含于此。沉积掺杂硼和/或磷的硅碳化物层的工艺的例子被2004年9月14日授权的美国专利No.6790788所公开,通过引用将其与本发明的权利要求和说明书一致的部分包含于此。
通常,通过与其上沉积硅碳化物层的衬底相距约200mm至约600mm的气体分布板,将有机硅化合物、惰性气体和可选的掺杂物引入处理室。可用单频和双频RF功率源来施加功率。例如,来自13.56MHz的单频RF功率源的功率被供给至室10中,以形成功率密度为约0.003W/cm2至约3.2W/cm2,或者对于200mm的衬底为约1W至约1000W功率水平的等离子体。供给至处理室以生成等离子体的功率密度优选为0.9W/cm2至约2.3W/cm2,或者对于200mm的衬底为约300W至约700W的功率水平。
或者,可采用双频系统来沉积硅碳化物材料。混合RF功率的双频源提供约10MHz至约30MHz(例如约13.56MHz)的高频功率以及约100KHz至约500KHz(例如约350KHz)的低频功率。混频RF功率施加的例子可包括第一RF功率和至少第二RF功率,其中,第一RF功率的频率范围为约10MHz至约30MHz,功率范围为约200W至约1000W;第二PF功率范围的频率为约100KHz至约500KHz,功率范围为约1W至约200W。第二RF功率与总混频功率的比率优选小于约0.2∶1.0。
此外,气体混合物中的硅源与掺杂物的比率应为约1∶1至约100∶1。当在可从California,Santa Clara的Applied Materials,Inc购得的沉积室中对200mm的衬底实施时,上述工艺参数提供了100/min至约3000/min的硅碳化物层沉积速率。
本文所述的沉积硅碳化物层的实施方式用于说明本发明,所述的具体实施方式不应用于限制本发明的范围。本发明还涵盖其他用于沉积硅碳化物层的工艺和材料。
虽然上面所述的涉及本发明的实施方式,但是可以设计本发明的其它和更多的实施方式,而不偏离本发明的基本范围,本发明的基本范围有所附权利要求确定。
Claims (20)
1.一种处理衬底的方法,包括:
将所述衬底置于处理室中,其中所述衬底具有包含至少硅和碳的阻挡层;
以有机硅化合物与氧化气体的第一比率将有所述机硅化合物和所述氧化气体引入所述处理室;
生成所述氧化气体与所述有机硅化合物的等离子,以在所述阻挡层上形成初始层;
以大于所述第一比率的有机硅化合物与氧化气体的第二比率将所述有机硅化合物和所述氧化气体引入所述处理室;以及
沉积相邻于所述电介质初始层的第一电介质层,其中所述电介质层包含硅、氧和碳并且具有约3或更小的介电常数。
2.如权利要求1的方法,其中所述阻挡层还包含氧或氮。
3.如权利要求1的方法,其中所述有机硅化合物选自三甲基硅烷、2,4,6,8-四甲基环四硅氧烷、八甲基环四硅烷及其组合,并且所述氧化气体选自氧、臭氧、一氧化碳、二氧化碳、氧化亚氮及其组合。
4.如权利要求1的方法,其中所述沉积所述初始层包括由双频RF功率源生成等离子体。
5.如权利要求1的方法,其中所述沉积所述第一电介质层包括由双频RF功率源生成等离子体。
6.如权利要求1的方法,其中所述有机硅化合物与氧化气体的第一比率包括约1∶1的比率,并且所述有机硅化合物与氧化气体的第二比率包括大于或等于约10∶1的比率。
7.如权利要求1的方法,还包括与所述有机硅化合物和所述氧化气体一起引入惰性气体。
8.如权利要求1的方法,还包括在引入所述氧化气体和所述有机硅化合物之前,将所述阻挡层暴露于惰性气体、氧化气体或两者的等离子体中。
9.一种处理衬底的方法,包括:
将所述衬底置于处理室中,其中所述衬底具有包含硅、氮和碳的阻挡层;
将惰性气体引入所述处理室;
由单频RF功率源生成第一等离子体,以改性所述阻挡层的表面;
以约1∶1的比率将有机硅化合物和氧化气体引入所述处理室;
由双频RF功率源生成第二等离子体,以在所述阻挡层上形成初始层;
以大于或等于约10∶1的比率将所述有机硅化合物和所述氧化气体引入所述处理室;以及
沉积相邻于所述电介质初始层的第一电介质层,其中所述电介质层包含硅、氧和碳并且具有约3或更小的介电常数。
10.如权利要求9的方法,其中所述惰性气体包括氦、氩或其组合。
11.如权利要求9的方法,其中所述有机硅化合物选自三甲基硅烷、2,4,6,8-四甲基环四硅氧烷、八甲基环四硅烷及其组合,并且所述氧化气体选自氧、臭氧、一氧化碳、二氧化碳、氧化亚氮及其组合。
12.如权利要求11的方法,其中与所述有机硅化合物一起引入惰性气体。
13.一种处理衬底的方法,包括:
将所述衬底置于处理室中,其中衬底具有包含至少硅和碳的阻挡层;
将氧化气体引入所述处理室;
生成所述氧化气体的等离子体,并且处理所述阻挡层的表面;
以第一流率引入有机硅化合物;
由所述氧化气体和所述有机硅化合物在所述阻挡层上沉积初始层;
以大于所述第一流率的第二流率引入所述有机硅化合物;以及
由所述氧化气体和所述有机硅化合物沉积相邻于所述电介质初始层的第一电介质层,其中所述电介质层包含硅、氧和碳并且具有约3或更小的介电常数。
14.如权利要求13所述的方法,其中所述阻挡层还包含氧或氮。
15.如权利要求13所述的方法,其中所述有机硅化合物选自三甲基硅烷、2,4,6,8-四甲基环四硅氧烷、八甲基环四硅烷及其组合,并且所述氧化气体选自氧、臭氧、一氧化碳、二氧化碳、氧化亚氮及其组合。
16.如权利要求13所述的方法,其中所述生成所述氧化气体的等离子体包括由单频RF功率源生成等离子体,并且所述沉积所述初始层包括由双频RF功率源生成等离子体。
17.如权利要求13的方法,其中与所述有机硅化合物一起引入惰性气体。
18.如权利要求13的方法,其中所述沉积所述初始层包括存在的所述有机硅化合物与氧化气体的比率为约1∶1。
19.如权利要求13的方法,其中所述沉积所述第一电介质层包括存在的所述有机硅化合物与氧化气体的比率大于或等于约10∶1。
20.一种处理衬底的方法,包括:
将所述衬底置于处理室中,其中衬底具有包含至少硅和碳的阻挡层;
将氧化气体引入所述处理室;
生成所述氧化气体的等离子体,并且在所述阻挡层上形成初始层;
将有机硅化合物引入所述处理室;
使所述有机硅化合物与所述氧化气体反应;以及
沉积相邻于所述初始层的第一电介质层,其中所述电介质层包含硅、氧和碳并且具有约3或更小的介电常数。
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102414341A (zh) * | 2009-05-04 | 2012-04-11 | 波音公司 | 涂层方法 |
CN102468228A (zh) * | 2010-11-19 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
CN105336674A (zh) * | 2014-07-28 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | 互连结构及其形成方法 |
CN105336674B (zh) * | 2014-07-28 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | 互连结构及其形成方法 |
CN106158729A (zh) * | 2015-04-08 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN106158729B (zh) * | 2015-04-08 | 2019-12-03 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
Also Published As
Publication number | Publication date |
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KR101046467B1 (ko) | 2011-07-04 |
US7459404B2 (en) | 2008-12-02 |
US20050202685A1 (en) | 2005-09-15 |
US7030041B2 (en) | 2006-04-18 |
US20060189162A1 (en) | 2006-08-24 |
WO2005091348A1 (en) | 2005-09-29 |
KR20070004847A (ko) | 2007-01-09 |
CN100483645C (zh) | 2009-04-29 |
TWI285927B (en) | 2007-08-21 |
TW200605221A (en) | 2006-02-01 |
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